CN115757001A - Mode adjusting method of memory, memory and electronic equipment - Google Patents
Mode adjusting method of memory, memory and electronic equipment Download PDFInfo
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- CN115757001A CN115757001A CN202111026836.5A CN202111026836A CN115757001A CN 115757001 A CN115757001 A CN 115757001A CN 202111026836 A CN202111026836 A CN 202111026836A CN 115757001 A CN115757001 A CN 115757001A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a mode adjustment method of a memory, the memory and an electronic device, wherein the mode adjustment method of the memory comprises the following steps: triggering the memory to enter a preset mode; detecting the voltage condition of a preset signal line; judging whether the voltage condition meets a preset voltage condition or not; if not, exiting the preset mode. The method can reduce the probability of memory initialization failure caused by mistaken touch entering the preset mode.
Description
Technical Field
The present disclosure relates to the field of storage technologies, and in particular, to a mode adjustment method for a memory, and an electronic device.
Background
At present, electronic storage devices are widely applied to various aspects of people's life, the types of SD cards become more and more, the functions become more and more complex, and LVS (Low Voltage Signaling) is an important function in development; when the device side supports the SD card with the LVS function, the device side may mistakenly enter the LVS mode under the condition that the SD card identification is inaccurate according to the condition triggered by the SD protocol LVS, thereby causing the initialization mode of the device side and the SD card side to be mismatched, and causing the disc loading failure of the SD card.
Disclosure of Invention
The application provides a mode adjustment method of a memory, the memory and an electronic device.
In order to solve the technical problem, the technical scheme adopted by the application comprises the following steps: a mode adjustment method of a memory is provided, and the method comprises the following steps: triggering the memory to enter a preset mode; detecting the voltage condition of a preset signal line; judging whether the voltage condition meets a preset voltage condition or not; if not, exiting the preset mode.
Wherein, detect the voltage condition of presetting the signal line, include: detecting a first voltage value of a preset signal line in a first preset time period after the memory enters a preset mode; judging whether the voltage condition meets the preset voltage condition or not, including: judging whether the first voltage value is equal to a first preset voltage value or not, wherein the first preset voltage value represents a voltage value in a first preset time period after an equipment end connected with the memory enters a preset mode; and if not, determining that the voltage condition does not meet the preset voltage condition.
Wherein, judge whether the voltage condition satisfies the preset voltage condition, still include: if the first voltage value is equal to the first preset voltage value, detecting a second voltage value of a preset signal line in a second preset time period after the memory enters the preset mode; judging whether the second voltage value is equal to a second preset voltage value, wherein the second preset voltage value represents the voltage value in a second preset time period after the equipment end enters a preset mode, the first preset time period is different from the second preset time period, and the first preset voltage value is different from the second preset voltage value; and if the second voltage value is not equal to the second preset voltage value, determining that the voltage condition does not meet the preset voltage condition.
The preset signal line comprises one or more of a command line and at least one data line controlled by an equipment end, wherein the equipment end is connected with the memory; and/or the voltage condition of the preset signal line is detected by a voltage monitoring circuit of the memory.
Wherein after exiting the preset mode, the method further comprises: switching the mode of the memory into an SD mode, wherein the working voltage of the SD mode is higher than that of a preset mode; in the SD mode, the memory is initialized.
The method for entering the preset mode in response to the triggering of the equipment end comprises the following steps: after the memory is powered on, judging whether the voltage of the clock signal line is pulled high or not; and entering a preset mode in response to the triggering of the equipment side.
The preset mode is a low voltage mode.
In order to solve the technical problem, the technical scheme adopted by the application comprises the following steps: a memory is provided having stored thereon program instructions that, when executed by the memory, implement a mode adjustment method for the memory.
The memory comprises a voltage monitoring circuit, and the voltage monitoring circuit is used for detecting the voltage condition of a preset signal line when the memory is determined to be in a preset mode.
In order to solve the technical problem, the technical scheme adopted by the application comprises the following steps: an electronic device is provided, which comprises the memory.
Different from the prior art, the beneficial effects of this application lie in: the voltage condition of the preset signal line is detected under the condition that the memory enters the preset mode, then whether the voltage value meets the preset voltage condition or not is judged, and if the voltage value does not meet the preset voltage condition, the preset mode exits, so that the condition that the memory fails to initialize due to the fact that the memory enters the preset mode through error touch can be reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flowchart illustrating a method for adjusting a mode of a memory according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a change in voltage condition of each signal line during the recognition and triggering process of a preset mode of the memory according to an embodiment of the method for adjusting a mode of a memory of the present application;
FIG. 3 is another flow chart illustrating an embodiment of a method for adjusting a mode of a memory according to the present application;
FIG. 4 is a schematic structural diagram of an embodiment of the memory of the present application;
fig. 5 is a schematic structural diagram of an embodiment of an electronic device according to the present application.
Detailed Description
The following describes in detail the embodiments of the present application with reference to the drawings attached hereto.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, interfaces, techniques, etc. in order to provide a thorough understanding of the present application.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship. Further, "plurality" herein means two or more than two. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of a, B, and C, and may mean including any one or more elements selected from the group consisting of a, B, and C.
The application provides a mode adjustment method of a memory. Referring to fig. 1 in detail, fig. 1 is a schematic flowchart illustrating a mode adjustment method of a memory according to an embodiment of the present disclosure. As shown in fig. 1, the method for adjusting the mode of the memory according to the embodiment may specifically include the following steps:
step S11: the memory is triggered to enter a preset mode.
The memory is connected to the device side. The triggering of the device may be due to voltage value jitter of a signal line connected to the device. The specific triggering manner can be referred to the relevant contents in the SD card protocol, and will not be described herein too much. The mode of the memory may be various, including a preset mode and other modes other than the preset mode.
Step S12: and detecting the voltage condition of the preset signal line.
Wherein, the voltage condition of the preset signal line can be detected by using a voltage monitoring circuit in the memory. The preset signal line may be a signal line between the memory and the device terminal. Among the signal lines between the memory and the device terminal, some signal lines have their voltages controlled by the memory and some signal lines have their voltages controlled by the device terminal. Alternatively, the preset signal line may be a signal line whose voltage is controlled by the device terminal. The disclosed embodiment selects to use a voltage detection circuit to detect the voltage of a preset signal line controlled by a device terminal. The voltage value of the preset signal line is controlled by the equipment terminal, that is, the mode of the equipment terminal can be detected by judging the voltage value of the preset signal line.
Step S13: and judging whether the voltage condition meets the preset voltage condition or not.
Specifically, it may be determined whether the voltage value of the preset signal line is equal to the preset voltage value.
Step S14: if not, exiting the preset mode.
Wherein exiting the predetermined mode includes switching to another mode. For example, the current operating voltage is switched from the operating voltage specified by the preset model to the operating voltage of the other mode.
According to the scheme, under the condition that the memory enters the preset mode, the voltage condition of the preset signal line is detected, whether the voltage value meets the preset voltage condition is judged, and if not, the preset mode exits, so that the condition that the initialization of the memory fails due to the fact that the memory enters the preset mode through error touch can be reduced.
In some disclosed embodiments, the manner of detecting the voltage condition of the preset signal line may be: the method comprises the steps of detecting a first voltage value of a preset signal line in a first preset time period after a memory enters a preset mode. Specifically, the voltage condition of the preset signal line is detected by a voltage monitoring circuit of the memory. The manner of determining whether the voltage condition satisfies the preset voltage condition may be: and judging whether the first voltage value is equal to the first preset voltage value or not. The first preset voltage value represents a voltage value in a first preset time period after the device end connected with the memory enters the preset mode. And if not, determining that the voltage condition does not meet the preset voltage condition. That is, in a first preset time period after the device terminal connected to the memory enters the preset mode, the voltage of the preset signal line is a first preset voltage. When the memory enters the preset mode, it is detected that the first voltage value of the preset signal line is not equal to the first preset voltage value, and it indicates that the device end does not enter the preset mode. That is, the current mode of the memory is different from the mode on the device side. Of course, if the first voltage value is equal to the first preset voltage value, the voltage condition of the preset signal line is considered to satisfy the preset voltage condition, that is, the device side also enters the preset mode.
In some disclosed embodiments, the manner of detecting the voltage condition of the preset signal line may also be: and detecting a second voltage value of the preset signal line in a second preset time period after the memory enters the preset mode. The first preset time period is different from the second preset time period. And, the manner of judging whether the voltage condition satisfies the preset voltage condition may be: and judging whether the second voltage value is equal to the second preset voltage value or not. And if the second voltage value is not equal to the second preset voltage value, determining that the voltage condition does not meet the preset voltage condition. And the second preset voltage value represents a voltage value in a second preset time period after the equipment end enters the preset mode. That is, in a second preset time period after the device enters the preset mode, the voltage of the signal line is preset to be a second preset voltage value. Since the voltage of the preset signal line is controlled by the device terminal, when the second voltage value is detected to be unequal to the second preset voltage value, it is indicated that the device segment does not enter the preset mode. Of course, if the second voltage value is equal to the second preset voltage value, the voltage condition of the preset signal line is considered to satisfy the preset voltage condition, that is, the device side also enters the preset mode. The first preset voltage value is different from the second preset voltage value. Optionally, the ending time point of the first preset time period is the starting time point of the second preset time period. The second preset voltage value is different from the first preset voltage value. Further, the first preset voltage value is smaller than the second preset voltage value.
In other disclosed embodiments, the manner of determining whether the voltage condition satisfies the preset voltage condition may further be: and if the first voltage value is equal to the first preset voltage value, detecting a second voltage value of a preset signal line in a second preset time period after the memory enters the preset mode. And then judging whether the second voltage value is equal to the second preset voltage value or not. And if the second voltage value is not equal to the second preset voltage value, determining that the voltage condition does not meet the preset voltage condition. And the second preset voltage value represents a voltage value within a second preset time period after the equipment end enters the preset mode. That is, in a second preset time period after the device enters the preset mode, the voltage of the signal line is preset to be a second preset voltage value. Since the voltage of the preset signal line is controlled by the device terminal, when the second voltage value is detected to be unequal to the second preset voltage value, it is indicated that the device segment does not enter the preset mode. Of course, if the second voltage value is equal to the second preset voltage value, the voltage condition of the preset signal line is considered to satisfy the preset voltage condition, that is, the device side also enters the preset mode. The first preset time period is different from the second preset time period, and optionally, the ending time point of the first preset time period is the starting time point of the second preset time period. The first preset voltage value is different from the second preset voltage value. Further, the first preset voltage value is smaller than the second preset voltage value. Whether the voltage values of the preset signal lines in the two time periods meet the conditions or not is detected, so that whether the voltage condition of the preset signal lines meets the preset voltage condition or not is judged, and the accuracy of the judgment result can be improved.
In some disclosed embodiments, the preset mode is a low voltage mode. The operating voltage of the memory in the low voltage mode is generally about 1.8V.
Wherein, the step S11 includes the following steps: after the memory is powered on, whether the voltage of the clock signal line is pulled high is judged. The preset mode is entered in response to the voltage of the clock signal line being pulled high. The preset signal line comprises one or more of a command line and at least one data line controlled by a device end, wherein the device end is connected with the memory.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating voltage condition changes of signal lines during the memory default pattern recognition and triggering process according to an embodiment of the memory mode adjustment method of the present application. As shown in FIG. 2, the data lines controlled by the device side include a first data line DAT [0], a second data line DAT [1], and a fourth data line DAT [3]. Wherein the voltage of the second data line DAT [2] is controlled by the memory. Fig. 2 shows a voltage change of each signal line in the case where no erroneous touch has occurred. Wherein, a memory power-on phase is between t1 and t 2. In the period from t3 to t4, the memory detects that the voltage of the clock signal line CLK is pulled high, indicating that the device has a signal triggering entry into the default mode. the stages t4 to t5 are memory identification preparation stages. The memory and device terminals then enter a preset mode from t5, where the preset mode is referred to as a low voltage mode (LVS mode). The period from t6 to t7 is a first preset time period, and the voltage on the command line CMD and the data line controlled by the device terminal is 0V, that is, the first preset voltage value is 0. If the first voltage value of the command line CMD or the corresponding data line detected in step S12 is not equal to 0, it is determined that the voltage condition of the predetermined signal line does not satisfy the predetermined voltage condition. In fig. 2, the second predetermined time period may be t7 and t8 phases, and the command line will be pulled up to 1.8V in the t7 and t8 phases, i.e. the second predetermined voltage value is 1.8V. If the voltage on the command line CMD controlled by the device end is detected to be not equal to 1.8V after the memory enters the preset mode in response to the trigger of the device end, the voltage condition of the command line CMD is considered not to meet the preset voltage condition. In the embodiment of the disclosure, it is first detected whether the first voltage value of the command line CMD between t6 and t7 is equal to 0, if so, it is continuously detected whether the first voltage value of the command line CMD between t7 and t8 is equal to 1.8V, if not, it is determined that the voltage condition of the preset signal line does not satisfy the preset voltage condition, and the memory exits the preset mode. If the data line of the device-side control voltage is detected, the first preset time period may be a period from t6 to t7, and the second preset time period may be a period from t8 to t 9. The voltage detection circuit can detect whether the voltage value of one preset signal line meets the corresponding preset voltage condition or not, and can also detect whether the voltage values of a plurality of preset signal lines all meet the corresponding preset voltage condition or not. The data line to be detected is not particularly limited. By detecting the voltage value conditions of a plurality of signals of the equipment terminal control voltage at each stage, the accuracy of judging whether the voltage conditions meet the preset voltage conditions can be improved.
Optionally, after exiting the preset mode, the mode of the memory is switched to the SD mode. The working voltage of the SD mode is higher than that of the preset mode. Specifically, the operating voltage of the memory in SD mode is 3.3V. Then, in the SD mode, the memory is initialized. The manner of initializing the memory can be referred to in the general art, and will not be described herein too much.
In some application scenarios, when the device side supports the memory in the LVS mode, due to differences developed in hardware, a signal line of the memory is easily affected by the device side to cause abnormal jitter, and according to a trigger condition of the LVS mode in the SD protocol, under a condition that the signal line is unstable and the memory identification is not accurate, the memory may mistakenly enter the LVS mode, so that the device side is not matched with the memory initialization mode, and the disk loading of the memory fails. According to the technical scheme provided by the embodiment of the disclosure, the preset signal line can be judged after the memory enters the LVS mode, so that the conclusion whether the device end also enters the LVS mode is obtained, if the device end also enters the LVS mode, the memory keeps the LVS mode and is initialized in the mode, and if the device end does not enter the LVS mode, the memory exits the LVS mode, is switched to the SD mode and is initialized.
For better understanding of the technical solutions provided by the embodiments of the present disclosure, please refer to the following examples. Referring to fig. 3, fig. 3 is another flow chart illustrating an embodiment of a method for adjusting a mode of a memory according to the present application. As shown in fig. 3, the method for adjusting the mode of the memory according to the embodiment of the present disclosure includes the following steps:
step S21: the memory is triggered to enter a preset mode.
The manner of the memory triggering to enter the preset mode is as described above, and is not described herein again.
Step S22: the method comprises the steps of detecting a first voltage value of a preset signal line in a first preset time period after a memory enters a preset mode.
Wherein the first voltage value of the preset signal line may be detected using a voltage monitoring circuit in the memory. The specific manner is as described above, and is not described herein again.
Step S23: and judging whether the first voltage value is equal to the first preset voltage value or not.
The manner of determining whether the first voltage value is equal to the first predetermined voltage value is as described above, and is not repeated herein. If yes, go to step S25, otherwise go to step S24.
Step S24: and exiting the preset mode.
Step S25: and detecting a second voltage value of the preset signal line in a second preset time period after the memory enters the preset mode.
The manner of detecting the second voltage value of the predetermined signal line is as described above, and is not described herein again.
Step S26: and judging whether the second voltage value is equal to the second preset voltage value or not.
The manner of determining whether the second voltage value is equal to the second preset voltage value is as described above, and is not repeated here. If yes, go to step S27, otherwise go to step S24.
Step S27: the preset mode is maintained.
In the preset mode, the step of initializing the memory may be performed, where the manner of initializing the memory is as described above, and is not described herein again.
According to the scheme, under the condition that the memory enters the preset mode, the voltage condition of the preset signal line is detected, whether the voltage value meets the preset voltage condition or not is judged, and if the voltage value does not meet the preset voltage condition, the preset mode exits, so that the condition that the memory fails to initialize due to the fact that the memory enters the preset mode through error touch can be reduced.
The execution main body of the mode adjustment method of the memory may be the memory, and may also be executed by a terminal device or a server or other processing device, where the terminal device may be a User Equipment (UE), a mobile device, a User terminal, a cellular phone, a cordless phone, a Personal Digital Assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, or the like. In some possible implementations, the mode adjustment method of the memory may be implemented by the processor calling computer readable instructions stored in the memory.
The present application further provides a memory, referring to fig. 4 specifically, fig. 4 is a schematic structural diagram of an embodiment of the memory of the present application. The memory 40 stores program instructions 41, and when executed by the memory, the program instructions 41 implement the steps in any of the above embodiments of the mode adjustment method of the memory 40.
The memory 40 includes a voltage monitoring circuit (not shown). The voltage monitoring circuit is used for detecting the voltage condition of the preset signal line when the memory 40 is determined to be in the preset mode.
Optionally, the preset signal line is a signal line between a memory and a device terminal, and the memory is connected to the device terminal. Further, the voltage of the preset signal line is controlled by the device terminal.
According to the scheme, under the condition that the memory 40 enters the preset mode, the voltage value of the preset signal line is detected, then whether the voltage value meets the preset voltage condition or not is judged, and if the voltage value does not meet the preset voltage condition, the preset mode exits, so that the condition that the disc loading of the memory 40 fails due to the fact that the memory 40 enters the preset mode through mistaken touch can be reduced.
The present application further provides an electronic device, please refer to fig. 5 specifically, and fig. 5 is a schematic structural diagram of an embodiment of the electronic device provided in the present application. As shown in fig. 5, the electronic device 50 includes any of the memories provided in the memory embodiments. The memory stores program instructions, and when the program instructions are executed by the memory, the program instructions implement any one of the steps provided in the embodiment of the method for adjusting the mode of the memory. In one particular implementation scenario, electronic device 50 may include, but is not limited to: a microcomputer, a server, and the electronic device 50 may also include a mobile device such as a notebook computer, a tablet computer, and the like, which is not limited herein.
According to the scheme, under the condition that the memory enters the preset mode, the voltage condition of the preset signal line is detected, whether the voltage value meets the preset voltage condition or not is judged, and if the voltage value does not meet the preset voltage condition, the preset mode exits, so that the condition that the memory fails to initialize due to the fact that the memory enters the preset mode through error touch can be reduced.
The foregoing description of the various embodiments is intended to highlight various differences between the embodiments, and the same or similar parts may be referred to each other, and for brevity, will not be described again herein.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely one type of logical division, and an actual implementation may have another division, for example, a unit or a component may be combined or integrated with another system, or some features may be omitted, or not implemented. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some interfaces, indirect coupling or communication connection between devices or units, and may be in an electrical, mechanical or other form.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Claims (10)
1. A method for adjusting a mode of a memory, the method comprising:
triggering the memory to enter a preset mode;
detecting the voltage condition of a preset signal line;
judging whether the voltage condition meets a preset voltage condition or not;
and if not, exiting the preset mode.
2. The method of claim 1, wherein the detecting the voltage condition of the predetermined signal line comprises:
detecting a first voltage value of the preset signal line in a first preset time period after the memory enters a preset mode;
the judging whether the voltage condition meets the preset voltage condition includes:
judging whether the first voltage value is equal to a first preset voltage value or not, wherein the first preset voltage value represents a voltage value within a first preset time period after an equipment end connected with the memory enters a preset mode;
and if not, determining that the voltage condition does not meet the preset voltage condition.
3. The method of claim 2, wherein said determining whether said voltage condition satisfies a predetermined voltage condition further comprises:
if the first voltage value is equal to the first preset voltage value, detecting a second voltage value of the preset signal line in a second preset time period after the memory enters a preset mode;
judging whether the second voltage value is equal to a second preset voltage value, wherein the second preset voltage value represents a voltage value in a second preset time period after the equipment end enters a preset mode, the first preset time period is different from the second preset time period, and the first preset voltage value is different from the second preset voltage value;
and if the second voltage value is not equal to the second preset voltage value, determining that the voltage condition does not satisfy the preset voltage condition.
4. The method of claim 1, wherein the predetermined signal line comprises one or more of a command line, at least one data line controlled by a device side, wherein the device side is connected to the memory;
and/or the voltage condition of the preset signal line is detected by a voltage monitoring circuit of the memory.
5. The method of claim 1, wherein after said exiting said preset mode, said method further comprises:
switching the mode of the memory to an SD mode, wherein the working voltage of the SD mode is higher than that of the preset mode;
initializing the memory in the SD mode.
6. The method of claim 1, wherein triggering the memory into a default mode comprises:
after the memory is powered on, judging whether the voltage of a clock signal line is pulled high or not;
entering a preset mode in response to the voltage of the clock signal line being pulled high.
7. The method of claim 1, wherein the preset mode is a low voltage mode.
8. A memory having stored thereon program instructions which, when executed by the memory, implement the method of any of claims 1 to 7.
9. The memory of claim 8, comprising a voltage monitoring circuit configured to detect a voltage condition of the predetermined signal line when the memory is in the predetermined mode.
10. An electronic device, characterized in that it comprises a memory according to claim 8 or 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111026836.5A CN115757001A (en) | 2021-09-02 | 2021-09-02 | Mode adjusting method of memory, memory and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111026836.5A CN115757001A (en) | 2021-09-02 | 2021-09-02 | Mode adjusting method of memory, memory and electronic equipment |
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| Publication Number | Publication Date |
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| CN115757001A true CN115757001A (en) | 2023-03-07 |
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| CN202111026836.5A Pending CN115757001A (en) | 2021-09-02 | 2021-09-02 | Mode adjusting method of memory, memory and electronic equipment |
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