CN115756982A - Method and device for testing system management interrupt response duration - Google Patents
Method and device for testing system management interrupt response duration Download PDFInfo
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Abstract
The invention provides a method and a device for testing interrupt response duration in system management, wherein the method comprises the following steps: under the condition that the BIOS is in a target environment and the BMC does not trigger system management interruption, controlling the BIOS to send error information corresponding to the test to the BMC through the IPMI interface, and recording the moment when the BIOS sends the error information corresponding to the test to the BMC as a first moment corresponding to the test; acquiring a second moment corresponding to the test by using the BIOS, wherein the second moment is a moment when the BMC triggers system management interruption in response to error information corresponding to the test; and acquiring the system management interrupt response time corresponding to the test based on the first time and the second time corresponding to the test. The method and the device for testing the system management interrupt response time can accurately and efficiently test the SMI response time, and can provide more objective data support for the parameter optimization of the CPU.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a method and a device for testing interrupt response duration in system management.
Background
The System Management Mode (SMM) is an execution Mode of a Central Processing Unit (CPU). System Management Interrupt (SMI) is a form of Interrupt provided by the CPU.
In general, each time the SMI triggers the CPU, the CPU enters SMM, then performs error handling and reporting, and exits SMM after the handling is completed. The delay that may be incurred by the CPU each time it enters or exits SMM may be referred to as the SMI response duration.
The SMI response time is an important factor of the interrupt processing speed and the CPU performance, and the improvement of the SMI response time has important significance for improving the interrupt processing speed and the CPU performance. Therefore, how to test the response time of the SMI is an urgent technical problem to be solved in the field.
Disclosure of Invention
The invention provides a method and a device for testing interrupt response time length in system management, which are used for testing SMI response time length.
The invention provides a method for testing interrupt response duration in system management, which comprises the following steps:
under the condition that a basic input/output system (BIOS) is in a target environment and a Baseboard Management Controller (BMC) does not trigger system management interruption, controlling the BIOS to send error information corresponding to the test to the BMC through an intelligent platform management interface, and recording the moment when the BIOS sends the error information corresponding to the test to the BMC as a first moment corresponding to the test;
acquiring a second moment corresponding to the test by using the BIOS, wherein the second moment is a moment when the BMC triggers system management interruption in response to error information corresponding to the test;
acquiring system management interrupt response time corresponding to the test based on a first moment and a second moment corresponding to the test;
the BIOS can perform troubleshooting debugging under a target environment.
According to the method for testing the interrupt response duration in the system management provided by the invention, after determining the interrupt response duration of the system management corresponding to the test based on the first time and the second time corresponding to the test, the method further comprises the following steps:
under the condition that the test is the Kth test in the target time period, acquiring an evaluation result of the system management interruption response time length based on the system management interruption response time length corresponding to each test in the target time period;
wherein K is a preset value; the target time period is determined based on the time when the system management interruption response duration corresponding to the first test is obtained.
According to the method for testing the interrupt response duration in the system management provided by the invention, the evaluation result of the interrupt response duration in the system management is obtained based on the interrupt response duration in the system management corresponding to each test in the target time period, and the method comprises the following steps:
based on the system management interruption response time length corresponding to each test in the target time period, acquiring the average value of the system management interruption response time lengths corresponding to each test in the target time period and the maximum value of the system management interruption response time lengths corresponding to each test;
obtaining the evaluation result based on the average value and the maximum value.
According to the method for testing the interrupt response duration in the system management provided by the invention, the obtaining of the evaluation result based on the average value and the maximum value comprises the following steps:
and determining that the system management interrupt response time length is not abnormal as the evaluation result under the condition that the average value is smaller than a first preset value and the maximum value does not exceed a second preset value.
According to the method for testing the interrupt response duration in the system management, provided by the invention, under the condition that the evaluation result includes that the system management interrupt response duration is abnormal, the method comprises the following steps:
and optimizing parameters of the BMC and/or the BIOS.
According to the method for testing the interrupt response time length in the system management, provided by the invention, the value range of the first preset value is between 40ms and 60ms; the value range of the second preset value is 140ms to 160ms.
The invention also provides a device for testing the interrupt response time length in system management, which comprises:
the interrupt triggering module is used for controlling the BIOS to send error information corresponding to the test to the BMC through an intelligent platform management interface under the condition that the BIOS is in a target environment and the BMC does not trigger system management interrupt, and recording the moment when the BIOS sends the error information corresponding to the test to the BMC as a first moment corresponding to the test;
the data acquisition module is used for acquiring a second moment corresponding to the test by using the BIOS, wherein the second moment is a moment when the BMC triggers system management interruption in response to the error information corresponding to the test;
the time length determining module is used for acquiring the system management interrupt response time length corresponding to the test based on the first time and the second time corresponding to the test;
the BIOS can perform troubleshooting debugging under a target environment.
The invention also provides an electronic device, which comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, wherein when the processor executes the program, the method for testing the system management interrupt response time length is realized.
The present invention also provides a non-transitory computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the method for testing system management interrupt response duration as described in any of the above.
The present invention also provides a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the method for testing the duration of the system management interrupt response.
The invention provides a method and a device for testing system management interruption response duration, which are characterized in that under the condition that a BIOS is in a target environment and a BMC does not trigger system management interruption, the BIOS is controlled to send error information corresponding to the current test to the BMC through an IPMI interface, the time when the BIOS sends the error information corresponding to the current test to the BMC is recorded as a first time corresponding to the current test, the BIOS is used for obtaining the time when the BMC triggers SMI interruption in response to the error information corresponding to the current test and taking the time as a second time corresponding to the current test, and the SMI response duration corresponding to the current test is obtained based on the first time and the second time corresponding to the current test.
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In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for testing system management interrupt response duration according to the present invention;
FIG. 2 is a second flowchart illustrating a method for testing system management interrupt response duration according to the present invention;
FIG. 3 is a schematic structural diagram of a testing apparatus for managing interrupt response duration in a system according to the present invention;
fig. 4 is a schematic structural diagram of an electronic device provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
It should be noted that the SMI is an interrupt form provided by the CPU, and is a productive interrupt, so that the processor can process the server management event. Typically, an SMI is a memory error, a PCI (Peripheral Component Interconnect) error, or other form of critical interrupt.
When SMI triggers, the CPU enters SMM. Before entering SMM, the CPU stores the value of the register in a System Management Random Access Memory (SMRAM), and jumps the program to an SIM Entry function (SMI Entry Point) to trigger SMI. After the processing is finished, the RSM instruction can be used for enabling the CPU to exit the system management mode, and meanwhile, the value of the CPU register is restored.
SMIs are divided into software interrupts, which refer to interrupts generated by program settings, and hardware interrupts, which refer to interrupts generated by external hardware, such as interrupts generated by a power key press. When SMI is triggered to the CPU each time, the CPU enters the SMM, then carries out error processing and reporting, and exits the SMM after the processing is finished. The delay is incurred each time the CPU enters or exits SMM, and the delay period during which the CPU enters or exits SMM may be referred to as the SMI response period.
The SMI response time length can influence the interrupt processing speed, further influence the performance of the CPU, and the improvement of the SMI response time length has important significance for improving the interrupt processing speed and the performance of the CPU.
In general, a technician can evaluate the performance of the CPU by looking up a fault log, and then perform parameter optimization on the CPU based on the evaluation result, but does not consider the influence of the SMI response duration on the interrupt processing speed and the performance of the CPU, so that the technical scheme of measuring the SMI response duration and performing parameter optimization on the CPU based on the SMI response duration does not exist in the conventional technology.
In view of the above, the present invention provides a method for testing interrupt response duration in system management. The method for testing the system management interrupt response time can accurately and efficiently test the SMI response time, further provide objective data support for the parameter optimization of the CPU and better meet the user requirements.
Fig. 1 is a schematic flow chart of a method for testing a system management interrupt response duration according to the present invention. The method for testing the duration of the system management interrupt response of the present invention is described below with reference to fig. 1. As shown in fig. 1, the method includes: step 101, under the condition that the basic input/output system BIOS is in a target environment and the BMC of the baseboard management controller does not trigger system management interruption, controlling the BIOS to send error information corresponding to the current test to the BMC through the intelligent platform management interface, and recording a time when the BIOS sends the error information corresponding to the current test to the BMC as a first time corresponding to the current test.
The BIOS can perform troubleshooting debugging under a target environment.
It should be noted that the execution subject in the embodiment of the present invention is a test apparatus for managing interrupt response time duration in a system.
The Basic Input Output System (BIOS) is a set of programs that is fixed on a ROM chip on a main board of a computer, and stores the most important Basic Input and Output programs of the computer, a self-test program after power-on, and a System self-boot program. The primary function of the BIOS is to provide the lowest level, most direct hardware setup and control for the computer.
The target environment can be debug environment, and the BIOS can carry out troubleshooting debugging under the target environment.
A Baseboard Management Controller (BMC) is a core component in a server Management system defined by an Intelligent Platform Management Interface (IPMI) protocol, and can manage an Interface between system Management software and Platform hardware.
IPMI is a set of computer interface specifications defined for the autonomous computer subsystem, which is used to provide software and hardware management and monitoring functions independent of the CPU, firmware (BIOS or UEFI), and operating system of the host system. IPMI defines a set of system administrator interfaces for out-of-band management and administrator operational monitoring of computer systems.
Under the condition that the BIOS is in the target environment and the BMC does not trigger SMI, the BIOS can be controlled to send the error information corresponding to the test to the BMC through the IPMI through the control instruction, and the time when the BIOS sends the error information corresponding to the test to the BMC can be recorded as the first time corresponding to the test.
Specifically, the BMC may trigger the SMI interrupt in response to the error information corresponding to the current test sent by the BIOS when receiving the error information corresponding to the current test.
In the embodiment of the invention, the BIOS can be used for acquiring the moment when the BMC triggers the SMI interruption in response to the error information corresponding to the test, and the moment can be used as the second moment corresponding to the test.
And 103, acquiring a system management interrupt response time corresponding to the test based on the first time and the second time corresponding to the test.
Specifically, after the first time and the second time corresponding to the test are obtained, an interval duration between the second time corresponding to the test and the first time corresponding to the test may be obtained, and the interval duration may be obtained. And determining the response time length of the SMI corresponding to the test.
It should be noted that, by repeating the above steps 101 to 103, multiple tests on the SMI response time duration can be implemented.
According to the embodiment of the invention, under the condition that the BIOS is in a target environment and the BMC does not trigger system management interruption, the BIOS is controlled to send the error information corresponding to the test to the BMC through the IPMI interface, the time when the BIOS sends the error information corresponding to the test to the BMC is recorded as the first time corresponding to the test, the BIOS is used for obtaining the time when the BMC responds to the error information corresponding to the test to trigger SMI interruption and taking the time as the second time corresponding to the test, and the SMI response duration corresponding to the test is obtained based on the first time and the second time corresponding to the test, so that the SMI response duration can be accurately and efficiently tested, more objective data support can be provided for parameter optimization of the CPU, and user requirements can be better met.
Based on the content of each embodiment, after determining the system management interrupt response duration corresponding to the current test based on the first time and the second time corresponding to the current test, the method further includes: under the condition that the test is the Kth test in the target time period, acquiring an evaluation result of the system management interruption response time length based on the system management interruption response time length corresponding to each test in the target time period;
wherein K is a preset value; the target time period is determined based on the time when the system management interrupt response duration corresponding to the first test is obtained.
Specifically, for the first test, the SMI response time duration corresponding to the first test may be obtained by executing the above steps 101 to 103, and further, the time for obtaining the SMI response time duration corresponding to the first test may be recorded.
And the evaluation accuracy of the SMI response time length is prevented from being reduced because the time length of the interval between the test and the first test is too long. In the embodiment of the invention, the target time interval can be determined based on the moment of acquiring the SMI response time corresponding to the first test.
Optionally, in this embodiment of the present invention, the start time of the target time period may be determined as a time when the SMI response time period corresponding to the first test is obtained, and the time when the SMI response time period corresponding to the first test is obtained is delayed by a preset time period and determined as a termination time of the target time period. The preset duration may be determined according to an actual situation and/or a priori knowledge, for example: the preset time period may be 10 minutes. The preset time period is not particularly limited in the embodiment of the present invention.
After the SMI response duration corresponding to the test is obtained, whether the test is the Kth test in the target time interval or not can be judged. And K is a preset value determined according to the actual situation and/or the prior knowledge. The specific value of K in the embodiment of the present invention is not limited.
Alternatively, K may range between 30 and 70. For example, K can take on a value of 30, 50, or 70.
If the test is determined to be the Kth test in the target time period, the evaluation result of the SMI response duration can be obtained through numerical calculation, mathematical statistics, deep learning or other modes based on the SMI response duration corresponding to each test in the target time period.
It should be noted that, for the ith test in the target time period, the obtaining of the SMI response time length corresponding to the ith test by executing the above steps 101 to 103 specifically includes: under the condition that the BIOS is in the target environment and the BMC does not trigger SMI, the BIOS can be controlled to send error information corresponding to the ith test to the BMC through the IPMI interface through the control instruction, and the time when the BIOS sends the error information corresponding to the ith test to the BMC can be recorded as the first time corresponding to the ith test. The BMC can respond to the error information corresponding to the ith test and trigger SMI interruption under the condition of receiving the error information corresponding to the ith test sent by the BIOS. The BIOS can be used for acquiring the moment when the BMC triggers SMI interruption in response to the error information corresponding to the ith test, and the moment can be used as a second moment corresponding to the ith test. After the first time and the second time corresponding to the ith test are obtained, the interval duration between the second time corresponding to the ith test and the first time corresponding to the ith test can be determined as the SMI response duration corresponding to the ith test.
According to the embodiment of the invention, under the condition that the current test is the Kth test in the target time interval, the evaluation result of the SMI response duration is obtained based on the SMI response duration corresponding to each test in the target time interval, the SMI response duration can be evaluated through the SMI response durations obtained through multiple tests, the interrupt processing capability of the CPU can be further evaluated based on the evaluation result of the SMI response duration, and more objective data support can be provided for parameter optimization of the CPU.
Based on the content of the foregoing embodiments, obtaining an evaluation result of the system management interrupt response duration based on the system management interrupt response duration corresponding to each test in the target time period includes: based on the system management interrupt response time length corresponding to each test in the target time period, the average value of the system management interrupt response time length corresponding to each test in the target time period and the maximum value of the system management interrupt response time length corresponding to each test are obtained.
Specifically, based on the response time length of the SMI corresponding to each test in the target time period, the average value of the response time lengths of the SMIs corresponding to each test in the target time period can be calculated in a numerical calculation manner.
Based on the SMI response time length corresponding to each test in the target time period, the maximum value of the SMI response time lengths corresponding to each test in the target time period can be determined in a mathematical statistics mode.
Based on the average value and the maximum value, an evaluation result is obtained.
Specifically, after obtaining the average value of the SMI response durations corresponding to each test and the maximum value of the SMI response durations corresponding to each test in the target time period, condition judgment may be performed based on the average value and the maximum value, and an evaluation result of the SMI response duration may be determined based on a result of the condition judgment.
It should be noted that the specific content of the above condition judgment can be determined based on a priori knowledge and/or actual conditions. The specific content of the above condition judgment is not limited in the embodiment of the present invention.
According to the embodiment of the invention, after the average value of the SMI response time length corresponding to each test in the target time interval and the maximum value of the SMI response time length corresponding to each test are obtained based on the SMI response time length corresponding to each test in the target time interval, the evaluation result of the SMI response time length can be more accurately and more efficiently obtained based on the average value and the maximum value.
Based on the content of the above embodiments, the evaluation result is obtained based on the average value and the maximum value, and includes: and determining that the system management interrupt response time length is not abnormal as an evaluation result when the average value is smaller than the first preset value and the maximum value is not larger than the second preset value.
Specifically, after obtaining an average value of SMI response durations corresponding to each test and a maximum value of the SMI response durations corresponding to each test within the target time period, it may be determined whether the average value is smaller than a first preset value, and whether the maximum value is not larger than a second preset value.
When the average value is smaller than a first preset value and the maximum value is not larger than a second preset value, determining that the SMI response time length is not abnormal as an evaluation result of the SMI response time length;
when the average value is not less than the first preset value and/or the maximum value is greater than the second preset value, it may be determined that the SMI response time length is abnormal as the evaluation result of the SMI response time length.
It should be noted that the first preset value and the second preset value in the embodiment of the present invention may be determined based on a priori knowledge and/or actual conditions. The specific values of the first preset value and the second preset value are not limited in the embodiment of the invention.
As an optional embodiment, the value range of the first preset value is between 40ms and 60ms; the value range of the second preset value is 140ms to 160ms.
Specifically, the value range of the first preset value may be between 40ms and 60ms, for example: the value of the first preset value can be 40ms, 50ms or 60ms; the value range of the second preset value may be 140ms to 160ms, for example: the second preset value may take on a value of 140ms, 150ms, or 160ms.
Preferably, the value of the first preset value may be 50ms; the value of the second preset value may be 150ms.
Optionally, the evaluation result of the SMI response time duration in the embodiment of the present invention may further include the average value and the maximum value.
In the embodiment of the invention, under the condition that the average value of the SMI response time lengths corresponding to each test in the target time interval is less than the first preset value and the maximum value of the SMI response time lengths corresponding to each test in the target time interval is not more than the second preset value, the SMI response time length is determined to be the evaluation result of the SMI response time length without exception, so that the evaluation result of the SMI response time length can be more accurately and efficiently obtained.
Based on the content of the foregoing embodiments, in a case where it is determined that the evaluation result includes that there is an abnormality in the system management interrupt response time length, the method includes: and optimizing parameters of the BMC and/or the BIOS.
It should be noted that the response time of the SMI may be affected by the number of tasks processed by the BIOS KCS delay and BMC, the speed of writing error information into the Flash generation log, and the like.
Therefore, in the embodiment of the present invention, when it is determined that the evaluation result of the SMI response time includes that the SMI response time is abnormal, the parameter optimization may be performed on the BMC, or the parameter optimization may also be performed on the BIOS KCS delay, or the parameter optimization may also be performed on the BMC and the BIOS KCS delay at the same time, and further, the SMI response time may be controlled by optimizing the parameters of the BMC and/or the BIOS KCS delay.
According to the embodiment of the invention, the parameter optimization is carried out on the BMC and/or the BIOS under the condition that the evaluation result of the SMI response time length includes that the SMI response time length is abnormal, so that the SMI response time length can be regulated and controlled, and the user requirements can be better met.
In order to facilitate understanding of the system management interrupt response time duration test method provided by the invention. The following describes the method for testing the response duration of the system management interrupt provided by the present invention by using an example.
FIG. 2 is a second flowchart illustrating a method for testing the SMI response time according to the present invention. As shown in fig. 2, in this example, the specific steps of testing the response duration of the SMI include: step 201, under the condition that the BIOS is in the target environment and the BMC does not trigger the SMI, controlling the BIOS to send the error information corresponding to the ith test to the BMC through the IPMI interface by the control instruction, and recording a time when the BIOS sends the error information corresponding to the ith test to the BMC as a first time corresponding to the ith test.
Wherein, i is 1,2,3, \ 8230;, in sequence.
And step 204, judging whether the ith test is the Kth measurement in the target time interval.
Under the condition that the ith test is not the Kth measurement in the target time period, increasing i by 1, and returning to execute the steps 201 to 204 until the ith test is the Kth measurement in the target time period;
in case the ith test is the kth measurement within the target period, step 205 is executed;
wherein the value of K is 50. The target time period starts from the moment of obtaining the SMI response time length corresponding to the first test and ends 10 minutes after the moment of obtaining the SMI response time length corresponding to the first test.
if the average value is smaller than the first preset value and the maximum value is not greater than the second preset value, go to step 207;
if the average value is not less than the first preset value and/or the maximum value is greater than the second preset value, go to step 208;
wherein the value of the first preset value is 50ms; the value of the second preset value is 150ms.
And step 207, determining that the SMI response time length is not abnormal as the evaluation result of the SMI response time length.
FIG. 3 is a schematic structural diagram of a testing apparatus for managing interrupt response duration in a system according to the present invention. The following describes the testing apparatus for system management interrupt response duration provided by the present invention with reference to fig. 3, and the testing apparatus for system management interrupt response duration described below and the testing method for system management interrupt response duration provided by the present invention described above may be referred to correspondingly. As shown in fig. 3, the apparatus includes: an interrupt triggering module 301, a data acquisition module 302 and a duration determination module 303.
The interrupt triggering module 301 is configured to, when the BIOS is in a target environment and the BMC of the BMC does not trigger system management interrupt, control the BIOS to send error information corresponding to the current test to the BMC through the intelligent platform management interface, and record a time when the BIOS sends the error information corresponding to the current test to the BMC as a first time corresponding to the current test;
a data acquisition module 302, configured to acquire a second time corresponding to the current test by using the BIOS, where the second time is a time when the BMC triggers system management interruption in response to error information corresponding to the current test;
a duration determining module 303, configured to obtain a system management interrupt response duration corresponding to the test based on a first time and a second time corresponding to the test;
the BIOS can perform troubleshooting debugging under a target environment.
Specifically, the interrupt triggering module 301, the data acquisition module 302 and the duration determination module 303 are electrically connected.
The interrupt triggering module 301 may be configured to, when the BIOS is in the target environment and the BMC does not trigger the SMI, control the BIOS to send the error information corresponding to the current test to the BMC through the IPMI interface through the control instruction, and record a time when the BIOS sends the error information corresponding to the current test to the BMC as a first time corresponding to the current test.
The data acquisition module 302 may be configured to acquire, by using the BIOS, a time at which the BMC triggers an SMI interrupt in response to the error information corresponding to the test, and may use the time as a second time corresponding to the test.
The duration determining module 303 may be configured to obtain an interval duration between the second time corresponding to the current test and the first time corresponding to the current test, and apply the interval duration. And determining the response time length of the SMI corresponding to the test.
Optionally, the test apparatus for managing interrupt response time length by the system may further include a time length evaluation module.
The time length evaluation module can be used for acquiring an evaluation result of the system management interruption response time length based on the system management interruption response time length corresponding to each test in the target time period under the condition that the test is the Kth test in the target time period;
wherein K is a preset value; the target time period is determined based on the time when the system management interrupt response duration corresponding to the first test is obtained.
It should be noted that, in order to avoid that the time length of the interval between the current test and the first test is too long, the accuracy of the evaluation of the SMI response time length is reduced. In the embodiment of the invention, the target time interval can be determined based on the moment of acquiring the SMI response time length corresponding to the first test.
Optionally, in this embodiment of the present invention, the starting time of the target time interval may be determined as a time of acquiring the SMI response time corresponding to the first test, and the time of delaying the time of acquiring the SMI response time corresponding to the first test by a preset time interval is determined as a time of terminating the target time interval. The preset duration may be determined according to an actual situation and/or a priori knowledge, for example: the preset time period may be 10 minutes. The preset time period is not particularly limited in the embodiment of the present invention.
It should be noted that K is a preset value determined according to actual conditions and/or a priori knowledge. The specific value of K is not limited in the embodiments of the present invention.
Alternatively, K may range from 30 to 70. For example, K can take on a value of 30, 50, or 70.
Optionally, the duration evaluation module may include a calculation unit and an evaluation unit.
The calculating unit may be configured to obtain an average value of system management interrupt response durations corresponding to each test in the target period and a maximum value of the system management interrupt response durations corresponding to each test based on the system management interrupt response duration corresponding to each test in the target period.
The above-described evaluation unit may be configured to obtain an evaluation result based on the average value and the maximum value.
Specifically, the calculating unit may be configured to calculate, in a numerical calculation manner, an average value of the SMI response durations corresponding to each test in the target time period based on the SMI response duration corresponding to each test in the target time period.
The calculating unit may be further configured to determine, in a mathematical statistics manner, a maximum value of the SMI response durations corresponding to the tests in each time within the target time period based on the SMI response durations corresponding to the tests in each time within the target time period.
The evaluation unit may be configured to perform condition judgment based on the average value and the maximum value, and may determine an evaluation result of the SMI response time period based on a result of the condition judgment.
Optionally, the evaluation unit may be specifically configured to determine that there is no abnormality in the system management interrupt response duration as the evaluation result when the average value is smaller than the first preset value and the maximum value does not exceed the second preset value.
Specifically, the evaluation unit may be specifically configured to determine whether the average value is smaller than a first preset value, and determine whether the maximum value is not larger than a second preset value.
When the average value is smaller than a first preset value and the maximum value is not greater than a second preset value, determining that there is no abnormality in the SMI response time as an evaluation result of the SMI response time; when the average value is not less than the first preset value and/or the maximum value is greater than the second preset value, it may be determined that the SMI response time length is abnormal as the evaluation result of the SMI response time length.
As an optional embodiment, the value range of the first preset value is between 40ms and 60ms; the value range of the second preset value is 140ms to 160ms.
Preferably, the value of the first preset value may be 50ms; the value of the second preset value may be 150ms.
Optionally, the testing apparatus for managing the interrupt response time of the system may further include a parameter optimization module.
The parameter optimization module may be configured to perform parameter optimization on the BMC and/or the BIOS when it is determined that the evaluation result includes that the system management interrupt response duration is abnormal.
Specifically, the parameter optimization module may be configured to perform parameter optimization on the BMC, or perform parameter optimization on the BIOS KCS delay, or perform parameter optimization on the BMC and the BIOS KCS delay simultaneously when it is determined that the evaluation result of the SMI response time includes that the SMI response time is abnormal, and further may adjust and control the SMI response time by performing parameter optimization on the BMC and/or the BIOS KCS delay.
According to the testing device for the response duration of the system management interrupt in the embodiment of the invention, under the condition that the BIOS is in a target environment and the BMC does not trigger the system management interrupt, the BIOS is controlled to send the error information corresponding to the test to the BMC through the IPMI interface, the moment when the BIOS sends the error information corresponding to the test to the BMC is recorded as the first moment corresponding to the test, the BIOS is used for obtaining the moment when the BMC triggers the SMI interrupt in response to the error information corresponding to the test as the second moment corresponding to the test, and the SMI response duration corresponding to the test is obtained based on the first moment and the second moment corresponding to the test.
Fig. 4 illustrates a physical structure diagram of an electronic device, which may include, as shown in fig. 4: a processor (processor) 410, a communication Interface 420, a memory (memory) 430 and a communication bus 440, wherein the processor 410, the communication Interface 420 and the memory 430 are communicated with each other via the communication bus 440. The processor 410 may call logic instructions in the memory 430 to perform a method of testing system management interrupt response durations, the method comprising: under the condition that the basic input/output system BIOS is in a target environment and the baseboard management controller BMC does not trigger system management interruption, controlling the BIOS to send error information corresponding to the test to the BMC through an intelligent platform management interface, and recording the time when the BIOS sends the error information corresponding to the test to the BMC as a first time corresponding to the test; acquiring a second moment corresponding to the test by using the BIOS, wherein the second moment is a moment when the BMC triggers system management interruption in response to error information corresponding to the test; acquiring system management interrupt response time corresponding to the test based on a first moment and a second moment corresponding to the test; the BIOS can perform troubleshooting debugging under a target environment.
In addition, the logic instructions in the memory 430 may be implemented in the form of software functional units and stored in a computer readable storage medium when the software functional units are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, the present invention further provides a computer program product, the computer program product including a computer program, the computer program being stored on a non-transitory computer-readable storage medium, wherein when the computer program is executed by a processor, the computer is capable of executing the method for testing duration of system management interrupt response provided by the above methods, the method comprising: under the condition that the basic input/output system BIOS is in a target environment and the baseboard management controller BMC does not trigger system management interruption, controlling the BIOS to send error information corresponding to the test to the BMC through an intelligent platform management interface, and recording the moment when the BIOS sends the error information corresponding to the test to the BMC as a first moment corresponding to the test; acquiring a second moment corresponding to the test by using the BIOS, wherein the second moment is a moment when the BMC responds to error information corresponding to the test and triggers system management interruption; acquiring system management interrupt response time corresponding to the test based on a first moment and a second moment corresponding to the test; the BIOS can perform troubleshooting debugging under a target environment.
In another aspect, the present invention also provides a non-transitory computer readable storage medium, on which a computer program is stored, where the computer program is implemented to implement a method for testing duration of system management interrupt response provided by the above methods when executed by a processor, and the method includes: under the condition that the basic input/output system BIOS is in a target environment and the baseboard management controller BMC does not trigger system management interruption, controlling the BIOS to send error information corresponding to the test to the BMC through an intelligent platform management interface, and recording the time when the BIOS sends the error information corresponding to the test to the BMC as a first time corresponding to the test; acquiring a second moment corresponding to the test by using the BIOS, wherein the second moment is a moment when the BMC responds to error information corresponding to the test and triggers system management interruption; acquiring system management interrupt response time corresponding to the test based on a first moment and a second moment corresponding to the test; the BIOS can perform troubleshooting debugging under a target environment.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for testing interrupt response duration in system management is characterized by comprising the following steps:
under the condition that a basic input/output system (BIOS) is in a target environment and a Baseboard Management Controller (BMC) does not trigger system management interruption, controlling the BIOS to send error information corresponding to the test to the BMC through an intelligent platform management interface, and recording the moment when the BIOS sends the error information corresponding to the test to the BMC as a first moment corresponding to the test;
acquiring a second moment corresponding to the test by using the BIOS, wherein the second moment is a moment when the BMC triggers system management interruption in response to error information corresponding to the test;
acquiring system management interrupt response time corresponding to the test based on a first moment and a second moment corresponding to the test;
the BIOS can perform troubleshooting debugging under a target environment.
2. The method for testing system management interrupt response duration according to claim 1, wherein after determining the system management interrupt response duration corresponding to the current test based on the first time and the second time corresponding to the current test, the method further comprises:
under the condition that the test is the Kth test in the target time period, acquiring an evaluation result of the system management interruption response time length based on the system management interruption response time length corresponding to each test in the target time period;
wherein K is a preset value; the target time period is determined based on the time when the system management interruption response duration corresponding to the first test is obtained.
3. The method according to claim 2, wherein the obtaining an evaluation result of the duration of the system management interrupt response based on the duration of the system management interrupt response corresponding to each test in the target period comprises:
based on the system management interruption response time corresponding to each test in the target time period, acquiring the average value of the system management interruption response time corresponding to each test in the target time period and the maximum value of the system management interruption response time corresponding to each test;
obtaining the evaluation result based on the average value and the maximum value.
4. The method for testing duration of interrupt response of system management according to claim 3, wherein said obtaining the evaluation result based on the average value and the maximum value comprises:
and determining that the system management interrupt response time length is not abnormal as the evaluation result under the condition that the average value is smaller than a first preset value and the maximum value does not exceed a second preset value.
5. The method for testing system management interrupt response time according to claim 4, wherein in case that it is determined that the evaluation result includes that there is an abnormality in system management interrupt response time, the method further comprises:
and optimizing parameters of the BMC and/or the BIOS.
6. The method for testing system management interrupt response time according to claim 4, wherein the first preset value ranges from 40ms to 60ms; the value range of the second preset value is 140ms to 160ms.
7. A test apparatus for managing interrupt response time duration in a system, comprising:
the interrupt triggering module is used for controlling the BIOS to send the error information corresponding to the test to the BMC through an intelligent platform management interface under the condition that the BIOS is in a target environment and the BMC does not trigger system management interrupt, and recording the time when the BIOS sends the error information corresponding to the test to the BMC as the first time corresponding to the test;
the data acquisition module is used for acquiring a second moment corresponding to the test by using the BIOS, wherein the second moment is a moment when the BMC responds to error information corresponding to the test and triggers system management interruption;
the time length determining module is used for acquiring the system management interrupt response time length corresponding to the test based on the first time and the second time corresponding to the test;
the BIOS can perform troubleshooting debugging under a target environment.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement a method of testing system management interrupt response durations as claimed in any one of claims 1 to 6.
9. A non-transitory computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements a method for testing system management interrupt response durations as recited in any one of claims 1 to 6.
10. A computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements a method for testing system management interrupt response times according to any one of claims 1 to 6.
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