CN115754946A - Composite echo signal simulator - Google Patents
Composite echo signal simulator Download PDFInfo
- Publication number
- CN115754946A CN115754946A CN202211473944.1A CN202211473944A CN115754946A CN 115754946 A CN115754946 A CN 115754946A CN 202211473944 A CN202211473944 A CN 202211473944A CN 115754946 A CN115754946 A CN 115754946A
- Authority
- CN
- China
- Prior art keywords
- modulation
- unit
- signal
- digital
- receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002131 composite material Substances 0.000 title claims abstract description 28
- 238000004364 calculation method Methods 0.000 claims abstract description 43
- 238000012545 processing Methods 0.000 claims abstract description 11
- 238000001514 detection method Methods 0.000 claims description 22
- 238000006243 chemical reaction Methods 0.000 claims description 21
- 238000002592 echocardiography Methods 0.000 claims description 20
- 238000004458 analytical method Methods 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims description 12
- 238000005259 measurement Methods 0.000 claims description 8
- 230000000903 blocking effect Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 238000004891 communication Methods 0.000 claims description 3
- 238000005070 sampling Methods 0.000 claims description 2
- 238000004088 simulation Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004422 calculation algorithm Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012549 training Methods 0.000 description 1
Images
Landscapes
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention discloses a composite echo signal simulator, which comprises a collection playback unit, a clock unit, a receiving modulation unit, a modulation calculation unit and an interface unit, wherein the clock unit is connected with the collection playback unit; a DRFM2500 board is used as a hardware platform, the device is provided with two paths of high-low gain signal receiving channels and three paths of echo signal generating channels, two kinds of modulation of point target modulation and time domain convolution modulation are adopted for parallel processing, combined output of various echo signal patterns is supported, and a time domain convolution modulation structure adopts a cascading mode to realize echo simulation in a large-distance coverage range.
Description
Technical Field
The invention relates to radar technology, in particular to a composite echo signal simulator.
Background
The rapid development of radar technology makes the modern electromagnetic signal environment become very complex, mainly reflecting the aspects of large signal density, coexistence of various interference signals, variable signal parameters and the like. The development, anti-interference performance evaluation and relevant military electronic countermeasure training of the radar system all put urgent requirements on the simulation of complex electromagnetic environment signals.
Compared with the traditional external field test, the method consumes a large amount of manpower, material resources and financial resources, the echo signal simulator has the characteristics of flexibility, economy, convenience and the like, can simulate target echoes, clutters and various types of interference signals, and provides a complex electromagnetic environment for the fields of radars and electronic countermeasures.
The current echo signal simulator focuses on target echo generation based on different constitution radar signal forms, false target deception jamming generation aiming at large scenes and target echo generation based on a data playback mode.
Due to the fact that modern electromagnetic signals are complex in environment, target echoes, interference signals and environmental clutter coexist, coverage distance of false target interference signals is large for increasing shielding distance, and the existing echo signal simulators cannot simultaneously meet target, interference and clutter composite generation under the condition of far coverage distance.
Therefore, there is a need for a composite echo signal simulator that can output any combination of target echo, clutter, and various types of interference signals, and that has long-range interference coverage capability.
Disclosure of Invention
The invention aims to: the invention aims to solve the defects in the prior art and provides a composite echo signal simulator.
The technical scheme is as follows: the invention relates to a composite echo signal simulator, which comprises a clock unit, an acquisition playback unit, a clock unit, a receiving modulation unit, a modulation calculation unit and an interface unit, wherein the clock unit is used for receiving and modulating an echo signal; the receiving and modulating unit is respectively connected with the acquisition and playback unit, the modulation and calculation unit and the interface unit, and the clock unit is connected with the acquisition and playback unit and sends a clock signal to the acquisition and playback unit; the acquisition playback unit comprises two analog-to-digital conversion modules (ADC) and three digital-to-analog converters (DAC); the two analog-to-digital conversion modules respectively convert the received two paths of analog signals with different gains (a high-gain channel intermediate-frequency analog signal and a low-gain channel intermediate-frequency analog signal) into digital signals in an analog-to-digital manner, and send the converted digital signals to the receiving modulation unit; the three digital-to-analog converters convert the three paths of intermediate frequency digital echo signals (intermediate frequency clutter/interference signals and intermediate frequency target echo signals) received from the receiving and modulating unit into analog signals in a digital-to-analog mode; the receiving modulation unit comprises two FPGAs; the two FPGAs are connected through a high-speed differential interconnection line and respectively receive intermediate-frequency digital signals sent by the corresponding analog-to-digital conversion module, modulation data and instruction return information sent by the modulation calculation unit and control instructions and setting parameters of the interface unit; then, the control instruction and the setting parameter received from the interface unit are sent to a modulation calculation unit, then, the echo signal modulated by the modulation unit is sent to a digital-to-analog conversion module, and the modulation calculation unit sends back information to the interface unit according to the received control instruction and the setting parameter; the modulation calculation unit comprises a digital signal processor, receives the control instruction and the setting parameter transmitted by the receiving modulation unit through the digital signal processor, then calculates the modulation data of the target echo/clutter/interference signal, and transmits the modulation data or instruction return information to the receiving modulation unit; the interface unit receives a control instruction and a setting parameter sent by an external main control computer through a serial port and sends the control instruction and the setting parameter to the receiving modulation unit, or receives return data sent by the receiving modulation unit and sends the return data to the main control computer.
Furthermore, the FPGA comprises a signal receiving detection sub-module, a PDW parameter measurement sub-module, a signal data caching sub-module and a signal modulation sub-module; the signal receiving and detecting submodule carries out digital channel analysis and signal detection on the intermediate-frequency digital signal sent by the analog-to-digital conversion module (201), and a detection result is used for receiving and transmitting wave gate control and is simultaneously transmitted to the PDW parameter measuring submodule and the signal data caching submodule; the digital channelization analysis is to extract the obtained single-channel digital signals into multi-channel signals at equal time intervals according to a clock signal for parallel transmission, and simultaneously, each parallel transmission channel is a channel, and the obtained digital signals are extracted into the multi-channel signals for transmission, so that the advantages of improving the detection signal-to-noise ratio and reducing the information modulation rate can be achieved; the PDW parameter measurement submodule measures pulse width, repetition period, amplitude, starting frequency, arrival time, bandwidth, central frequency, intra-pulse modulation type and intra-pulse modulation parameters of PDW, generates PDW parameters and then sends the PDW parameters to the modulation calculation unit; the signal data cache submodule selects and caches signal data of the detection result of the signal receiving detection submodule; and the signal modulation submodule performs convolution operation on the modulation data received from the modulation calculation unit and the signal data output by the signal data caching submodule, so that modulation of target echoes, clutter and multi-false-target interference signals is realized.
Further, in order to output various types of signals in a combined mode, the signal modulation submodule conducts combined output of various echo signal patterns and various interference types through parallel processing of point target modulation and time domain convolution modulation and cascade of time domain convolution modulation structures.
The signal modulation submodule on the same FPGA realizes the output of the point target type echo signal/clutter/multi-false target interference signal by parallel processing of the point target modulation structure and the time domain convolution modulation structure; the time domain convolution modulation structures on different FPGAs are cascaded, namely the time domain convolution modulation structures on two FPGAs adopt a cascading mode, namely the time domain convolution modulation initial distance delay on the second FPGA is linked with the time domain convolution modulation farthest distance delay on the first FPGA so as to realize clutter or multiple false targets with the distance coverage range of at most 75 kilometers; the point target modulation structure carries out time delay and amplitude phase modulation on input signal data after channel analysis to generate point target type echoes, wherein the point target type echoes comprise target echoes, flight path false target interference, towing interference, speed flicker interference and Doppler blocking interference; the time domain convolution modulation structure generates clutter and echoes interfered by multiple false targets, and the time domain convolution modulation structure on each FPGA can generate the clutter or the multiple false targets with the distance of 37.5 kilometers at most.
Furthermore, the point target modulation structure comprises three modulation branches, the modulation process of each modulation branch comprises time delay, amplitude modulation and phase modulation, and 1-3 point target type echo combinations with mutually independent modulation parameters can be simultaneously generated through superposition.
Furthermore, the clock unit adopts a clock driving chip to generate a 1800MHz clock signal to the acquisition playback unit as a sampling clock.
Further, the interface unit adopts an RS485 serial port transmission line to complete communication between the main control computer and the composite echo signal simulator.
Further, the digital signal processor adopts a DSP TMS320C6455 chip.
Furthermore, the FPGA adopts a Virtex6 SX315T chip.
Further, the acquisition playback unit, the clock unit, the receiving modulation unit, the modulation calculation unit and the interface unit are all integrated on one board card (for example, a DRFM2500 board).
Has the advantages that: the invention is based on DRFM2500 board as hardware platform, has two high and low gain receiving and processing channels and three echo signal generating channels, compared with the prior art, the invention includes the following advantages:
1. the analog output of the target, the clutter and the interference can be simultaneously realized, and the parallel processing of point target modulation and time domain convolution modulation can simultaneously simulate the composite echo of the target, the clutter and various interferences;
2. the cascade connection of the time domain convolution modulation structure can enlarge the range coverage of clutter or multi-false target echoes, and the coverage is in direct proportion to the number of cascaded FPGA chips.
Drawings
FIG. 1 is a schematic view of the overall structure of the present invention;
FIG. 2 is a detailed structural schematic diagram of the present invention;
FIG. 3 is a schematic diagram of an FPGA module of the present invention;
FIG. 4 is a schematic diagram of a signal modulation sub-module according to the present invention;
FIG. 5 is a schematic diagram of a point target modulation scheme according to the present invention;
FIG. 6 is a schematic diagram of a time-domain convolutional modulation structure in the present invention;
FIG. 7 is a diagram showing an example of a composite signal simultaneously outputting interference, a target, and a clutter in an embodiment;
fig. 8 is a graph of a false target interferer generated by an embodiment covering 75km (500 us).
Detailed Description
The technical solution of the present invention is described in detail below, but the scope of the present invention is not limited to the embodiments.
As shown in fig. 1, the composite echo signal simulator of the present invention includes a clock unit, an acquisition playback unit, a clock unit, a receiving modulation unit, a modulation calculation unit, and an interface unit; the receiving and modulating unit is respectively connected with the acquisition and playback unit, the modulation calculation unit and the interface unit, and the clock unit is connected with the acquisition and playback unit and sends a clock signal to the acquisition and playback unit; the acquisition playback unit comprises two analog-to-digital conversion modules (ADC) and three digital-to-analog converters (DAC); the two analog-to-digital conversion modules respectively convert the received two paths of analog signals with different gains (a high-gain channel intermediate-frequency analog signal and a low-gain channel intermediate-frequency analog signal) into digital signals in an analog-to-digital manner, and send the converted digital signals to the receiving modulation unit; the three digital-to-analog converters convert the three paths of intermediate frequency digital echo signals (intermediate frequency clutter/interference signals and intermediate frequency target echo signals) received from the receiving and modulating unit into analog signals in a digital-to-analog manner; the receiving modulation unit comprises two FPGAs; the two FPGAs are connected through a high-speed differential interconnection line and respectively receive intermediate-frequency digital signals sent by the corresponding analog-to-digital conversion module, modulation data and instruction return information sent by the modulation calculation unit and control instructions and setting parameters of the interface unit; then the control instruction and the setting parameter received from the interface unit are sent to a modulation calculation unit, then the echo signal modulated by the modulation unit is sent to a digital-to-analog conversion module, and the modulation calculation unit sends back information to the interface unit according to the received control instruction and the setting parameter; the modulation calculation unit comprises a digital signal processor, receives the control instruction and the setting parameter transmitted by the receiving modulation unit through the digital signal processor, then calculates the modulation data of the target echo/clutter/interference signal, and transmits the modulation data or instruction return information to the receiving modulation unit; the interface unit receives a control instruction and a setting parameter sent by an external main control computer through a serial port and sends the control instruction and the setting parameter to the receiving modulation unit, or receives return data from the receiving modulation unit and sends the return data to the main control computer.
In the two paths of high-low gain intermediate frequency signals in this embodiment, the maximum gain of the intermediate frequency high gain channel is greater than or equal to 10dB, and the maximum gain of the intermediate frequency low gain channel is greater than or equal to-20 dB.
As shown in fig. 2 and fig. 3, the receiving modulation unit of this embodiment is mainly used for performing digital channel analysis on a single-channel digital signal according to a clock signal, setting a detection threshold in each channel, performing PDW measurement on the digital signal passing through the detection threshold, sending an obtained PDW parameter to the modulation calculation unit, simultaneously performing selective storage of modulation data according to a signal detection result, then performing modulation of a target echo, a clutter and an interference signal on modulation information sent by the modulation calculation unit 4 and the stored modulation data, and performing channel synthesis to form three paths of intermediate frequency echo signals, and sending the three paths of intermediate frequency echo signals to the acquisition playback unit 2; the digital channelization analysis is to extract the obtained single-channel digital signals into multiple channels of signals at equal time intervals according to a clock signal for parallel transmission, and simultaneously, each channel for parallel transmission is a channel, and the obtained digital signals are extracted into multiple channels of signals for transmission, so that the advantages of improving the detection signal-to-noise ratio and reducing the information modulation rate can be achieved.
The invention can simultaneously collect and process two paths of high-low gain intermediate frequency radar signals and can simultaneously output three paths of intermediate frequency analog echo signals, namely: the analog-to-digital conversion module of the acquisition playback unit converts the received two paths of analog signals with different gains into digital signals and sends the digital signals to the receiving modulation unit; and converting the three paths of intermediate frequency digital echo signals given by the receiving and modulating unit 3 into three paths of intermediate frequency analog echo signals by a digital-to-analog converter of the acquisition and playback unit. The acquisition playback unit of the embodiment can realize efficient transmission and conversion of signals by adopting the structure, and is convenient for subsequent signal processing.
As shown in fig. 3, the receiving and modulating unit 3 of the present embodiment includes two pieces of FPGA301; receiving the intermediate frequency digital signal provided by the analog-to-digital conversion module 201, the modulation data and instruction return information sent by the modulation calculation unit 4, and the control instruction and setting parameters of the receiving interface unit 5 through the FPGA301; and the processing unit is configured to send the control instruction and the setting parameter of the interface unit 5 to the modulation calculation unit 4, send the modulated echo signal to the digital-to-analog conversion module 202, and send the returned information given by the modulation calculation unit 4 to the interface unit 5. The receiving modulation unit 3 can also be responsible for receiving the clock signal of the clock unit 1, controlling the working timing of the whole receiving modulation unit 3, and meanwhile, being a data channel for communication between the modulation calculation unit 4 and the interface unit 5.
The FPGA301 of this embodiment includes a signal receiving and detecting sub-module, a PDW parameter measuring sub-module, a signal data buffering sub-module, and a signal modulating sub-module; the signal receiving and detecting submodule performs digital channel analysis and signal detection on the received intermediate-frequency digital signal sent by the analog-to-digital conversion module 201, and a detection result is used for controlling a receiving-transmitting wave gate and is simultaneously transmitted to the PDW parameter measuring submodule and the signal data caching submodule; the PDW parameter measurement submodule completes the measurement functions of pulse width, repetition period, amplitude, starting frequency, arrival time, bandwidth, center frequency, intra-pulse modulation type and intra-pulse modulation parameters of PDW to generate PDW parameters; the signal data cache submodule receives the detection result of the signal receiving detection submodule, locks the channel number of the signal, selects and stores m paths of signal data of channels required from input N paths of channel data, and transmits the signal data to the signal modulation submodule; and the signal modulation submodule receives the modulation data sent by the modulation calculation unit 4 and the signal data output by the signal data caching submodule, and completes the modulation of the target echo/clutter/interference signal.
As shown in fig. 4, the signal modulation submodule of this embodiment implements combined output of multiple echo signal patterns and multiple interference types by using parallel processing of point target modulation and time domain convolution modulation and a method of cascading time domain convolution modulation structures. The concrete content is as follows:
the signal modulation submodule on the same FPGA realizes the output of the point target type echo signal/clutter/multi-false target interference signal by parallel processing of the point target modulation structure and the time domain convolution modulation structure; the time domain convolution modulation structures on different FPGAs are cascaded, namely the time domain convolution modulation structures on two pieces of FPGAs 301 adopt a cascading mode, namely the time domain convolution modulation starting distance delay on the second piece of FPGA301 is linked with the time domain convolution modulation farthest distance delay on the first piece of FPGA301, so that clutter or multiple false targets with the distance coverage of at most 75 kilometers are realized; the point target modulation structure carries out time delay and amplitude phase modulation on input signal data after channel analysis to generate point target type echoes, wherein the point target type echoes comprise target echoes, track false target interference, dragging interference, speed flicker interference and Doppler blocking interference; the time domain convolution modulation structure generates clutter and echoes interfered by multiple false targets, and the time domain convolution modulation structure on each FPGA301 can generate the clutter or the multiple false targets with the distance coverage range of 37.5 kilometers at most.
As shown in fig. 4. The point target modulation structure comprises three modulation branches and can simultaneously generate 1-3 point target type echo combinations with mutually independent modulation parameters, wherein the point target type echoes comprise target echoes, track false target interference, towing interference, speed flicker interference and Doppler blocking interference.
As shown in fig. 5, the time domain convolution modulation structure of this embodiment is used to generate echoes with clutter and multiple false target interference, and the time domain convolution modulation structure on each of the above FPGAs 301 can generate clutter or multiple false targets with a distance coverage of 37.5 km at most.
As shown in fig. 2, the modulation calculation unit of the present embodiment includes a digital signal processor 401; and the digital signal processor (a chip of the DSP TMS320C 6455) receives the control command and the setting parameter transmitted by the receiving modulation unit 3, completes the modulation data calculation of the target echo/clutter/interference signal, and sends the modulation data or command return information to the receiving modulation unit 3.
Specifically, the modulation calculation unit 4 is responsible for receiving a control instruction and setting parameters, and completing the tasks of instruction analysis, system working mode switching control, modulation information calculation and downloading of target echo/clutter/interference signals, input/output power control, instruction feedback and the like.
The composite echo signal effect obtained in the invention is embodied by a digital signal processing algorithm on one hand, and is also based on a hardware architecture and a hardware platform on the other hand, wherein the hardware platform comprises:
the DSP TMS320C6455 chip is adopted, so that the operation efficiency of the system can be improved;
more preferably, the FPGA301 is a chip with a model number Virtex6 SX 315T;
the Virtex6 SX315T chip is used as the FPGA301, which is the optimal result of the applicant through chip resource overhead evaluation, and the chip improves the running speed of the composite echo signal simulator;
in this embodiment, each unit (clock unit, acquisition playback unit, clock unit, receiving modulation unit, modulation calculation unit and interface unit) is integrated on one DRFM2500 board.
The specific working principle of the invention is as follows:
after the equipment is powered on, the system carries out initialization setting. The acquisition playback unit 2 respectively performs analog-to-digital conversion, digital channelized reception and detection and PDW parameter measurement on the intermediate frequency analog signals of the high-low gain channel. When the interface unit 5 receives an instruction sent by the main control computer, the instruction is transmitted to the modulation calculation unit 4 through the receiving modulation unit 3. The modulation calculation unit 4 analyzes the instruction and controls the working state of the system according to the result of the instruction analysis. If the working state of the system is self-checking, starting the system self-checking and returning a self-checking result; and if the working state of the system is the simulation of target echo, clutter and interference signals, starting the generation of echo signals. At this time, the modulation calculation unit 4 calculates corresponding modulation information according to the setting parameters of the target echo, the clutter and the interference signal and sends the corresponding modulation information to the receiving modulation unit 3, the receiving modulation unit 3 performs caching according to signal data selected by the channelization detection result, performs corresponding signal modulation with the modulation information given by the modulation calculation unit 4, outputs an intermediate frequency digital echo signal to the acquisition playback unit 2 after channel synthesis, and then performs digital-to-analog conversion by the acquisition playback unit 2 to output an intermediate frequency echo analog signal.
Examples of the target, interference, and clutter composite signals generated by the composite echo signal simulator of the present invention are shown in fig. 7 and 8. Fig. 7 shows that the composite signal of interference, target and clutter is output simultaneously, yellow is the reference pulse signal transmitted by the radar, blue is the target echo output by the target channel, and pink is the composite signal of clutter and multi-false target interference. FIG. 8 shows the generation of a false target interference signal covering 75km (500 us) by two-slice FPGA time domain convolution structure cascade.
Claims (9)
1. A composite echo signal simulator, characterized by: the device comprises a clock unit, an acquisition playback unit, a clock unit, a receiving modulation unit, a modulation calculation unit and an interface unit; the receiving and modulating unit is respectively connected with the acquisition and playback unit, the modulation and calculation unit and the interface unit, and the clock unit is connected with the acquisition and playback unit and sends a clock signal to the acquisition and playback unit;
the acquisition playback unit comprises two analog-to-digital conversion modules ADC and three digital-to-analog converters DAC; the two analog-to-digital conversion modules respectively convert the received two paths of analog signals with different gains into digital signals in an analog-to-digital mode and send the converted digital signals to the receiving modulation unit; the three digital-to-analog converters convert the three paths of intermediate frequency digital echo signals received from the receiving and modulating unit into analog signals in a digital-to-analog mode;
the receiving modulation unit comprises two FPGAs; the two FPGAs are connected through a high-speed differential interconnection line and respectively receive intermediate-frequency digital signals sent by the corresponding analog-to-digital conversion module, modulation data and instruction return information sent by the modulation calculation unit and control instructions and setting parameters of the interface unit; then the control instruction and the setting parameter received from the interface unit are sent to a modulation calculation unit, then the echo signal modulated by the modulation calculation unit is sent to a digital-to-analog conversion module, and the modulation calculation unit sends back information to the interface unit according to the received control instruction and the setting parameter;
the modulation calculation unit comprises a digital signal processor, receives the control instruction and the setting parameter transmitted by the receiving modulation unit through the digital signal processor, then calculates the modulation data of the target echo/clutter/interference signal, and transmits the modulation data or instruction return information to the receiving modulation unit;
the interface unit receives a control instruction and a setting parameter sent by an external main control computer through a serial port and sends the control instruction and the setting parameter to the receiving modulation unit, or receives return data sent by the receiving modulation unit and sends the return data to the main control computer.
2. The composite echo signal simulator of claim 1, wherein: the FPGA comprises a signal receiving detection submodule, a PDW parameter measurement submodule, a signal data cache submodule and a signal modulation submodule;
the signal receiving and detecting submodule carries out digital channel analysis and signal detection on the intermediate-frequency digital signal sent by the analog-to-digital conversion module, and a detection result is used for receiving and transmitting wave gate control and is simultaneously transmitted to the PDW parameter measuring submodule and the signal data caching submodule; the digital channelization analysis is to extract the obtained single-channel digital signals into multi-channel signals at equal time intervals according to a clock signal for parallel transmission, and simultaneously, each parallel transmission channel is a channel, and the obtained digital signals are extracted into the multi-channel signals for transmission, so that the advantages of improving the detection signal-to-noise ratio and reducing the information modulation rate can be achieved;
the PDW parameter measurement submodule measures pulse width, repetition period, amplitude, starting frequency, arrival time, bandwidth, central frequency, intra-pulse modulation type and intra-pulse modulation parameters of PDW, generates PDW parameters and then sends the PDW parameters to the modulation calculation unit;
the signal data cache submodule selects and caches signal data of the detection result of the signal receiving detection submodule;
and the signal modulation submodule performs convolution operation on the modulation data received from the modulation calculation unit and the signal data output by the signal data caching submodule, so that modulation of target echoes, clutter and multi-false-target interference signals is realized.
3. The composite echo signal simulator of claim 2, wherein: the signal modulation submodule on the same FPGA realizes the output of the point target type echo signal/clutter/multi-false target interference signal by parallel processing of the point target modulation structure and the time domain convolution modulation structure; the time domain convolution modulation structures on different FPGAs are cascaded, namely the time domain convolution modulation structures on two FPGAs adopt a cascading mode, namely the time domain convolution modulation initial distance delay on the second FPGA is connected with the time domain convolution modulation maximum distance delay on the first FPGA;
the point target modulation structure carries out time delay and amplitude phase modulation on input signal data after channel analysis to generate point target type echoes, wherein the point target type echoes comprise target echoes, track false target interference, dragging interference, speed flicker interference and Doppler blocking interference;
the time domain convolution modulation structure generates clutter and echoes interfered by multiple false targets, and the time domain convolution modulation structure on each FPGA generates clutter or multiple false targets with the distance of 37.5 kilometers away from the coverage range;
the echo signal pattern combination comprises one or more of any combination of target echo, clutter and interference signals;
the interference type combination comprises one or more of any combination of multi-decoy interference, track decoy interference, towing interference, speed flicker interference and Doppler blocking interference.
4. A composite echo signal simulator according to claim 3, wherein: the point target modulation structure comprises three modulation branches, the modulation process of each modulation branch comprises time delay, amplitude modulation and phase modulation, and 1-3 point target type echo combinations with mutually independent modulation parameters can be simultaneously generated through superposition.
5. The composite echo signal simulator of claim 1, wherein: the clock unit adopts a clock driving chip to generate 1800MHz clock signals to the acquisition playback unit as sampling clocks.
6. The composite echo signal simulator of claim 1, wherein: and the interface unit adopts an RS485 serial port transmission line to complete the communication between the main control computer and the composite echo signal simulator.
7. The composite echo signal simulator of claim 1, wherein: the digital signal processor adopts a DSP TMS320C6455 chip.
8. The composite echo signal simulator of claim 1, wherein: the FPGA adopts a Virtex6 SX315T chip.
9. The composite echo signal simulator of claim 1, wherein: the acquisition playback unit, the clock unit, the receiving modulation unit, the modulation calculation unit and the interface unit are integrated on a board card, and the board card supplies power to the clock unit, the acquisition playback unit, the clock unit, the receiving modulation unit, the modulation calculation unit and the interface unit from a 27v external direct current power supply through a power socket on the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211473944.1A CN115754946B (en) | 2022-11-22 | 2022-11-22 | Composite echo signal simulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211473944.1A CN115754946B (en) | 2022-11-22 | 2022-11-22 | Composite echo signal simulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115754946A true CN115754946A (en) | 2023-03-07 |
| CN115754946B CN115754946B (en) | 2023-10-20 |
Family
ID=85336046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211473944.1A Active CN115754946B (en) | 2022-11-22 | 2022-11-22 | Composite echo signal simulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115754946B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109001697A (en) * | 2018-08-14 | 2018-12-14 | 电子科技大学 | A kind of multiple target radar echo simulator |
| US20200110156A1 (en) * | 2018-10-09 | 2020-04-09 | Rohde & Schwarz Gmbh & Co. Kg | Radar target simulator and method for radar target simulation |
| CN213149226U (en) * | 2020-08-19 | 2021-05-07 | 南京胜宇研创科技有限公司 | Radar echo simulator |
| CN113835070A (en) * | 2021-09-27 | 2021-12-24 | 大连海天防务科技有限公司 | Radar tactical performance detection and anti-interference capability evaluation simulator |
| CN115047417A (en) * | 2022-08-15 | 2022-09-13 | 成都锐新科技有限公司 | Method and system for simulating radar echo and interference |
-
2022
- 2022-11-22 CN CN202211473944.1A patent/CN115754946B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109001697A (en) * | 2018-08-14 | 2018-12-14 | 电子科技大学 | A kind of multiple target radar echo simulator |
| US20200110156A1 (en) * | 2018-10-09 | 2020-04-09 | Rohde & Schwarz Gmbh & Co. Kg | Radar target simulator and method for radar target simulation |
| CN213149226U (en) * | 2020-08-19 | 2021-05-07 | 南京胜宇研创科技有限公司 | Radar echo simulator |
| CN113835070A (en) * | 2021-09-27 | 2021-12-24 | 大连海天防务科技有限公司 | Radar tactical performance detection and anti-interference capability evaluation simulator |
| CN115047417A (en) * | 2022-08-15 | 2022-09-13 | 成都锐新科技有限公司 | Method and system for simulating radar echo and interference |
Non-Patent Citations (1)
| Title |
|---|
| 卢丁丁 等: "一种雷达中频信号回波模拟系统的设计", 信息通信, no. 03 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115754946B (en) | 2023-10-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN212433393U (en) | Radar interference simulation equipment | |
| CN107728127B (en) | Radar simulation test system | |
| CN105629207B (en) | Radar Signal Processing System and intensive target jamming production method based on DRFM technology | |
| CN213210458U (en) | Radar target simulation and interference countermeasure training system | |
| CN110988830A (en) | Multi-frequency-band radar target simulator | |
| CN109031282A (en) | The system that a kind of electronic reconnaissance and radar detection work at the same time | |
| CN206400092U (en) | Multifunctional comprehensive signal simulator | |
| CN109917342B (en) | Radar simulation platform with medium-frequency signal and digital signal dual modes | |
| CN107367717B (en) | Radar multi-target intermediate frequency simulation device | |
| CN208805564U (en) | A kind of radar beacon machine | |
| CN112415482B (en) | Radio frequency injection type digital signal synthesis simulation test system | |
| CN112578346B (en) | Broadband radar target echo signal simulation system and simulation method | |
| CN104597440B (en) | Intelligent radar based on target motion match | |
| CN113835070A (en) | Radar tactical performance detection and anti-interference capability evaluation simulator | |
| CN108562892A (en) | A kind of UAV system passive bistatic radar device and object localization method | |
| CN202794515U (en) | Navigation radar for FMCW (frequency-modulated continuous wave) ship | |
| CN112799023A (en) | Multi-false-target interference method for fast forwarding | |
| CN109001697A (en) | A kind of multiple target radar echo simulator | |
| CN111025338A (en) | Method for simulating complex electromagnetic environment of satellite navigation terminal | |
| CN113608183B (en) | Hypersonic broadband radio frequency target simulation system | |
| CN114624658A (en) | Software reconfigurable jammer system and signal generation method | |
| CN213181996U (en) | Radar signal reconnaissance and interference signal generation calibration equipment | |
| CN111736129B (en) | Space-time modulation bistatic radar system, implementation method and medium thereof | |
| CN115754946B (en) | Composite echo signal simulator | |
| Fernandes | Implementation of a RADAR System using MATLAB and the USRP |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Building 4, Jiangguang Smart City East Garden, No. 15 Wenchang East Road, Guangling District, Yangzhou City, Jiangsu Province, 225006 Patentee after: Yangzhou Yuan Electronic Technology Co.,Ltd. Country or region after: China Address before: Building 4, Dongyuan, Jiangguang smart city, No. 15, Wenchang East Road, Guangling District, Yangzhou City, Jiangsu Province 225002 Patentee before: YANGZHOU YU'AN ELECTRONIC TECHNOLOGY CO.,LTD. Country or region before: China |
|
| CP03 | Change of name, title or address |