CN115754677A - Chip testing system and chip testing method - Google Patents

Abstract

The invention provides a chip test system, comprising: an automatic test machine that generates at least a set of test signals and a set of adjustment signals, wherein the test signals include positive side test signals and negative side test signals, and the adjustment signals include positive side adjustment signals and negative side adjustment signals; the adjusting circuit comprises a positive end adjusting module and a negative end adjusting module, the positive end adjusting module receives a positive end test signal and a positive end adjusting signal, and the negative end adjusting module receives a negative end test signal and a negative end adjusting signal, so that the voltage amplitude of the test signal is continuously adjusted based on the adjusting signal and/or common-mode noise is added to the test signal. The chip test system provided by the invention solves the problems that in the existing test system using ATE, the differential signal of ATE can not be subjected to continuous voltage amplitude change and common mode noise can not be directly added.

Description

Chip testing system and chip testing method

Technical Field

The invention relates to the technical field of chip testing, in particular to a chip testing system and a chip testing method.

Background

The serializer/deserializer (SERDES) can realize a higher signal transmission rate due to the characteristics of no associated clock, high tolerance to noise jitter, and the like. Nowadays, the signal interconnection rate is higher and higher, and the SERDES is therefore one of the mainstream high-speed interfaces of chips.

SERDES is generally composed of a transmitting end (TX) and a receiving end (RX). The main test of the RX is a signal tolerance test, wherein the test sends a pressurized Pseudo Random Binary Sequence (PRBS) signal to the RX through an automatic test machine (ATE), and a PRBS checker of the SERDES is used for judging whether the RX can correctly receive the signal; the pressurizing mode comprises the following steps: reducing voltage amplitude, adding timing jitter noise, adding voltage noise (i.e., common mode noise), speeding up or slowing down rates, etc.

For most pressurization modes, ATE can generally directly provide corresponding hardware and methods to implement; however, the ATE has no direct way to implement the following two specific pressurization conditions:

1) The voltage amplitude of the differential signal is continuously adjusted in real time. As shown in FIG. 1, V _DP And V _DN Positive terminal voltage and negative terminal voltage of differential signal, the voltage amplitude of the differential signal in stage 1 is V _OD1 The voltage amplitude at phase 2 is V _OD2 . The voltage amplitudes of the two phases are different and the transition from phase 1 to phase 2 is continuous in real time.

2) Common mode noise is added to the differential signal, which has the advantage of being resistant to common mode interference. As shown in FIG. 2, when common mode noise is present, the single-ended voltage V _DP And V _DN There is common mode noise with the same phase, while at the differential voltage V _DIFF The noise is not seen. The added common mode noise may be transient or periodic. In addition, testing requires that the voltage amplitude and frequency of the common mode noise be adjustable.

For the two pressurization conditions as above, the existing solutions are as follows:

when the RX is tested for receiving capability of different signal amplitudes, one feasible scheme is that the ATE sends signals with different voltage amplitudes for multiple times, and the chip performs signal correctness judgment on the signals with different voltage amplitudes. The ATE signal at this time is shown in FIG. 3, and the slave voltage has a magnitude V _OD1 Phase 1 to a voltage amplitude of V _OD2 With a period of time T in between. During this time T, the ATE needs to instruct the voltage amplitude of the transmission signal to change again, so that the chip RX cannot make a correct judgment on the signal during this time T. And after the voltage amplitude is modified and enters the stage 2, resetting the chip and then judging the correctness of the received signal again.

Because ATE is not capable of continuous voltage amplitude changes, the prior art solutions have the disadvantage of requiring separate testing of signals of different voltage amplitudes. On the one hand, the test cannot cover the condition that the voltage amplitude continuously changes; on the other hand, because the chip needs to be reset to enter the test state, the test time of the whole chip is increased. Moreover, ATE cannot directly add common mode noise and cannot cover RX tolerance tests for common mode noise.

Another feasible scheme is that a test platform is built by using a special test instrument instead of ATE, for example, a signal generator, a direct-current stabilized voltage supply, a Field Programmable Gate Array (FPGA), and the like are used for building a test system; based on the test specificity of the special test instrument, the method can send signals with continuous voltage amplitude changes and can add common-mode noise required by the test.

Compared to test systems using ATE, test systems built using dedicated test instruments have several significant drawbacks in chip volume production: firstly, the system is complicated to build, special personnel needing to know the participation of the system are built each time, and the built system is unstable and easily causes mass production interruption; and secondly, the number of signal channels limited to the test instrument is small, the number of multi-chip simultaneous tests which can be realized by the test system is small, and the output rate of chip mass production is influenced.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a chip testing system and a chip testing method, which are used to solve the problems that the differential signal of ATE cannot be changed continuously in voltage amplitude and common mode noise cannot be added directly in the existing testing system using ATE.

To achieve the above and other related objects, the present invention provides a chip testing system, comprising:

an automatic test machine that generates at least a set of test signals and a set of adjustment signals, wherein the test signals include a positive side test signal and a negative side test signal, and the adjustment signals include a positive side adjustment signal and a negative side adjustment signal;

the adjusting circuit comprises a positive end adjusting module and a negative end adjusting module, the positive end adjusting module receives the positive end test signal and the positive end adjusting signal, and the negative end adjusting module receives the negative end test signal and the negative end adjusting signal, so that the voltage amplitude of the test signal is continuously adjusted based on the adjusting signal and/or common-mode noise is added to the test signal.

Optionally, the positive end adjusting module and the negative end adjusting module are both implemented by three-resistor power dividers.

Optionally, in the three-resistor power divider, the resistance of each resistor is 50 Ω, and the insertion loss between the ports is 6dB.

Optionally, the chip test system further includes: and the test load board bears the adjusting circuit and the chip to be tested, and transmits signals among the automatic testing machine, the adjusting circuit and the chip to be tested.

Optionally, the adjusting circuit is disposed on the test load board in a patch manner.

The invention also provides a chip testing method, which comprises the following steps:

building the chip testing system recorded above;

and performing signal tolerance test on the SERDES chip based on the chip test system.

Optionally, the method for performing a signal tolerance test on the SERDES chip by reducing the voltage amplitude includes:

powering on the SERDES chip and entering a test mode;

the automatic tester generates two groups of differential signals, one group of differential signals is used as a test signal and has a first voltage amplitude, the other group of differential signals is used as an adjusting signal and has a second voltage amplitude, wherein the test signal is continuously output within a set time, the adjusting signal is continuously output at a first stage within the set time, and the output is stopped at a second stage;

the adjusting circuit continuously adjusts the voltage amplitude of the test signal based on the adjusting signal and generates an input signal, wherein the input signal has a third voltage amplitude in a first phase and a fourth voltage amplitude in a second phase, and the third voltage amplitude is larger than the fourth voltage amplitude;

and the SERDES chip performs a signal tolerance test based on the input signal.

Optionally, the third voltage amplitude is equal to half of a sum of the first voltage amplitude and the second voltage amplitude, and the fourth voltage amplitude is equal to half of the first voltage amplitude.

Optionally, the method for performing a signal tolerance test on the SERDES chip by adding common mode noise includes:

powering on the SERDES chip and entering a test mode;

the automatic test machine generates a group of differential signals and a group of single-ended signals, the differential signals serve as test signals and have a fifth voltage amplitude, and the two single-ended signals serve as adjusting signals and have the same voltage amplitude and phase;

the adjusting circuit adds common-mode noise to the test signal based on the adjusting signal and generates an input signal, wherein the input signal has a sixth voltage amplitude, and the sixth voltage amplitude is smaller than the fifth voltage amplitude;

and the SERDES chip performs a signal tolerance test based on the input signal.

Optionally, the sixth voltage magnitude is equal to half of the fifth voltage magnitude.

As described above, according to the chip test system and the chip test method of the present invention, the adjustment circuit is added to the existing test system using ATE to adjust the differential signal, so that the continuous change of the voltage amplitude of the differential signal can be realized, and the addition of the common mode noise to the differential signal is realized, thereby realizing the completion of the signal tolerance test of the SERDES chip by using ATE.

Drawings

Fig. 1 is a schematic diagram showing the continuous adjustment of the voltage amplitude of the differential signal during the signal tolerance test of the SERDES chip.

Fig. 2 is a schematic diagram illustrating the addition of common mode noise to the differential signal during the signal tolerance test of the SERDES chip.

Fig. 3 is a schematic diagram illustrating the adjustment of the voltage amplitude of the differential signal when a testing system using ATE performs a signal tolerance test on the SERDES chip.

FIG. 4 is a schematic diagram of a chip testing system according to the present invention.

Fig. 5 is a circuit diagram of a three-resistor power divider according to the present invention.

Fig. 6 is a waveform diagram of the related signals at the first stage when the chip testing system of the present invention performs the signal tolerance test on the SERDES chip based on the reduced voltage amplitude.

FIG. 7 is a waveform diagram of the related signals at the second stage when the chip testing system of the present invention performs the signal tolerance test on the SERDES chip based on the reduced voltage amplitude.

FIG. 8 is a waveform diagram of the related signals when the voltage amplitudes of the input signals are continuously switched in the chip testing system according to the present invention.

FIG. 9 is a diagram showing the waveforms of the signals involved in the signal tolerance test of the SERDES chip by the chip test system based on the addition of common mode noise.

Description of the element reference numerals

10. Chip testing system

100. Automatic testing machine

101. Power supply module

102. High speed digital module

103. Low speed digital module

200. Regulating circuit

201. Positive terminal adjustment module

202. Negative terminal adjustment module

300. Test load board

400. Chip to be tested

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 4 to fig. 9. It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

As shown in fig. 4, the present embodiment provides a chip testing system 10, where the chip testing system 10 includes: an automatic tester 100 and a regulating circuit 200; further, the chip testing system 10 further includes: the load board 300 is tested.

The automatic test machine 100 generates at least a set of test signals including a positive side test signal DP and a negative side test signal DN and a set of adjustment signals including a positive side adjustment signal SP and a negative side adjustment signal SN.

Specifically, the automatic tester 100 includes: a power module 101, a high-speed digital module 102, and a low-speed digital module 103.

Wherein the content of the first and second substances,

the power module 101 not only supplies power to the automatic tester 100, but also generates a power supply signal to supply power to the chip 400 to be tested; certainly, when the chip testing system 10 further includes the test load board 300, the power module 101 further generates another power supply signal to supply power to the test load board 300; the supply voltages of the two power supply signals may be the same or different, and are determined by the power supply requirements of the test load board 300 and the chip 400 to be tested.

The high-speed digital module 102 includes at least two groups of differential circuit units for generating test signals and adjustment signals; certainly, if it is desired to realize the simultaneous testing of a plurality of chips 400 to be tested, the number of differential circuit units in the high-speed digital module 102 and the number of corresponding adjusting circuits 200 may be expanded (for one chip 400 to be tested, two sets of differential circuit units and one adjusting circuit 200 are required), in practical applications, the number of differential circuit units is usually greater than 10, and may even be greater than 20; wherein the test signal and the conditioning signal are high speed signals, such as GHz level signals.

In addition, the automatic tester 100 can control whether each differential circuit unit in the high-speed digital module 102 outputs, when to output, and whether to output the differential circuit unit or the single-ended output by a program, and can even control parameters such as amplitude, phase, frequency, etc. of the output signal, which are conventional functions of the automatic tester 100, and how to control is not described in detail herein.

The low-speed digital module 103 includes a clock unit and a control unit, wherein the clock unit is configured to generate a clock signal, and the control unit is configured to generate a control signal, such as a register configuration signal, so as to complete the test mode setting of the chip 400 to be tested according to the clock signal and the control signal, so that the chip 400 to be tested enters a test mode; the clock signal and the control signal are low-speed signals, such as signals in the MHz level.

The adjusting circuit 200 includes a positive end adjusting module 201 and a negative end adjusting module 202, the positive end adjusting module 201 receives a positive end test signal DP and a positive end adjusting signal SP, and the negative end adjusting module 202 receives a negative end test signal DN and a negative end adjusting signal SN to continuously adjust a voltage amplitude of the test signal and/or add common mode noise to the test signal based on the adjusting signal.

Specifically, as shown in fig. 5, the positive terminal adjusting module 201 and the negative terminal adjusting module 202 are both implemented by three-resistor power dividers (also called combiners); wherein, the three resistance type merit divides the ware to include: the three-resistor power divider comprises a first resistor R1, a second resistor R2 and a third resistor R3, wherein the first ends of the three resistors are connected with each other, and the second ends are used as three ports of the three-resistor power divider; for example, the second terminal of the first resistor R1 is the port a, the second terminal of the second resistor R2 is the port B, and the second terminal of the third resistor R3 is the port C.

More specifically, in the three-resistor power divider, the resistance values of the resistors are all 50 Ω, and the insertion loss between the ports is all 6dB; that is, R1= R2= R3=50 Ω, the insertion loss between the port a and the port B is 6dB, the insertion loss between the port a and the port C is 6dB, and the insertion loss between the port B and the port C is 6dB.

In the three-resistor power divider of this embodiment, when a signal is input from any one of the ports and then output from the other two ports, the voltage amplitudes of the signals at the two output ports are both half of the voltage amplitude of the signal at the input port; by utilizing the symmetry of each port, when signals are input from the two ports and then output from the third port, the voltage amplitude of the signal at the output port is half of the sum of the voltage amplitudes of the signals at the two input ports; thereby, it is achieved that the voltage amplitude of the test signal is continuously adjusted based on the adjustment signal and/or that common mode noise is added to the test signal based on the adjustment signal.

The test load board 300 carries the conditioning circuit 200 and the chip 400 to be tested, and performs signal transmission among the automatic test machine 100, the conditioning circuit 200, and the chip 400 to be tested. For chip testing, the use of the test load board is beneficial to realizing multi-chip simultaneous testing, and the chip can be prevented from being damaged due to external force in the testing process.

In practical applications, the chip 400 to be tested may be inserted into the test load board 300 through a mounting card, or may be directly mounted on the test load board 300, which has no substantial effect on the embodiment. In addition, the adjusting circuit 200 is directly arranged on the test load board 300, and each resistor therein can adopt a direct insertion mode or a patch mode, so that the stability of the whole system is improved, and the system is simple to build; however, due to many considerations such as process, size, and expansion, the adjustment circuit 200 is generally mounted on the test load board 300 in a patch manner.

Correspondingly, the embodiment further provides a chip testing method, which includes: the chip testing system 10 as described above is constructed, and a signal tolerance test is performed on the SERDES chip based on the chip testing system 10.

The method comprises the steps of carrying out signal tolerance test on the SERDES chip, mainly sending a pressurized input signal (such as a PRBS signal) to the SERDES chip, and judging whether a receiving end of the SERDES chip can correctly receive the signal by utilizing a checker (such as a PRBS checker) carried by the SERDES chip so as to finish the signal tolerance test. Wherein, the mode of pressurization includes: reducing voltage amplitude, adding timing jitter noise, adding voltage noise (i.e., common mode noise), speeding up or slowing down rates, etc.

Specifically, a signal tolerance test is performed on the SERDES chip by reducing the voltage amplitude, that is, the voltage amplitude of the signal input to the SERDES chip is reduced, and whether a receiving end of the SERDES chip can correctly receive the signal is judged.

Step 1.1) powering on the SERDES chip and entering a test mode.

The SERDES chip is powered on by the power module 101 in the automatic tester 100 and enters a test mode by the clock signal and the control signal generated by the low speed digital module 103.

Step 1.2) the automatic tester 100 generates two sets of differential signals, one set of differential signals is used as a test signal and has a first voltage amplitude, and the other set of differential signals is used as an adjusting signal and has a second voltage amplitude, wherein the test signal is continuously output within a set time, the adjusting signal is continuously output at a first stage within the set time, and the output is stopped at a second stage.

The two differential circuit units of the high-speed digital module 102 in the automatic test machine 100 are controlled, so that one differential circuit unit continuously outputs a differential signal with a first voltage amplitude within a set time, and the other differential circuit unit continuously outputs a differential signal with a second voltage amplitude in a first stage within the set time and stops outputting in a second stage.

In this embodiment, the first stage and the second stage within the setting time are continuous without any break in the middle, that is, the start point of the first stage is the start point of the setting time, the end point of the first stage is the start point of the second stage, and the end point of the second stage is the end point of the setting time.

Step 1.3) the adjusting circuit 200 continuously adjusts the voltage amplitude of the test signal based on the adjusting signal and generates an input signal, wherein the input signal has a third voltage amplitude in the first phase and a fourth voltage amplitude in the second phase, and the third voltage amplitude is greater than the fourth voltage amplitude.

The input signals comprise a positive terminal input signal RXP and a negative terminal input signal RXN;

in the first stage, the test signal has a first voltage amplitude V ₁ The regulating signal has a second voltage amplitude V ₂ At this time, the voltage amplitude of the positive terminal test signal

Voltage amplitude of negative terminal test signal

Voltage amplitude of positive side adjustment signal

The negative terminal adjusts the voltage amplitude of the signal

By usingCharacteristics of three-resistor power divider, voltage amplitude of positive input signal

Voltage amplitude of negative side input signal

Thus, the voltage amplitude of the input signal

That is, the input signal has a third voltage magnitude, and the third voltage magnitude is equal to half of the sum of the first voltage magnitude and the second voltage magnitude, as shown in fig. 6;

in the second stage, the test signal has a first voltage amplitude V ₁ The adjusting signal is not output, that is, the voltage amplitude of the adjusting signal is zero, and at this time, the voltage amplitude of the positive terminal test signal

Voltage amplitude of negative terminal test signal

Voltage amplitude V of the positive side regulation signal _SP =0, negative terminal adjusts voltage amplitude V of signal _SN =0; the voltage amplitude of the input signal at the positive terminal is obtained by utilizing the characteristics of the three-resistor power divider

Voltage amplitude of negative side input signal

Thus, the voltage amplitude of the input signal

That is, the input signal has a fourth voltage amplitude, and the fourth voltage amplitude is equal to half of the first voltage amplitude, as shown in fig. 7;

since the first phase and the second phase are consecutive in time, an input signal with continuously dynamically switched voltage amplitudes as shown in fig. 8 can be obtained. The test signal is used as a main signal and has a fixed voltage amplitude, the regulating signal is used as an auxiliary signal, when the input signal needs a large voltage amplitude, the regulating signal is controlled to be output and has a fixed voltage amplitude, and when the input signal needs a small voltage amplitude, the regulating signal is controlled not to be output; by the mode, the signals input to the SERDES chip can be continuously switched from large voltage amplitude to small voltage amplitude without stopping signal transmission of the automatic test machine 100 midway, and the signals switched to the small voltage amplitude are continuously transmitted after the voltage amplitude changing instruction takes effect.

In practical applications, the first voltage amplitude and the second voltage amplitude may be reasonably designed according to the expected voltage amplitude (i.e. the third voltage amplitude) and the reduced value thereof (i.e. the fourth voltage amplitude), where the first voltage amplitude and the second voltage amplitude may be the same or different, which has no substantial effect on the embodiment.

And step 1.4) carrying out signal tolerance test on the SERDES chip based on the input signal.

After the input signal is sent to the SERDES chip, a checker of the SERDES chip can judge whether the receiving end correctly receives the input signal, and the function of the SERDES chip is judged according to the judgment result.

If the input signal with the third voltage amplitude is sent to the SERDES chip, a checker carried by the SERDES chip can judge whether the receiving end correctly receives the input signal; if the receiving end is judged to correctly receive the input signal, the function of the SERDES chip under the test condition is judged to be basically normal, and the pressurization test is continued; if the receiving end is judged not to correctly receive the input signal, judging that the function of the SERDES chip under the test condition is abnormal, recording the current test condition, and ending the test;

continuing to perform the pressurization test, namely after the input signal with the fourth voltage amplitude is sent to the SERDES chip, judging whether the receiving end correctly receives the input signal by a checker of the SERDES chip; if the receiving end is judged to correctly receive the input signal, the function of the SERDES chip under the test condition is judged to be basically normal, and the test is finished; if the receiving end is judged not to correctly receive the input signal, the function of the SERDES chip under the test condition is judged to be abnormal, the current test condition is recorded, and the test is finished.

Specifically, a signal tolerance test is performed on the SERDES chip by adding the common mode noise, that is, the common mode noise is added to the signal input to the SERDES chip, and whether a receiving end of the SERDES chip can correctly receive the signal is judged.

And 2.1) powering on the SERDES chip and entering a test mode.

The SERDES chip is powered on by the power module 101 in the automatic tester 100 and enters a test mode by the clock signal and the control signal generated by the low speed digital module 103.

Step 2.2) the automatic tester 100 generates a group of differential signals and a group of single-ended signals, wherein the differential signals are used as test signals and have a fifth voltage amplitude, and the two single-ended signals are used as adjusting signals and have the same voltage amplitude and phase; the frequency of the single-ended signal can be set according to actual requirements.

And controlling the two differential circuit units of the high-speed digital module 102 in the automatic tester 100, so that one differential circuit unit differentially outputs a differential signal with a fifth voltage amplitude, and the other differential circuit unit single-end outputs a single-end signal with a fixed voltage amplitude, frequency and phase.

Step 2.3) the adjusting circuit 200 adds common mode noise to the test signal based on the adjusting signal and generates an input signal, wherein the input signal has a sixth voltage amplitude, and the sixth voltage amplitude is smaller than the fifth voltage amplitude.

The test signal is a differential signal with a fifth voltage amplitude, and the adjusting signal is a single-ended signal with fixed voltage amplitude, frequency and phase and can be regarded as common-mode noise; by utilizing the characteristics of the three-resistor power divider, common-mode noise can be added to the positive terminal test signal DP and the negative terminal test signal DN, so that a positive terminal input signal RXP and a negative terminal input signal RXN which are respectively added with the common-mode noise are obtained, namely, input signals added with the common-mode noise are obtained; for is toFor differential input signals, the single-ended voltage V _RXP And V _RXN The common mode noise exists, but the differential signal can finally generate the differential voltage V due to the inhibition effect of the differential signal on the common mode noise _DIFF The common mode noise is invisible; also, the sixth voltage amplitude is equal to half the fifth voltage amplitude, as shown in fig. 9. In practical application, the fifth voltage amplitude can be reasonably designed according to the expected voltage amplitude (namely, the sixth voltage amplitude), and the expected chip test coverage can be realized by reasonably designing the voltage amplitude and the frequency of the common-mode noise. And 2.4) carrying out a signal tolerance test on the SERDES chip based on the input signal.

After the input signal is sent to the receiving end of the SERDES chip, the checker of the SERDES chip can judge whether the receiving end correctly receives the input signal, and the function of the SERDES chip is judged according to the judgment result.

If common-mode noise with fixed voltage amplitude and frequency is added to the input signal and the input signal is sent to the SERDES chip, a checker of the SERDES chip can judge whether the receiving end correctly receives the input signal; if the receiving end is judged to correctly receive the input signal, the function of the SERDES chip under the test condition is judged to be basically normal, and the pressurization test is continued; if the receiving end is judged not to correctly receive the input signal, judging that the function of the SERDES chip under the test condition is abnormal, recording the current test condition, and ending the test; wherein the stress test is continued by changing the voltage amplitude and/or frequency of the common mode noise to deteriorate the test conditions to repeat the test until the SERDES chip fails to receive the signal correctly.

Specifically, a signal tolerance test is carried out on the SERDES chip by adding timing sequence jitter noise, namely, the timing sequence jitter noise is added to the signal input to the SERDES chip, and whether a receiving end can correctly receive the signal is judged; the automatic tester 100 may add timing jitter noise to a signal input to the SERDES chip, so that the automatic tester 100 is controlled to make no adjustment signal output during the test, and the test scheme is the same as the existing scheme, which is not described herein again.

The signal tolerance test is carried out on the SERDES chip by accelerating or slowing down the speed, namely, the speed of the signal input to the SERDES chip is accelerated or slowed down, and whether the receiving end can correctly receive the signal is judged; the automatic tester 100 can accelerate or decelerate the rate of the signal input to the SERDES chip, and therefore, in the testing process, the automatic tester 100 is controlled to make the adjustment signal output nothing, and the testing scheme is the same as the existing scheme, and is not described here again.

In summary, according to the chip test system and the chip test method of the present invention, the adjustment circuit is added to the existing test system using ATE to adjust the differential signal, so that the continuous change of the voltage amplitude of the differential signal can be realized, and the addition of the common mode noise to the differential signal is realized, thereby realizing the signal tolerance test of the SERDES chip by using ATE. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (10)

1. A chip test system, comprising:

an automatic test machine that generates at least a set of test signals and a set of adjustment signals, wherein the test signals include a positive side test signal and a negative side test signal, and the adjustment signals include a positive side adjustment signal and a negative side adjustment signal;

the adjusting circuit comprises a positive end adjusting module and a negative end adjusting module, the positive end adjusting module receives the positive end test signal and the positive end adjusting signal, and the negative end adjusting module receives the negative end test signal and the negative end adjusting signal, so that the voltage amplitude of the test signal is continuously adjusted based on the adjusting signal and/or common-mode noise is added to the test signal.

2. The chip test system according to claim 1, wherein the positive side regulation module and the negative side regulation module are implemented by three-resistor type power dividers.

3. The chip test system according to claim 2, wherein in the three-resistor power divider, the resistance of each resistor is 50 Ω, and the insertion loss between the ports is 6dB.

4. The chip test system according to any one of claims 1 to 3, further comprising: and the test load board bears the adjusting circuit and the chip to be tested, and transmits signals among the automatic testing machine, the adjusting circuit and the chip to be tested.

5. The chip test system according to claim 4, wherein the regulating circuit is disposed on the test load board in a patch manner.

6. A chip testing method is characterized by comprising the following steps:

building a chip testing system according to any one of claims 1-5;

and performing signal tolerance test on the SERDES chip based on the chip test system.

7. The chip testing method of claim 6, wherein the method for performing the signal tolerance test on the SERDES chip by reducing the voltage amplitude comprises:

powering on the SERDES chip and entering a test mode;

the automatic tester generates two groups of differential signals, one group of differential signals is used as a test signal and has a first voltage amplitude, the other group of differential signals is used as an adjusting signal and has a second voltage amplitude, wherein the test signal is continuously output within a set time, the adjusting signal is continuously output at a first stage within the set time, and the output is stopped at a second stage;

the adjusting circuit continuously adjusts the voltage amplitude of the test signal based on the adjusting signal and generates an input signal, wherein the input signal has a third voltage amplitude in a first phase and a fourth voltage amplitude in a second phase, and the third voltage amplitude is greater than the fourth voltage amplitude;

and the SERDES chip performs a signal tolerance test based on the input signal.

8. The chip testing method according to claim 7, wherein the third voltage magnitude is equal to half of a sum of the first voltage magnitude and the second voltage magnitude, and the fourth voltage magnitude is equal to half of the first voltage magnitude.

9. The chip testing method of claim 6, wherein the method for performing the signal tolerance test on the SERDES chip by adding the common mode noise comprises:

powering on the SERDES chip and entering a test mode;

the automatic tester generates a group of differential signals and a group of single-ended signals, the differential signals are used as test signals and have a fifth voltage amplitude, and the two single-ended signals are used as adjusting signals and have the same voltage amplitude and phase;

the adjusting circuit adds common-mode noise to the test signal based on the adjusting signal and generates an input signal, wherein the input signal has a sixth voltage amplitude, and the sixth voltage amplitude is smaller than the fifth voltage amplitude;

and the SERDES chip performs a signal tolerance test based on the input signal.

10. The chip testing method according to claim 9, wherein the sixth voltage magnitude is equal to half of the fifth voltage magnitude.

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