CN115733502B - Reconfigurable communication transmitter and method - Google Patents
Reconfigurable communication transmitter and method Download PDFInfo
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Abstract
The invention discloses a reconfigurable communication transmitter and a method, wherein the transmitter comprises: the baseband generating circuit is used for generating a digital baseband signal and outputting different data control bits so as to realize switching of different modulation modes; the digital phase shifter is used for receiving an input signal and carrying out phase switching on the input signal according to the data control bit; the quadrature signal generator is used for receiving the frequency signal output by the digital phase shifter and outputting IQ two paths of quadrature signals; the digital power amplifier comprises a first amplifier and a second amplifier, and is used for respectively modulating and amplifying signals of an I path and a Q path according to data control bits; and the output synthesis end is used for synthesizing the modulation signals output by the first amplifier and the second amplifier and outputting a synthesized signal. The invention adopts direct modulation to realize high-speed communication, and reduces the requirement for a digital-to-analog converter. The invention can be widely applied to the technical field of communication.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a reconfigurable communication transmitter and a method.
Background
The millimeter wave communication transmitter is used as a key part of the radio frequency front-end system, and the performance of the millimeter wave communication transmitter directly determines the communication distance and the signal quality of the whole system. Under the condition of ensuring the indexes such as output power, how to improve the communication rate and the quality of communication information of a transmitter and reduce the power consumption is always the key point and the difficulty of a high-speed communication transmitter.
In the existing high-speed communication transceiver design, a high-precision high-speed digital-to-analog converter (DAC/ADC) is mostly used, but the power consumption brought by the part reaches a watt level, so that the power consumption of the whole communication system is greatly improved. In addition, the transmitter with the traditional structure has higher requirements on the linearity of the power amplifier and the efficiency of the back-off power point when performing high-order QAM modulation, so that the high-order QAM modulation in the millimeter wave band becomes more difficult to realize and has low energy efficiency.
Disclosure of Invention
In order to solve at least one of the technical problems existing in the prior art to a certain extent, the invention aims to provide a reconfigurable communication transmitter and a reconfigurable communication method.
The technical scheme adopted by the invention is as follows:
a reconfigurable communication transmitter comprising:
the baseband generating circuit is used for generating a digital baseband signal and outputting different data control bits so as to realize switching of different modulation modes; wherein the modulation mode includes at least one of the following modes: QPSK,8PSK, N-APSK, N-QAM, N is more than or equal to 16;
the digital phase shifter is used for receiving an input signal and carrying out phase switching on the input signal according to the data control bit;
the quadrature signal generator is used for receiving the frequency signal output by the digital phase shifter and outputting IQ two paths of quadrature signals;
the digital power amplifier comprises a first amplifier and a second amplifier, and is used for respectively modulating and amplifying signals of an I path and a Q path according to data control bits; the signal modulation includes phase modulation and/or amplitude modulation;
and the output synthesis end is used for synthesizing the modulation signals output by the first amplifier and the second amplifier and outputting a synthesized signal.
Further, the digital phase shifter is an injection locking phase shifter;
the control of the resonant cavity LC network of the injection locking phase shifter is realized by changing the Bn end of the switch capacitor, and the self-oscillation frequency of the injection locking phase shifter is indirectly changed, so that the output phase response of the injection locking phase shifter is changed on the basis of the locking frequency.
Further, the digital power amplifier comprises a plurality of tail current tubes with different width-to-length ratios, and the output power of the digital power amplifier is controlled by changing the conduction condition of the different tail current tubes so as to realize the switching of the output amplitude.
Further, when the reconfigurable high-speed communication transmitter operates in the QPSK mode;
the phase of the digital phase shifter remains unchanged; the digital amplifier carries out phase modulation under the control of the data control bit to generate BPSK signals, outputs two paths of BPSK signals through the first amplifier and the second amplifier, synthesizes the two paths of BPSK signals and obtains QPSK modulation information.
Further, when the reconfigurable high-speed communication transmitter operates in the 8PSK mode;
the digital phase shifter is modulated by the data control bits to produce a switching of the 0 ° phase and the 45 ° phase;
when the modulation signal makes the digital phase shifter work at 0 degree, under the control of the data control bit, the digital amplifier respectively generates BPSK signals in two paths of IQ, and a signal with a constellation diagram of QPSK is obtained at the synthesis end;
when the digital phase shifter is switched to a 45 DEG state, the BPSK signal generated by the digital amplifier is phase-shifted by 45 DEG to obtain a QPSK signal rotated by 45 DEG;
and controlling the digital phase shifter to switch between two states to obtain 8PSK modulation information.
Further, the amplitude information on the digital amplifier is further controlled by the data control bit to obtain N-APSK modulation information.
Further, when the reconfigurable high-speed communication transmitter is operating in the N-QAM mode;
the phase of the digital phase shifter remains unchanged; the method comprises the steps of controlling amplitude information and phase information of a digital amplifier through a data control bit to generate an m-bit APSK signal, outputting two paths of m-bit APSK signals through a first amplifier and a second amplifier, and synthesizing the two paths of APSK signals to obtain N-QAM modulation information; wherein m is greater than or equal to 2, N=2 m 。
The invention adopts another technical scheme that:
a control method for controlling a reconfigurable communication transmitter as described above, comprising the steps of:
determining a modulation mode, and acquiring a first data control bit and a second data control bit according to the modulation mode;
controlling the digital phase shifter through the first data control bit so as to enable the digital phase shifter to switch different phases;
controlling the digital power amplifier by the second data control bit so that the digital power amplifier generates signals of different phases and/or different amplitudes;
and synthesizing the two paths of signals output by the first amplifier and the second amplifier to obtain a final modulation signal.
Further, the controlling the digital phase shifter by the first data control bit includes:
and changing Bn end of the switch capacitor according to the first data control bit, changing capacitance value of a capacitor in the LC network of the resonant cavity, changing self-oscillation frequency of the digital phase shifter, and finally changing output phase response of the digital phase shifter.
Further, the amplifier switching amplitude information is controlled by:
and controlling the working states of different tail current tubes according to the second data control bit to obtain different tail currents so as to realize switching with different amplitudes.
The beneficial effects of the invention are as follows: the invention adopts direct modulation to realize high-speed communication, reduces the requirement on a digital-to-analog converter, and solves the problem of high power consumption caused by the need of using a high-precision high-speed digital-to-analog converter in the existing high-speed communication transmitter.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made with reference to the accompanying drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and other drawings may be obtained according to these drawings without the need of inventive labor for those skilled in the art.
Fig. 1 is a 16QAM constellation according to an embodiment of the present invention;
fig. 2 is 8PSK and 16APSK constellations in an embodiment of the present invention;
FIG. 3 is a schematic diagram of a reconfigurable high-speed communication transmitter based on constellation rotation synthesis in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a conventional transmitter;
FIG. 5 is a schematic diagram of an injection locked phase shifter in accordance with an embodiment of the present invention;
FIG. 6 is a schematic diagram of a digital amplifier in an embodiment of the invention;
fig. 7 is a schematic diagram of a process of synthesizing 8PSK with 45 ° rotation of a QPSK constellation in an embodiment of the present invention;
fig. 8 is a schematic diagram of a process of two-way 16QAM synthesis using a 4APSK constellation IQ according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a process of obtaining 16APSK by 45 ° rotation synthesis and amplitude control of a QPSK constellation in an embodiment of the present invention;
fig. 10 is a schematic diagram of a process of two-way synthesis of 64QAM in an 8APSK constellation IQ according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a result of synthesizing 8PSK by 45 ° rotation of a QPSK constellation obtained by simulation design in the embodiment of the present invention;
fig. 12 is a schematic diagram of an IQ two-path 4APSK modulation synthesis 16QAM result obtained by simulation design in the embodiment of the present invention;
fig. 13 is a schematic diagram of a process of obtaining a 16APSK by 45 ° rotation synthesis and amplitude control of a QPSK constellation obtained by simulation design in the embodiment of the present invention;
fig. 14 is a schematic diagram of a process of performing IQ two-path synthesis on an 8APSK constellation diagram according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.
In the description of the present invention, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present invention can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
The existing high-speed communication transmitter has the problems that high power consumption is caused by using a high-precision high-speed DAC, and the linearity and efficiency requirements of high-order QAM modulation on a power amplifier are difficult to meet. Based on this, the present invention aims to solve the problem of high power consumption caused by the need of using a high-precision high-rate digital-to-analog converter in the existing high-speed communication transmitter, and to realize high-speed communication by adopting direct modulation, thereby reducing the requirement on the digital-to-analog converter. In addition, the invention aims to solve the problem that the linearity and efficiency of the power amplifier are difficult to realize when the traditional transmitter carries out high-order QAM modulation, and aims to realize high-order PSK and QAM modulation by adopting constellation diagram rotation synthesis, thereby realizing a millimeter wave direct modulation transmitter with high speed and high energy efficiency.
As shown in fig. 3, the present embodiment provides a reconfigurable high-speed communication transmitter based on constellation diagram rotation synthesis, which includes a baseband generating circuit, a digital phase shifter, a quadrature signal (IQ) generator, a digital power amplifier (digital PA), and an output synthesis end.
The core of the reconfigurable high-speed communication transmitter based on constellation diagram rotation synthesis is a digital phase shifter, a digital PA (i.e. a digital power amplifier) and a baseband generating circuit. The baseband generating circuit has two functions, on one hand, the generated digital baseband signal is used for directly modulating the signal, and on the other hand, the switching of modulation modes such as QPSK,8PSK,16 APSK, 16QAM, 64QAM and the like is realized by gating different data control bits.
(1) When working in QPSK mode, the digital phase shifter does not need to carry out phase switching control, the phase of the control is kept unchanged, and the digital phase shifter can be used as a Buffer. And the subsequent digital PA only carries out direct modulation on only one bit of information in the I path and the Q path respectively, the rest bits of information remain unchanged to generate BPSK signals, and finally, two paths of BPSK signals at the output end are synthesized to obtain QPSK modulation information.
It should be noted that the digital PA may be controlled by a plurality of bit data control bits, where a part of the data control bits control phases and another part of the data control bits control amplitudes, specifically how many bit control phases or amplitudes are adopted, may be selected according to a specific scheme, and are not limited herein, but the corresponding technical schemes shall fall within the protection scope of the present invention.
(2) When the digital phase shifter works in the 8PSK mode, the digital phase shifter is directly modulated by 1bit information bit to generate 0-degree and 45-degree phase switching, when the modulation signal enables the digital phase shifter to work in the 0-degree mode, BPSK signals generated by the back-end digital PA in two paths of IQ are respectively obtained at the synthesis end, a constellation diagram is QPSK signal, when the digital phase shifter is switched to the 45-degree state, the BPSK signal generated by the back-end digital PA is phase-shifted by 45 degrees, a QPSK signal rotating by 45 degrees can be seen at the synthesis end, when the phase shifter is switched in two states, finally 8PSK modulation information can be obtained at the output end, the specific process is shown in figure 7, amplitude information changes can be loaded at the digital PA end on the basis of the principle, the multiple modulation modes such as 16APSK are obtained through extension, and the generation of 16APSK is shown in figure 9.
It should be noted that the digital phase shifter may not only switch phases of 0 ° and 45 °, but also switch phases of other angles, and may be controlled by setting a plurality of information bits, for example, by controlling switching of 4 phases by 2bit information bits, and the specific need to set a plurality of information bits is determined by specific implementation, which is not limited herein.
(3) When the digital phase shifter works in the 16QAM mode, the digital phase shifter is closed and works as a Buffer, the digital PA at the rear end generates 2bit APSK signals respectively in two paths of IQ, and finally the 16QAM signals are synthesized at the output end, the final synthesis effect is shown in figure 8, the scheme reduces the linearity requirement on the PA compared with the scheme that the up-conversion is firstly carried out and then the amplification is carried out, the digital PA only needs to pay attention to 2 state amplitude changes when in the 16QAM mode, and the digital PA only needs to respond to 3 state amplitude changes when in the traditional transmitter architecture.
(4) The digital phase shifter is turned off when operating in 64QAM mode, which operates as only one Buffer, and the digital PA at the back end generates 3bit APSK signals at the IQ two paths, respectively, and finally synthesizes the 64QAM signals at the output end, the final synthesis effect is shown in FIG. 10, the scheme reduces the linearity requirement for the PA compared with the scheme that needs to perform up-conversion first and then amplification, the digital PA only needs to deal with the amplitude change of 4 states when in 64QAM, and the digital PA needs to respond to the amplitude change of 10 states for the traditional transmitter architecture.
The present invention is more advantageous for higher order modulation communication designs than conventional communication transmitters. Referring to fig. 4, fig. 4 is a circuit schematic diagram of a conventional communication transmitter, an input signal is directly input into a quadrature signal generator, the quadrature signal generator outputs IQ two paths of signals, the two paths of signals are mixed with a digital baseband signal respectively, then synthesized, amplified by an amplifier, and output to a transmitting end.
As an alternative embodiment, the digital phase shifter is a broadband, low phase error, low amplitude error, high speed phase shifter, which responds to high speed digital switching while avoiding its EVM degradation effect on the overall transmitter, the specific configuration of the digital phase shifter used in this example is shown in fig. 5 below.
As an alternative embodiment, the digital PA is a high-efficiency, low-amplitude error digital power amplifier, so as to meet the amplitude variation required during different state switching, and reduce the influence of the amplitude error on the EVM of the transmitter, and the specific structure used in this example is shown in fig. 6 below.
The reconfigurable high-speed communication transmitter is described in detail below with reference to specific embodiments, and simulation verification is performed using a CMOS process.
Referring to fig. 3, the present embodiment provides a reconfigurable high-speed communication transmitter based on constellation rotation synthesis, including:
digital phase shifter (Digital Phase Shifter): acting as a phase switch and amplifying the input LO.
Number PA (Digital PA): acting to amplify the input signal and modulate the digital signal.
Digital Baseband circuit (Baseband Data): random high-speed symbol information is generated and the modulation state is switched.
IQ generation circuit (IQ Generator): generating quadrature signals.
Output synthesis end (IQ Combiner): the modulated signals are synthesized and output to the antenna end.
The key of implementing phase control and implementing amplitude control is a digital phase shifter and a digital PA, where the digital phase shifter is based on an injection locking phase shifter to implement a phase shifting function, and the working principle is that the oscillator core is locked by an injection signal, so that the frequency change of the oscillator core cannot be suddenly changed, and therefore, the self-oscillation frequency of the oscillator core is indirectly changed by changing the Bn end of a switch capacitor to control the LC network of a resonant cavity, so that the output phase response of the injection locking phase shifter is changed on the basis of the locking frequency, and a constant amplitude effect is implemented when the output phase is changed for a Buffer at the rear end.
As An alternative embodiment, the digital PA is as shown in fig. 6 by controlling tail current pipes An and
the terminal indirectly controls the output power of the amplifier, so as to realize the switching of the output amplitude and achieve the multi-bit APSK control effect required by the design of the invention. Referring to FIG. 6, when the An end is turned on, the tail current tube array at the left end operates when +.>
The tail current tube array at the right end works by switching An and +.>
And the end realizes 0/180 phase control.
The connection relation of each part is as follows:
taking the generation of 8PSK as an example, an externally input LO signal is connected to the input end of a digital phase shifter, the other end of the digital phase shifter is connected with a digital baseband circuit, the state switching controlled by the digital baseband circuit enables the digital phase shifter to work in an 8PSK modulation mode and provides 1bit of high-speed random digital information, so that the digital phase shifter generates 0/45 phase switching required by constellation diagram rotation, and the output end of the digital phase shifter is connected to an IQ generating circuit, so that the rear end respectively forms IQ two paths; the output ends of the IQ two paths are respectively connected with the input ends of the two paths of digital PAs, the other ends of the two paths of digital PAs are respectively connected with the digital baseband circuit to ensure that the digital PAs are switched in multiple modulation modes and each path of digital PAs are directly modulated with 1bit digital information, and the output ends of the IQ two paths of digital PAs are finally synthesized with a constellation diagram at an output synthesis end and are connected to an output load end to obtain the required 8PSK modulation information.
Taking the generation of 16APSK as an example, an externally input LO signal is connected to the input end of a digital phase shifter, the other end of the digital phase shifter is connected with a digital baseband circuit, the state switching controlled by the digital baseband circuit enables the digital phase shifter to work in a 16APSK modulation mode and provides 1bit of high-speed random digital information, so that the digital phase shifter generates 0/45 phase switching required by constellation diagram rotation, and the output end of the digital phase shifter is connected to an IQ generating circuit, so that the rear end respectively forms IQ two paths; the output ends of the two paths of IQ are respectively connected with the input ends of the two paths of digital PAs, the other ends of the two paths of digital PAs are respectively connected with the digital baseband circuit to ensure that the digital PAs work in a 16APSK modulation mode, under the modulation mode, the digital PAs of the two paths of IQ are respectively controlled by 2bit digital information, one bit enables the digital PAs to be synthesized to generate QPSK, the other bit information bit enables the QPSK to carry out amplitude variation, and the output ends of the digital PAs of the two paths of IQ finally carry out constellation diagram synthesis at an output synthesis end and are connected to an output load end to obtain the required 16APSK modulation information.
Taking the generation of 16QAM as an example, an externally input LO signal is connected to the input end of a digital phase shifter, the other end of the digital phase shifter is connected with a digital baseband circuit, the state switching controlled by the digital baseband circuit enables the digital phase shifter to work as an LO amplifier and cannot perform phase switching, and the output end of the digital phase shifter is connected to an IQ generating circuit so that the rear end forms IQ two paths respectively; the output ends of the two paths of IQ are respectively connected with the input ends of the two paths of digital PAs, the other ends of the two paths of digital PAs are respectively connected with the digital baseband circuit to ensure that the digital PAs work in a 16QAM mode and each path of digital PAs directly modulate 2bit digital information, and the output ends of the two paths of digital PAs of IQ finally perform constellation diagram synthesis at an output synthesis end and are connected to an output load end to obtain the required 16QAM modulation information.
Taking the generation of 64QAM as an example, an externally input LO signal is connected to the input end of a digital phase shifter, the other end of the digital phase shifter is connected with a digital baseband circuit, the state switching controlled by the digital baseband circuit enables the digital phase shifter to work as an LO amplifier and cannot perform phase switching, and the output end of the digital phase shifter is connected to an IQ generating circuit so that the rear end forms IQ two paths respectively; the output ends of the two paths of IQ are respectively connected with the input ends of the two paths of digital PAs, the other ends of the two paths of digital PAs are respectively connected with the digital baseband circuit to ensure that the digital PAs work in a 64QAM mode and each path of digital PAs directly modulate 3bit digital information, and the output ends of the two paths of digital PAs of IQ finally perform constellation diagram synthesis at an output synthesis end and are connected to an output load end to obtain the required 64QAM modulation information. Each symbol synthesized by the QAM constellation can be expressed as shown in the following equation (1)
S k (t)＝A k cos(ω 0 t+θ k ) (1)
Expanding the formula:
S k (t)＝A k cos(θ k )cos(ω 0 t)-A k sin(θ k )sin(ω 0 t) (2)
let X k ＝A k cos(θ k )，Y k ＝-A k sin(θ k ) The signal becomes:
S k (t)＝X k cos(ω 0 t)+Y k sin(ω 0 t) (3)
wherein X is k And Y k Is a variable of a discrete value determined by the amplitude and phase. Each symbol can be regarded as the sum of two carrier-quadrature N-bit amplitude phase shift keying signals to obtain a 16QAM signal, for the generation of the rotating constellation synthesis 8PSK of the present example can be regarded as the sum of two carrier-quadrature N-bit amplitude phase shift keying signals plus phase rotation, and for the generation of the rotating constellation synthesis 16APSK of the present example can be regarded as the sum of two carrier-quadrature N-bit amplitude phase shift keying signals plus phase rotation and output amplitude control, the corresponding constellations of which are shown in fig. 1 and 2.
Referring to fig. 11-14, fig. 11 is a schematic diagram of a QPSK constellation rotated 45 ° to synthesize 8PSK result obtained by a simulation design; fig. 12 is a schematic diagram of an IQ two-path 4APSK modulation synthesis 16QAM result obtained by simulation design, fig. 13 is a schematic diagram of a process of obtaining 16APSK by 45 ° rotation synthesis and amplitude control of a QPSK constellation obtained by simulation design, and fig. 14 is a schematic diagram of a process of obtaining 64QAM by IQ two-path synthesis of an 8APSK constellation obtained by simulation design.
In summary, compared with the prior art, the embodiment has the following advantages and beneficial effects:
(1) The invention can work under the condition of high code element rate
The digital phase shifter and the digital PA can realize rapid phase and amplitude switching, and the digital phase shifter has small phase error and amplitude error, and effectively avoids EVM deterioration caused by high-speed modulation. When simulation is performed, a 30Gbps rate can be obtained, and a faster speed can be obtained compared with the existing millimeter wave communication structure. Referring to fig. 12 and 14, the data of 16QAM in fig. 12 can reach 32Gbps, and 64QAM in fig. 14 can also reach 30Gbps.
(2) The invention has lower requirements on linearity and rollback efficiency of the power amplifier
The digital PA of the invention directly synthesizes information at the synthesizing end after respectively amplifying signals in IQ two paths, thereby avoiding the harsh requirement on circuit linearity when the traditional transmitter carries out high-order QAM modulation, and simultaneously avoiding the situation that the traditional 8PSK transmitter needs to obtain through amplitude control and digital circuit point selection, while the 8PSK modulation of the design can realize the function through constant amplitude plus constellation diagram rotation.
(3) The modulation mode of the invention can realize the switching of a plurality of modulation modes through the simple switch selection
The invention can switch the control bit of the digital baseband according to the actual situation, so as to meet the switching of various states such as QPSK,8PSK,16QAM, and compared with the high-precision DAC required by the traditional transmitter, the direct modulation mode reduces the system power consumption and realizes various modulation modes with a simpler structure.
For the reconfigurable high-speed communication transmitter based on constellation diagram rotation synthesis, the embodiment further provides a control method, which comprises the following steps:
a control method for controlling a reconfigurable communication transmitter as described above, comprising the steps of:
s1, determining a modulation mode, and acquiring a first data control bit and a second data control bit according to the modulation mode;
s2, controlling the digital phase shifter through the first data control bit so that the digital phase shifter switches different phases;
s3, controlling the digital power amplifier through a second data control bit so that the digital power amplifier generates signals with different phases and/or different amplitudes;
s4, combining the two paths of signals output by the first amplifier and the second amplifier to obtain a final modulation signal.
Further as an alternative embodiment, the controlling the digital phase shifter by the first data control bit includes:
and changing Bn end of the switch capacitor according to the first data control bit, changing capacitance value of a capacitor in the LC network of the resonant cavity, changing self-oscillation frequency of the digital phase shifter, and finally changing output phase response of the digital phase shifter.
Further as an alternative embodiment, the amplifier switching amplitude information is controlled by:
and controlling the working states of different tail current tubes according to the second data control bit to obtain different tail currents so as to realize switching with different amplitudes.
The control method of the embodiment has a one-to-one correspondence with the reconfigurable high-speed communication transmitter, so that the control method has corresponding functions and beneficial effects.
In the foregoing description of the present specification, reference has been made to the terms "one embodiment/example", "another embodiment/example", "certain embodiments/examples", and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present invention, and these equivalent modifications and substitutions are intended to be included in the scope of the present invention as defined in the appended claims.
Claims (15)
1. A reconfigurable communication transmitter, comprising:
the baseband generating circuit is used for generating a digital baseband signal and outputting different data control bits so as to realize switching of different modulation modes; wherein the modulation mode includes at least one of the following modes: QPSK,8PSK, N-APSK, N-QAM, N is more than or equal to 16;
the digital phase shifter is used for receiving an input signal and carrying out phase switching on the input signal according to the data control bit; the quadrature signal generator is used for receiving the frequency signal output by the digital phase shifter and outputting IQ two paths of quadrature signals;
the digital power amplifier comprises a first amplifier and a second amplifier, and is used for respectively modulating and amplifying signals of an I path and a Q path according to data control bits; the signal modulation includes phase modulation and/or amplitude modulation;
the output synthesis end is used for synthesizing the modulation signals output by the first amplifier and the second amplifier and outputting a synthesized signal;
when the reconfigurable high-speed communication transmitter operates in QPSK mode:
the phase of the digital phase shifter remains unchanged; the digital amplifier carries out phase modulation under the control of the data control bit to generate BPSK signals, outputs two paths of BPSK signals through the first amplifier and the second amplifier, synthesizes the two paths of BPSK signals and obtains QPSK modulation information.
2. A reconfigurable communication transmitter as claimed in claim 1, wherein said digital phase shifter is an injection locked phase shifter;
the control end of the switch capacitor is changed to control the resonant cavity LC network of the injection locking phase shifter, so that the self-oscillation frequency of the injection locking phase shifter is indirectly changed, and the output phase response of the injection locking phase shifter is changed on the basis of the locking frequency.
3. The reconfigurable communication transmitter of claim 1, wherein the digital power amplifier includes a plurality of tail current tubes with different width to length ratios, and the switching of the output amplitude is achieved by changing the conduction condition of the different tail current tubes to control the output power of the digital amplifier.
4. A reconfigurable communication transmitter, comprising:
the baseband generating circuit is used for generating a digital baseband signal and outputting different data control bits so as to realize switching of different modulation modes; wherein the modulation mode includes at least one of the following modes: QPSK,8PSK, N-APSK, N-QAM, N is more than or equal to 16;
the digital phase shifter is used for receiving an input signal and carrying out phase switching on the input signal according to the data control bit; the quadrature signal generator is used for receiving the frequency signal output by the digital phase shifter and outputting IQ two paths of quadrature signals;
the digital power amplifier comprises a first amplifier and a second amplifier, and is used for respectively modulating and amplifying signals of an I path and a Q path according to data control bits; the signal modulation includes phase modulation and/or amplitude modulation;
the output synthesis end is used for synthesizing the modulation signals output by the first amplifier and the second amplifier and outputting a synthesized signal;
when the reconfigurable high-speed communication transmitter operates in the 8PSK mode:
the digital phase shifter is modulated by the data control bit to generate a switching of the first phase and the second phase;
when the digital phase shifter works in a first phase state by modulating signals, under the control of a data control bit, the digital amplifier respectively generates BPSK signals in two paths of IQ, and a signal with a constellation diagram of QPSK is obtained at a synthesis end;
when the digital phase shifter is switched to a second phase state, the BPSK signal generated by the digital amplifier is shifted by n degrees to obtain a QPSK signal rotated by n degrees; wherein n DEG is the difference between the first phase and the second phase;
and controlling the digital phase shifter to switch between two states to obtain 8PSK modulation information.
5. The reconfigurable communication transmitter of claim 4, wherein the digital phase shifter is an injection locked phase shifter;
the control end of the switch capacitor is changed to control the resonant cavity LC network of the injection locking phase shifter, so that the self-oscillation frequency of the injection locking phase shifter is indirectly changed, and the output phase response of the injection locking phase shifter is changed on the basis of the locking frequency.
6. The reconfigurable communication transmitter of claim 4, wherein the digital power amplifier includes a plurality of tail current tubes with different width to length ratios, and the switching of the output amplitude is achieved by changing the conduction condition of the different tail current tubes to control the output power of the digital amplifier.
7. A reconfigurable communication transmitter, comprising:
the baseband generating circuit is used for generating a digital baseband signal and outputting different data control bits so as to realize switching of different modulation modes; wherein the modulation mode includes at least one of the following modes: QPSK,8PSK, N-APSK, N-QAM, N is more than or equal to 16;
the digital phase shifter is used for receiving an input signal and carrying out phase switching on the input signal according to the data control bit; the quadrature signal generator is used for receiving the frequency signal output by the digital phase shifter and outputting IQ two paths of quadrature signals;
the digital power amplifier comprises a first amplifier and a second amplifier, and is used for respectively modulating and amplifying signals of an I path and a Q path according to data control bits; the signal modulation includes phase modulation and/or amplitude modulation;
the output synthesis end is used for synthesizing the modulation signals output by the first amplifier and the second amplifier and outputting a synthesized signal;
when the reconfigurable high-speed communication transmitter operates in the N-APSK mode:
the digital phase shifter is modulated by the data control bit to generate a switching of the first phase and the second phase;
when the digital phase shifter works in a first phase state by modulating signals, under the control of a data control bit, the digital amplifier respectively generates BPSK signals in two paths of IQ, and a signal with a constellation diagram of QPSK is obtained at a synthesis end;
when the digital phase shifter is switched to a second phase state, the BPSK signal generated by the digital amplifier is shifted by n degrees to obtain a QPSK signal rotated by n degrees; wherein n DEG is the difference between the first phase and the second phase;
the digital phase shifter is controlled to switch between two states to obtain 8PSK modulation information, and the amplitude information on the digital amplifier is further controlled through the data control bit to obtain N-APSK modulation information.
8. The reconfigurable communication transmitter of claim 7, wherein the digital phase shifter is an injection locked phase shifter;
the control end of the switch capacitor is changed to control the resonant cavity LC network of the injection locking phase shifter, so that the self-oscillation frequency of the injection locking phase shifter is indirectly changed, and the output phase response of the injection locking phase shifter is changed on the basis of the locking frequency.
9. The reconfigurable communication transmitter of claim 7, wherein the digital power amplifier includes a plurality of tail current tubes with different width to length ratios, and the switching of the output amplitude is achieved by changing the conduction condition of the different tail current tubes to control the output power of the digital amplifier.
10. A reconfigurable communication transmitter, comprising:
the baseband generating circuit is used for generating a digital baseband signal and outputting different data control bits so as to realize switching of different modulation modes; wherein the modulation mode includes at least one of the following modes: QPSK,8PSK, N-APSK, N-QAM, N is more than or equal to 16;
the digital phase shifter is used for receiving an input signal and carrying out phase switching on the input signal according to the data control bit; the quadrature signal generator is used for receiving the frequency signal output by the digital phase shifter and outputting IQ two paths of quadrature signals;
the digital power amplifier comprises a first amplifier and a second amplifier, and is used for respectively modulating and amplifying signals of an I path and a Q path according to data control bits; the signal modulation includes phase modulation and/or amplitude modulation;
the output synthesis end is used for synthesizing the modulation signals output by the first amplifier and the second amplifier and outputting a synthesized signal;
when the reconfigurable high-speed communication transmitter is operating in the N-QAM mode:
the phase of the digital phase shifter remains unchanged; the method comprises the steps of controlling amplitude information and phase information of a digital amplifier through a data control bit to generate an m-bit APSK signal, outputting two paths of m-bit APSK signals through a first amplifier and a second amplifier, and synthesizing the two paths of APSK signals to obtain N-QAM modulation information; wherein m is more than or equal to 2.
11. A reconfigurable communication transmitter according to claim 10, wherein the digital phase shifter is an injection locked phase shifter;
the control end of the switch capacitor is changed to control the resonant cavity LC network of the injection locking phase shifter, so that the self-oscillation frequency of the injection locking phase shifter is indirectly changed, and the output phase response of the injection locking phase shifter is changed on the basis of the locking frequency.
12. The reconfigurable communication transmitter of claim 10, wherein the digital power amplifier includes a plurality of tail current tubes with different width to length ratios, and the switching of the output amplitude is achieved by changing the conduction condition of the different tail current tubes to control the output power of the digital amplifier.
13. A control method for controlling a reconfigurable communication transmitter as claimed in any one of claims 1 to 12, comprising the steps of:
determining a modulation mode, and acquiring a first data control bit and a second data control bit according to the modulation mode;
controlling the digital phase shifter through the first data control bit so as to enable the digital phase shifter to switch different phases;
controlling the digital power amplifier by the second data control bit so that the digital power amplifier generates signals of different phases and/or different amplitudes;
and synthesizing the two paths of signals output by the first amplifier and the second amplifier to obtain a final modulation signal.
14. A control method according to claim 13, wherein said controlling the digital phase shifter by the first data control bit comprises:
and changing a control end of the switch capacitor according to the first data control bit, changing a capacitance value of a capacitor in the LC network of the resonant cavity, changing the self-oscillation frequency of the digital phase shifter, and finally changing the output phase response of the digital phase shifter.
15. A control method according to claim 13, characterized in that the amplifier switching amplitude information is controlled by:
and controlling the working states of different tail current tubes according to the second data control bit to obtain different tail currents so as to realize switching with different amplitudes.
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