CN115733476A

CN115733476A - High-side MOSFET switch chip with short-circuit protection and short-circuit protection control method thereof

Info

Publication number: CN115733476A
Application number: CN202211380004.8A
Authority: CN
Inventors: 熊平; 杨世红; 余远强; 付玉建
Original assignee: Shaanxi Reactor Microelectronics Co ltd
Current assignee: Shaanxi Reactor Microelectronics Co ltd
Priority date: 2022-11-04
Filing date: 2022-11-04
Publication date: 2023-03-03

Abstract

The invention provides a high-side MOSFET switch chip with short-circuit protection and a short-circuit protection control method thereof, aiming at solving the technical problem that a power MOS tube is easily burnt out when the output of the conventional high-side MOSFET switch chip is short-circuited. The high-side MOSFET switch chip comprises a charge pump, an oscillator, a logic control unit, a linear voltage stabilizer, a power MOS tube and a short-circuit protection unit; the short-circuit protection unit is respectively connected with a VBB pin, a high-side power supply voltage Vs, an OUT pin and a power MOS (metal oxide semiconductor) transistor GATE (GATE on transistor) driving end and comprises a first-stage Von detection circuit, a second-stage Von detection and clamping current-limiting circuit, a delay time generation circuit and an enable signal generation circuit; when certain threshold voltage and delay requirements are met, the short-circuit protection unit pulls down the voltage of the GATE driving end to turn off the power MOS tube and lock the short-circuit protection state, or the voltage drop of the GATE driving end and the VOUT pin is clamped to the clamping voltage.

Description

High-side MOSFET switch chip with short-circuit protection and short-circuit protection control method thereof

Technical Field

The invention relates to a high-side MOSFET switch chip, in particular to a high-side MOSFET switch chip with short-circuit protection.

Background

The high-side MOSFET switch chip is an electronic device for automobiles, is used for replacing a relay or a fuse, is generally placed on the high side of a certain branch of an automobile power supply, and can realize self detection while providing a switch power supply.

Fig. 1 is a system architecture and pin diagram of a conventional high-side MOSFET switch chip. If the output of the chip is short-circuited, large current can flow in the power MOS tube, and even the power MOS tube is burnt. If the existing short-circuit protection unit is directly added to the chip, the short-circuit protection unit must be added with a delay circuit, so that the power MOS tube is turned off when the conduction voltage Von is detected to be larger than a set value after a period of time delay, otherwise, the output voltage Vout of a VOUT pin suddenly changes when the short-circuit protection unit without the delay circuit is connected with an inductive load, so that the short-circuit protection is triggered mistakenly, and further, the system is restarted. Therefore, the conventional short-circuit protection unit is not suitable for being applied to a high-side MOSFET switch chip.

Disclosure of Invention

The invention aims to provide a high-side MOSFET switch chip with short-circuit protection and a short-circuit protection control method thereof, which solve the technical problem that a power MOS tube is easily burnt out when the output of the conventional high-side MOSFET switch chip is short-circuited.

In order to achieve the purpose, the technical solution of the invention is as follows:

a short-circuit protection control method of a high-side MOSFET switch chip is characterized in that:

after starting up, the input voltage of an IN pin is sent to a high-side MOSFET switch chip, high-side power supply voltage Vs is output through a linear voltage stabilizer, and meanwhile, a short-circuit protection unit carries out first-stage Von detection and second-stage Von detection;

the first-stage Von detection means that if the on-state voltage Von is larger than a first short-circuit threshold voltage Vth1 and the holding time exceeds a first delay time Tdelay1, after reaching a second delay time Tdelay2, a chip internal driving signal inL is generated as a short-circuit protection signal, and the voltage of a GATE driving end is pulled down, so that a power MOS (metal oxide semiconductor) tube is turned off and a short-circuit protection state is locked; if the on-voltage Von is greater than the first short-circuit threshold voltage Vth1 and the holding time does not exceed the first delay time Tdelay1, clamping the voltage drop of the GATE driving end and the OUT pin to the clamping voltage;

the second-stage Von detection means that if the on-state voltage Von is larger than a third short-circuit threshold voltage Vth3 and smaller than a first short-circuit threshold voltage Vth1, or the on-state voltage Von is larger than a second short-circuit threshold voltage Vth2 and smaller than a third short-circuit threshold voltage Vth3 and the holding time exceeds a second delay time Tdelay2, the voltage drop of the GATE driving end and the VOUT pin is clamped to a clamping voltage;

the first short-circuit threshold voltage Vth1 is more than a third short-circuit threshold voltage Vth3 is more than a second short-circuit threshold voltage Vth2;

the second delay time Tdelay2 > the first delay time Tdelay1.

Further, the first-stage Von detection specifically includes that in a current mirror circuit, a reference current generated by adding a voltage drop of a second voltage-regulator tube to a reference resistor R1 is compared with a detection current generated by adding a conducting voltage Von to a detection resistor R2, so as to judge whether the conducting voltage Von reaches a first short-circuit threshold voltage Vth1, if the conducting voltage Von is always greater than the first short-circuit threshold voltage Vth1 within a first delay time Tdelay1, after the second delay time Tdelay2 is over, an internal chip driving signal inL is output as a short-circuit protection signal pull-down GATE driving end voltage, so as to turn off a power MOS tube and lock a short-circuit protection state; if the on-voltage Von is greater than the first short-circuit threshold voltage Vth1 and the holding time does not exceed the first delay time Tdelay1, clamping the voltage drop of the GATE driving end and the OUT pin to the clamping voltage; the breakover voltage Von is the difference value of an input voltage Vbb of a VBB pin and an output voltage Vout of a VOUT pin, and the voltage drop of the first short-circuit threshold voltage Vth1 and the voltage drop of the second voltage-stabilizing tube is in a linear relation;

the second stage Von detection is to clamp the voltage drop of the GATE driving end and the VOUT pin to the clamping voltage if the on-state voltage Von is greater than the third short-circuit threshold voltage Vth3 and smaller than the first short-circuit threshold voltage Vth1, or the on-state voltage Von is greater than the second short-circuit threshold voltage Vth2 and smaller than the third short-circuit threshold voltage Vth3 and the holding time exceeds the second delay time Tdelay2; the third short-circuit threshold voltage Vth3 is equal to the clamping voltage of three field effect transistors, and the second short-circuit threshold voltage Vth2 is equal to the clamping voltage of one field effect transistor; and shielding and outputting the short-circuit protection signal within the delayed second delay time Tdelay2 of the second-stage Von detection.

Further, the high-side power supply voltage Vs = Vbb-Vdz1+ Vgs _ p1 of the linear regulator, where Vdz1 is the voltage drop of the first regulator, and Vgs _ p1 is the clamping voltage of the first PMOS transistor;

the clamping voltage is (R) ₃ +R ₄ )/R ₃ X Vgs _ p17, where R ₃ Is the resistance value of the third resistor R3, R ₄ The Vgs _ P17 is the resistance value of the fourth resistor, and is the clamping voltage of a seventeenth PMOS tube P17;

after the power is started for a period of time and EN enables output, the short-circuit protection unit carries out first-stage Von detection and second-stage Von detection.

The invention also provides a high-side MOSFET switch chip with short-circuit protection, which IS used for realizing the method and comprises a VBB pin, an IN pin, an IS pin, an OUT pin, a charge pump, an oscillator, a logic control unit, a linear voltage stabilizer and a power MOS tube; the linear voltage regulator is used for generating a high-side power supply voltage Vs according to an input voltage of an IN pin;

it is characterized in that: the short-circuit protection device also comprises a short-circuit protection unit; the short-circuit protection unit is respectively connected with a VBB pin, a high-side power supply voltage Vs, an OUT pin and a power MOS (metal oxide semiconductor) transistor GATE driving end;

the short-circuit protection unit comprises a first-stage Von detection circuit, a second-stage Von detection and clamping current limiting circuit, a delay time generation circuit and an enable signal generation circuit;

the first-stage Von detection circuit is used for comparing a current Ionsc generated by the breakover voltage Von with a reference current Idz generated by an IN pin and outputting a detection signal Vonsc, wherein the detection signal Vonsc is used for judging whether the breakover voltage Von reaches a first short-circuit threshold voltage Vth1;

the enable signal generating circuit is used for delaying for a period of time and then outputting an enable signal EN;

the delay time generating circuit is used for generating a first delay time Tdelay1 and a second delay time Tdelay2 according to an enable signal EN, and outputting a chip internal driving signal inL;

the second-stage Von detection and clamping current-limiting circuit is used for judging whether the conduction voltage Von is greater than a third short-circuit threshold voltage Vth3 or greater than a second short-circuit threshold voltage Vth2 after delaying for a second delay time Tdelay2, and clamping the voltage drop of the GATE driving end and the OUT pin to a clamping voltage;

the second delay time Tdelay2 > the first delay time Tdelay1.

Further, the first-stage Von detection circuit comprises a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a second voltage regulator transistor Dz2, a reference resistor R1, a detection resistor R2, a second field effect transistor N2, a third field effect transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5;

the source electrodes of a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7 and an eighth PMOS tube P8 are all connected with a VBB pin; the grid and the drain of the fourth PMOS tube P4 are both connected with the cathode of the second voltage-regulator tube Dz2, the anode of the second voltage-regulator tube Dz2 is connected with the source of the second PMOS tube P2, the drain and the grid of the second PMOS tube P2 are both connected with the drain of the second field-effect tube N2, and the grid and the source of the second field-effect tube N2 are both connected with an IN pin; the grid electrode and the drain electrode of the fifth PMOS tube P5 are both connected with one end of the reference resistor R1, the other end of the reference resistor R1 is connected with the source electrode of the third PMOS tube P3, the grid electrode of the third PMOS tube P3 is connected with the grid electrode of the second PMOS tube P2, and the drain electrode of the third PMOS tube P3 is connected with the IN pin; the grid electrode of the sixth PMOS tube P6 is connected with the grid electrode of the fifth PMOS tube P5, and the drain electrode of the sixth PMOS tube P6 is connected with the drain electrode of the fifth NMOS tube N5; the drain electrode of the eighth PMOS tube P8 is connected with the drain electrode and the grid electrode of the fourth NMOS tube N4, and the source electrode of the fourth NMOS tube N4 and the source electrode of the fifth NMOS tube N5 are both connected with a high-side power supply voltage Vs; the grid electrode of the eighth PMOS tube P8 is connected with the grid electrode of the seventh PMOS tube P7; the grid and the drain of the seventh PMOS tube P7 are both connected with one end of the detection resistor R2, the other end of the detection resistor R2 is connected with the drain of the third field-effect tube N3, and the grid and the source of the third field-effect tube N3 are both connected with the OUT pin; the drain electrode of the sixth PMOS transistor P6 is used for drawing the detection signal Vonsc output by the first-stage Von detection circuit.

Further, the delay time generation circuit includes a first current source I1, a first not gate inv1, a ninth PMOS transistor P9, a sixth NMOS transistor N6, a second capacitor C2, a seventh NMOS transistor N7, a second not gate inv2, a third not gate inv3, a second current source I2, a fourth not gate inv4, a tenth PMOS transistor P10, an eighth NMOS transistor N8, a third capacitor C3, a fifth not gate inv5, a sixth not gate inv6, a first nand gate nand1, a second nand gate nand2, and a seventh not gate inv7;

one end of the first current source I1 is connected with a VBB pin, and the other end of the first current source I1 is connected with a source electrode of a ninth PMOS tube P9; the input end of the first NOT gate inv1 is connected with the detection signal Vonsc output by the first-stage Von detection circuit, and the output end of the first NOT gate inv1 is connected with the grid electrode of the ninth PMOS tube P9 and the grid electrode of the sixth NMOS tube N6; the drain electrode of the ninth PMOS transistor P9 and the drain electrode of the sixth NMOS transistor N6 are all connected to one end of the second capacitor C2, the drain electrode of the seventh NMOS transistor N7 and the input end of the second not gate inv 2; the output end of the second not gate inv2 is connected with the input end of the third not gate inv3, and the output end of the third not gate inv3 is connected with one input end of the first nand gate nand 1; the source electrode of the sixth NMOS transistor N6, the source electrode of the seventh NMOS transistor N7 and the other end of the second capacitor C2 are all connected with a high-side power supply voltage Vs;

one end of the second current source I2 is connected with a VBB pin, and the other end of the second current source I2 is connected with the source electrode of a tenth PMOS tube P10; the input end of the fourth not gate inv4 is connected with the enable signal EN, and the output end of the fourth not gate inv4 is connected with the grid electrode of the tenth PMOS tube P10 and the grid electrode of the eighth NMOS tube N8; the drain of the tenth PMOS transistor P10 and the drain of the eighth NMOS transistor N8 are both connected to one end of the third capacitor C3 and the input end of the fifth not gate inv 5; the output end of the fifth not gate inv5 is connected with the input end of the sixth not gate inv6, and the output end of the sixth not gate inv6 is connected with the other input end of the first nand gate nand 1; the source electrode of the eighth NMOS tube N8 and the other end of the third capacitor C3 are both connected with a high-side power supply voltage Vs;

the output signal of the first NAND GATE nand1 and the enable signal EN are respectively sent to two input ends of a second NAND GATE nand2, and the output end of the second NAND GATE nand2 is connected with the GATE driving end of the chip through a seventh NOT GATE inv7; the grid electrode of the seventh NMOS tube N7 is connected with the output end of the fourth NOT gate inv 4; an output terminal of the third not gate inv3 is configured to output the first delay time signal Tdelay1; an output terminal of the fifth not gate inv5 is configured to output the second delay time signal Tdelay2; the output end of the second nand gate nand2 is also connected with the input end of the second-stage Von detection and clamping current-limiting circuit.

Further, the second-stage Von detection and clamping current-limiting circuit includes a third current source I3, a current mirror composed of an eleventh PMOS transistor P11 and a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, a ninth field-effect transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a third resistor R3, a fourth resistor R4, and a fifth resistor R5;

the input end of the third current source I3 is connected with a high-side power supply voltage Vs, and the output end of the third current source I is connected with the drain electrode and the grid electrode of the eleventh PMOS tube P11 and the grid electrode of the twelfth PMOS tube P12; the source electrode of the eleventh PMOS pipe P11 and the source electrode of the twelfth PMOS pipe P12 are both connected with the VBB pin; the drain of the twelfth PMOS tube P12 is connected with the source of the thirteenth PMOS tube P13 and the source of the fifteenth PMOS tube P15; the grid electrode and the drain electrode of the thirteenth PMOS tube P13 are both connected with the source electrode of the fourteenth PMOS tube P14, and the grid electrode and the drain electrode of the fourteenth PMOS tube P14 and the drain electrode of the fifteenth PMOS tube P15 are both connected with the source electrode of the sixteenth PMOS tube P16; the drain electrode of a sixteenth PMOS tube P16 is connected with the drain electrode and the grid electrode of a ninth NMOS tube N9, the grid electrode of a tenth NMOS tube N10 and the grid electrode of an eleventh NMOS tube N11; the drain electrode of the tenth NMOS tube N10 is connected with the grid electrode of the power MOS tube, the source electrode of the seventeenth PMOS tube P17 and the drain electrode of the twelfth NMOS tube N12 sequentially through the fourth resistor R4 and the third resistor R3; the grid electrode of a seventeenth PMOS tube P17 is connected with the connection point of the fourth resistor R4 and the third resistor R3, and the drain electrode of the seventeenth PMOS tube P17 is connected with the drain electrode of the eleventh NMOS tube N11, one end of the fifth resistor R5 and the grid electrode of the twelfth NMOS tube N12; the source electrode of the ninth NMOS transistor N9, the source electrode of the tenth NMOS transistor N10, the source electrode of the eleventh NMOS transistor N11, the other end of the fifth resistor and the source electrode of the twelfth NMOS transistor N12 are all connected with an OUT pin; the gate of the fifteenth PMOS transistor P15 is configured to receive the second delay time signal Tdelay2.

Furthermore, the enabling signal generating circuit comprises an enabling starting unit, a first-stage hysteresis unit, a shaping and second-stage hysteresis unit and a delay unit; the enabling and starting unit comprises a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, an eighteenth PMOS tube P18 and a ninth resistor R9; the first-stage hysteresis unit comprises a seventeenth NMOS tube N17; the shaping and second-stage hysteresis unit comprises a nineteenth PMOS tube P19, a thirteenth field effect tube N13, a fourteenth NMOS tube N14, a fifteenth NMOS tube N15, an eighth NOT gate inv8 and a ninth NOT gate inv9;

the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are sequentially connected in series, and the other end of the sixth resistor R6, the source electrode of the eighteenth PMOS tube P18 and the source electrode of the nineteenth PMOS tube P19 are connected with the VBB pin; the drain of the eighteenth PMOS transistor P18 is connected to one end of the ninth resistor R9, the gate of the nineteenth PMOS transistor P19, and the gate of the thirteenth NMOS transistor N13; the grid electrode of the eighteenth PMOS pipe P18 is connected with the connection point of the sixth resistor R6 and the seventh resistor R7; a connection point of the seventh resistor R7 and the eighth resistor R8 is connected to a drain of a seventeenth NMOS transistor N17, and a gate of the seventeenth NMOS transistor N17 is connected to an output terminal of the eighth not gate inv 8; the drain electrode of the nineteenth PMOS tube P19 and the drain electrode of the thirteenth NMOS tube N13 are both connected with the input end of the eighth NOT gate inv 8; the source electrode of the thirteenth NMOS tube N13 and the drain electrode of the fifteenth NMOS tube N15 are both connected with the drain electrode and the grid electrode of the fourteenth NMOS tube N14; the grid electrode of the fifteenth NMOS tube N15 and the output end of the eighth NOT gate inv8 are both connected with the input end of the ninth NOT gate inv9; the output end of the ninth not gate inv9 is connected with the input end of the delay unit; the delay unit is used for delaying an output enable signal EN;

the source electrode of the seventeenth NMOS transistor N17, the other end of the eighth resistor R8, the other end of the ninth resistor R9, the source electrode of the fourteenth NMOS transistor N14, and the source electrode of the fifteenth NMOS transistor N15 are all connected to the high-side power supply voltage Vs.

Further, the delay unit includes a fourth current source I4, a twentieth PMOS transistor P20, a sixteenth NMOS transistor N16, a fourth capacitor C4, a tenth not gate inv10, and an eleventh not gate inv11;

the input end of the fourth current source I4 is connected with a VBB pin, and the output end of the fourth current source I4 is connected with the source electrode of a twentieth PMOS tube P20; the grid electrode of the twentieth PMOS tube P20 and the grid electrode of the sixteenth NMOS tube N16 are both connected with the output end of the ninth NOT gate inv9; the drain electrode of the twentieth PMOS transistor P20 is connected with the drain electrode of the sixteenth NMOS transistor N16 and one end of the fourth capacitor C4, and outputs the enable signal EN after passing through the tenth not gate inv10 and the eleventh not gate inv11 in sequence; and the source electrode of the sixteenth NMOS transistor N16 and the other end of the fourth capacitor C4 are both connected to a high-side power supply voltage Vs.

Further, the linear regulator is a low dropout linear regulator, and comprises a first voltage regulator tube Dz1, a first field effect tube N1, a first PMOS tube P1 and a first capacitor C1; wherein: the negative electrode of the first voltage-regulator tube Dz1 is connected with a VBB pin and one end of a first capacitor C1, the other end of the first capacitor C1 is connected with the source electrode of a first PMOS tube P1, the grid electrode of the first PMOS tube P1 is connected with the positive electrode of the first voltage-regulator tube Dz1 and the drain electrode of a first field-effect tube N1, and the grid electrode and the source electrode of the first field-effect tube N1 are both connected with an IN pin and the drain electrode of the first PMOS tube P1; the source electrode of the first PMOS pipe P1 is used for outputting a high-side power supply voltage Vs;

the first field effect transistor N1, the second field effect transistor N2 and the third field effect transistor N3 are high-voltage-loss or JEFT field effect transistors;

the first PMOS tube P1, the second PMOS tube P2 and the third PMOS tube P3 are high-voltage PMOS tubes;

the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7 and the eighth PMOS tube P8 are low-voltage PMOS tubes;

the sixteenth PMOS tube P16 is a high-voltage PMOS tube;

the reference resistor R1 and the detection resistor R2 are resistors with the same type, consistent width-length ratio and high matching degree.

The invention has the beneficial effects that:

1. according to the invention, the short-circuit protection unit is added in the high-side MOSFET switch chip, and the short-circuit protection unit generates a short-circuit protection signal when the chip outputs a short circuit, and pulls down the clamping voltage Vgs of the power MOS tube in the GATE driving end, or turns off the power MOS tube and locks the protection state, so that the purpose of current limiting is achieved, and the effect of protecting the power MOS tube is achieved. Specifically, the unit detects the on-voltage Von, and compares the on-voltage Von with a first short-circuit threshold voltage Vth1, a second short-circuit threshold voltage Vth2 and a third short-circuit threshold voltage Vth3 to perform short-circuit protection or voltage clamping on the power MOS transistor.

2. The invention adopts the low dropout linear regulator to realize a high-side power supply; the low-voltage device is adopted to complete various functional designs of short-circuit protection, so that the area can be saved, and the circuit design can be simplified.

3. The added short-circuit protection unit does not influence the normal work of the high-side MOSFET switch chip.

Drawings

FIG. 1 is a schematic diagram of a system architecture of a prior art high-side MOSFET switch chip;

FIG. 2 is a schematic diagram of the external connection relationship of the short-circuit protection unit in the high-side MOSFET switch chip of the present invention;

FIG. 3 is a flow chart of a short circuit protection method of the present invention;

FIG. 4 is a schematic diagram of a low dropout linear regulator (LDO) of the present invention;

FIG. 5 is a schematic diagram of a first stage Von detection circuit in the short circuit protection unit;

fig. 6 is a schematic diagram of a delay time generation circuit in the short-circuit protection unit;

FIG. 7 is a schematic diagram of a second stage Von detection and clamp current limiting circuit in the short protection unit;

FIG. 8 is a schematic diagram of an enable signal generation circuit;

fig. 9 is an operation waveform of each input signal after output short-circuiting:

fig. 10 is a waveform of operation of each input signal when normal operation is performed first and then short-circuited to be output:

fig. 11 is the operating waveforms of the second stage Von detection and clamp current limiting circuit and the power MOS clamp voltage Vgs.

Detailed Description

Referring to fig. 2, the present invention adds an oscillator, a low dropout regulator and a short-circuit protection unit to the existing high-side MOSFET switch chip, wherein the oscillator is used for providing an internal clock signal.

Fig. 4 to 8 are schematic electrical schematic diagrams of the low dropout regulator in the high-side MOSFET switch chip with short-circuit protection, the first stage Von detection circuit, the delay time generation circuit, the second stage Von detection and clamping current limiting circuit, and the enable signal generation circuit in sequence.

Wherein:

FIG. 4 is a schematic diagram of a low dropout regulator LDO, wherein the first FET N1 is a high-voltage drain or JFET FET for generating a current bias; the first voltage regulator tube Dz1 is used as a reference voltage; the first PMOS is a high-voltage PMOS tube and is used for resisting high voltage; as can be seen from the figure, the output voltage = Vbb-Vs = Vdz1-Vgs _ p1 of the low dropout linear regulator.

Fig. 5 is a first-stage Von detection circuit, in which fourth to seventh PMOS transistors P4 to P7 are all high-side low-voltage PMOS transistors, and second and third PMOS transistors P2 and P3 are high-voltage PMOS transistors for high voltage resistance; the fets N2 and N3 are high-voltage-drain or JFET fets operating in the saturation region to provide bias current. The working principle of the first-stage Von detection circuit is that the voltage drop of a first voltage-regulator tube is added to a reference resistor R1 to generate a reference current Idz, the breakover voltage Von is added to a detection resistor R2 to generate a detection current Ionsc, and the detection current Ionsc is compared with the reference current Idz according to the working principle of a current mirror, so that whether the detection signal Vonsc reaches a first short-circuit threshold voltage Vth1 or not is judged.

Fig. 6 is a delay time generation circuit. In the figure, a first delay time generation unit is composed of a first current source I1, a first not gate inv1, a ninth PMOS tube P9, a sixth NMOS tube N6, a second capacitor C2, a seventh NMOS tube N7, a second not gate inv2 and a third not gate inv 3; when the ninth PMOS transistor P9 is turned on and the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are turned off, the first current source I1 charges the first capacitor C1 until the second not gate inv2 is turned over, and the first delay Tdelay1 ends; the detection signal Vonsc is a detection signal output by the first-stage Von detection circuit. Similarly, the second current source I2, the fourth not gate inv4, the tenth PMOS transistor P10, the eighth NMOS transistor N8, the third capacitor C3, the fifth not gate inv5, and the sixth not gate inv6 form a second delay time generation unit for generating a second delay time Tdelay2; where EN is the enable signal.

Fig. 7 is a second stage Von detection and clamp current limit circuit. In the figure, a third current source I3 provides current bias, and an eleventh PMOS tube P11 and a twelfth PMOS tube P12 form a current mirror; the sum of the clamping voltages of the thirteenth PMOS tube P13, the fourteenth PMOS tube P14 and the ninth NMOS tube N9 is taken as a third short circuitThreshold voltage Vth3 reference voltage; when the on-state voltage Von = (Vbb-Vout) is greater than the third short-circuit threshold voltage Vth3 (i.e., the clamping voltage of the three fets), the tenth NMOS transistor N10 is turned on, and then the seventeenth PMOS transistor P17 and the twelfth NMOS transistor N12 are turned on, clamping the voltage drop between the GATE driving terminal and the OUT terminal, and the clamping voltage is (R) ₃ +R ₄ )/R ₃ X Vgs _ p17 for current limiting purposes. After the time delay of Tdelay2, if the on-voltage Von is greater than the second short-circuit threshold voltage Vth2 (i.e. the clamping voltage of a fet), the voltage drop between the GATE driver and the OUT pin is clamped. The sixteenth PMOS transistor P16 is a high-voltage PMOS transistor, and is used as a switch, and the on-voltage Von is detected only when the internal driving signal inL is low, that is, the on-voltage Von is detected when the power MOS transistor is in an on state.

Fig. 8 is an enable signal generating circuit. In the figure, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, an eighteenth PMOS transistor P18, and a ninth resistor R9 constitute an enable module; the seventeenth NMOS transistor N17 is used for hysteresis voltage setting after startup; a nineteenth PMOS tube P19, a thirteenth NMOS tube N13, a fourteenth NMOS tube N14, a fifteenth NMOS tube N15, an eighth NOT gate inv8 and a ninth NOT gate inv9 form a shaper and a second-stage hysteresis, and high and low levels are output; the eighth not gate inv8 outputs a uvloH signal which is connected to the grid of the seventeenth NMOS transistor N17; a fourth current source I4, a twentieth PMOS transistor P20, a sixteenth NMOS transistor N16, a fourth capacitor C4, a tenth not gate inv10, and an eleventh not gate inv11 form a delay circuit, that is, the enable signal EN is output after a period of delay.

Referring to fig. 3, the invention realizes a high-side MOSFET switch chip short-circuit protection flow chart:

1) An input signal of an IN pin is accessed, a linear voltage-stabilized power supply is built IN a high-side MOSFET switch chip, the internal linear voltage-stabilized power supply is a high-side voltage-stabilized power supply, and the high-side power supply voltage Vs is regarded as a high-side ground; then, realizing a short-circuit protection function under a high-side voltage-stabilized power supply;

2) Shielding the output short-circuit protection signal within the second delay time Tdelay2;

simultaneously, performing first-stage Von detection; if the on-state voltage Von is larger than the first short-circuit threshold voltage Vth1 and the on-state voltage Von is larger than the first short-circuit threshold voltage Vth1 within the second delay time Tdelay1, judging that the output short circuit occurs, and pulling down a GATE driving end by the output short-circuit protection signal to turn off the power MOS tube and lock the protection state;

meanwhile, performing second-level Von detection; if the conduction voltage Von is larger than a third short-circuit threshold voltage Vth3, the output short-circuit protection signal pulls down a GATE driving end and clamps the clamping voltage Vgs of the power MOS tube so as to achieve the purpose of current limiting;

3) After the second delay time Tdelay2 is over, if the on-voltage Von > the second short-circuit threshold voltage Vth2, the GATE driving terminal is pulled down and the clamping voltage Vgs of the power MOS transistor is clamped, so as to achieve the purpose of current limiting.

Fig. 9 is a working waveform of each input turn-on signal after the chip of the present invention outputs the short circuit first. The output is firstly short-circuited, voltage is input at an IN pin at the time of t1, a high-side power supply voltage Vs is established, an enable signal EN is triggered at the time of t2 after delay to generate an internal driving signal inL, then a power MOS tube is started, the output current IL rises, short-circuit protection is triggered at the time of t3 after the delay of Tdelay2, the power MOS tube is turned off, and the output current IL becomes 0.

Fig. 10 is a waveform of operation when the chip of the present invention operates normally and then short-circuits for output. The output is firstly provided with a normal load, voltage is input at an IN pin at the time of t1, a high-side power supply voltage Vs is established, an enable signal EN is triggered at the time of t2 after delay to generate an internal driving signal inL, then a power MOS tube is started, an output current IL rises, the output still normally works after the delay of Tdelay2, the output is short-circuited at the time of t4, the output current rises instantly and enters current limiting at the time of t5, short-circuit protection is triggered after the delay of Tdelay1, the power MOS tube is turned off, and the output current IL is reduced to 0.

Fig. 11 is the operating waveforms of the second stage Von detection and clamp current limiting circuit and the power MOS clamp voltage Vgs. Before an input signal is started, a load power supply works normally, an IN pin is started at the moment t1 to input the signal, the high-side power supply voltage Vs is established, a power MOS tube is conducted at the moment t2, the conduction voltage Von is reduced, and the conduction voltage Von is greater than a third short-circuit threshold voltage Vth3 between t2 and t3, so that the clamping voltage Vgs of the power MOS tube is clamped to limit the output current; until the moment t3, the conduction voltage Von is smaller than a third short-circuit threshold voltage Vth3, the current limiting is relieved, and the clamping voltage Vgs of the power MOS tube is increased to the normal voltage; after the start is finished, increasing the load at the time t4 to enable the breakover voltage Von to be larger than the second short-circuit threshold voltage Vth2, entering a current limiting mode, pulling down the clamping voltage Vgs of the power MOS tube to limit the output current, namely, the threshold value entering the current limiting mode after the start is finished is reduced from the third short-circuit threshold voltage Vth3 to the second short-circuit threshold voltage Vth2, and releasing the output current limitation until the breakover voltage Von is smaller than the second short-circuit threshold voltage Vth2 at the time t 5; and (3) the output is short-circuited at the time t6, the on-state voltage Von is suddenly increased and is larger than the first short-circuit threshold voltage Vth1, current limitation is carried out at the time, short-circuit protection delay is started, short-circuit protection is triggered until the short-circuit protection delay at the time t7 is finished, the power MOS tube is turned off, and the clamping voltage Vgs of the power MOS tube starts to drop to 0.

Claims

1. A short-circuit protection control method of a high-side MOSFET switch chip is characterized by comprising the following steps:

the second-stage Von detection is to clamp the voltage drop of the GATE driving end and the VOUT pin to the clamping voltage if the on-voltage Von is greater than the third short-circuit threshold voltage Vth3 and less than the first short-circuit threshold voltage Vth1, or the on-voltage Von is greater than the second short-circuit threshold voltage Vth2 and less than the third short-circuit threshold voltage Vth3 and the holding time exceeds the second delay time Tdelay2;

the first short-circuit threshold voltage Vth1 is more than the third short-circuit threshold voltage Vth3 is more than the second short-circuit threshold voltage Vth2;

the second delay time Tdelay2 > the first delay time Tdelay1.

2. The short-circuit protection control method of the high-side MOSFET switch chip of claim 1, wherein:

the first-stage Von detection specifically comprises the steps that in a current mirror circuit, reference current generated by adding voltage drop of a second voltage-regulator tube to a reference resistor R1 is compared with detection current generated by adding breakover voltage Von to a detection resistor R2, so that whether the breakover voltage Von reaches a first short-circuit threshold voltage Vth1 or not is judged, if the breakover voltage Von is always greater than the first short-circuit threshold voltage Vth1 within a first delay time Tdelay1, after the second delay time Tdelay2 is over, an internal chip driving signal inL is output and is used as a short-circuit protection signal to pull down a GATE driving end voltage, so that a power MOS tube is turned off, and a short-circuit protection state is locked; if the on-voltage Von is greater than the first short-circuit threshold voltage Vth1 and the holding time does not exceed the first delay time Tdelay1, clamping the voltage drop of the GATE driving end and the OUT pin to the clamping voltage; the breakover voltage Von is the difference value of an input voltage Vbb of a VBB pin and an output voltage Vout of a VOUT pin, and the voltage drop of the first short-circuit threshold voltage Vth1 and the voltage drop of the second voltage-stabilizing tube is in a linear relation;

the second-stage Von detection is to clamp the voltage drop of the GATE driving end and the VOUT pin to the clamping voltage if the on-voltage Von is greater than the third short-circuit threshold voltage Vth3 and less than the first short-circuit threshold voltage Vth1, or the on-voltage Von is greater than the second short-circuit threshold voltage Vth2 and less than the third short-circuit threshold voltage Vth3 and the holding time exceeds the second delay time Tdelay2; the third short-circuit threshold voltage Vth3 is equal to the clamping voltage of three field effect transistors, and the second short-circuit threshold voltage Vth2 is equal to the clamping voltage of one field effect transistor; and shielding and outputting the short-circuit protection signal within the delayed second delay time Tdelay2 of the second-stage Von detection.

3. The short-circuit protection control method of the high-side MOSFET switch chip of claim 2, characterized in that:

the high-side power supply voltage Vs = Vbb-Vdz1+ Vgs _ p1 of the linear voltage stabilizer, wherein Vdz1 is the voltage drop of the first voltage stabilizer, and Vgs _ p1 is the clamping voltage of the first PMOS tube;

the clamping voltage is (R) ₃ +R ₄ )/R ₃ X Vgs _ p17, wherein R ₃ Is the resistance value of the third resistor R3, R ₄ The value of the fourth resistor is, and Vgs _ P17 is the clamping voltage of the seventeenth PMOS tube P17;

4. The high-side MOSFET switch chip with short-circuit protection for realizing the method of any one of claims 1 to 3, comprising a VBB pin, an IN pin, an IS pin, an OUT pin, a charge pump, an oscillator, a logic control unit, a linear voltage regulator and a power MOS tube; the linear voltage regulator is used for generating a high-side power supply voltage Vs according to an input voltage of an IN pin;

the method is characterized in that: the short-circuit protection device also comprises a short-circuit protection unit; the short-circuit protection unit is respectively connected with a VBB pin, a high-side power supply voltage Vs, an OUT pin and a power MOS (metal oxide semiconductor) transistor GATE driving end;

the first-stage Von detection circuit is used for comparing a current Ionsc generated by an on-state voltage Von with a reference current Idz generated by an IN pin and outputting a detection signal Vonsc, wherein the detection signal Vonsc is used for judging whether the on-state voltage Von reaches a first short-circuit threshold voltage Vth1;

the enabling signal generating circuit is used for delaying for a period of time and then outputting an enabling signal EN;

the second delay time Tdelay2 > the first delay time Tdelay1.

5. The high-side MOSFET switch chip with short-circuit protection of claim 4, wherein:

the first-stage Von detection circuit comprises a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a second voltage-regulator tube Dz2, a reference resistor R1, a detection resistor R2, a second field-effect tube N2, a third field-effect tube N3, a fourth NMOS tube N4 and a fifth NMOS tube N5;

the source electrodes of a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7 and an eighth PMOS tube P8 are all connected with a VBB pin; the grid and the drain of the fourth PMOS tube P4 are both connected with the cathode of the second voltage-regulator tube Dz2, the anode of the second voltage-regulator tube Dz2 is connected with the source of the second PMOS tube P2, the drain and the grid of the second PMOS tube P2 are both connected with the drain of the second field-effect tube N2, and the grid and the source of the second field-effect tube N2 are both connected with an IN pin; the grid electrode and the drain electrode of the fifth PMOS tube P5 are both connected with one end of the reference resistor R1, the other end of the reference resistor R1 is connected with the source electrode of the third PMOS tube P3, the grid electrode of the third PMOS tube P3 is connected with the grid electrode of the second PMOS tube P2, and the drain electrode of the third PMOS tube P3 is connected with the IN pin; the grid electrode of a sixth PMOS pipe P6 is connected with the grid electrode of a fifth PMOS pipe P5, and the drain electrode of the sixth PMOS pipe P6 is connected with the drain electrode of a fifth NMOS pipe N5; the drain electrode of the eighth PMOS tube P8 is connected with the drain electrode and the grid electrode of the fourth NMOS tube N4, and the source electrode of the fourth NMOS tube N4 and the source electrode of the fifth NMOS tube N5 are both connected with a high-side power supply voltage Vs; the grid electrode of the eighth PMOS tube P8 is connected with the grid electrode of the seventh PMOS tube P7; the grid and the drain of the seventh PMOS tube P7 are both connected with one end of the detection resistor R2, the other end of the detection resistor R2 is connected with the drain of the third field-effect tube N3, and the grid and the source of the third field-effect tube N3 are both connected with the OUT pin; the drain electrode of the sixth PMOS transistor P6 is used for leading out the detection signal Vonsc output by the first-stage Von detection circuit.

6. The high-side MOSFET switch chip with short-circuit protection of claim 4 or 5, wherein:

the delay time generation circuit comprises a first current source I1, a first not gate inv1, a ninth PMOS (P-channel metal oxide semiconductor) tube P9, a sixth NMOS (N-channel metal oxide semiconductor) tube N6, a second capacitor C2, a seventh NMOS tube N7, a second not gate inv2, a third not gate inv3, a second current source I2, a fourth not gate inv4, a tenth PMOS tube P10, an eighth NMOS tube N8, a third capacitor C3, a fifth not gate inv5, a sixth not gate inv6, a first NAND gate nand1, a second NAND gate nand2 and a seventh not gate inv7;

one end of the first current source I1 is connected with a VBB pin, and the other end of the first current source I1 is connected with a source electrode of a ninth PMOS tube P9; the input end of the first NOT gate inv1 is connected with the detection signal Vonsc output by the first-stage Von detection circuit, and the output end of the first NOT gate inv1 is connected with the grid electrode of the ninth PMOS tube P9 and the grid electrode of the sixth NMOS tube N6; the drain electrode of the ninth PMOS transistor P9 and the drain electrode of the sixth NMOS transistor N6 are connected to one end of the second capacitor C2, the drain electrode of the seventh NMOS transistor N7 and the input end of the second not gate inv 2; the output end of the second not gate inv2 is connected with the input end of a third not gate inv3, and the output end of the third not gate inv3 is connected with one input end of the first nand gate nand 1; the source electrode of the sixth NMOS transistor N6, the source electrode of the seventh NMOS transistor N7 and the other end of the second capacitor C2 are all connected with a high-side power supply voltage Vs;

7. The high-side MOSFET switch chip with short-circuit protection of claim 6, wherein:

the second-stage Von detection and clamping current-limiting circuit comprises a third current source I3, a current mirror consisting of an eleventh PMOS (P-channel metal oxide semiconductor) tube P11 and a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, a seventeenth PMOS tube P17, a ninth field-effect tube N9, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a third resistor R3, a fourth resistor R4 and a fifth resistor R5;

the input end of the third current source I3 is connected with a high-side power supply voltage Vs, and the output end of the third current source I is connected with the drain electrode and the grid electrode of the eleventh PMOS tube P11 and the grid electrode of the twelfth PMOS tube P12; the source electrode of the eleventh PMOS pipe P11 and the source electrode of the twelfth PMOS pipe P12 are both connected with the VBB pin; the drain of the twelfth PMOS tube P12 is connected with the source of the thirteenth PMOS tube P13 and the source of the fifteenth PMOS tube P15; the grid electrode and the drain electrode of the thirteenth PMOS tube P13 are both connected with the source electrode of the fourteenth PMOS tube P14, and the grid electrode and the drain electrode of the fourteenth PMOS tube P14 and the drain electrode of the fifteenth PMOS tube P15 are both connected with the source electrode of the sixteenth PMOS tube P16; the drain electrode of the sixteenth PMOS tube P16 is connected with the drain electrode and the grid electrode of the ninth NMOS tube N9, the grid electrode of the tenth NMOS tube N10 and the grid electrode of the eleventh NMOS tube N11; the drain electrode of the tenth NMOS tube N10 is connected with the grid electrode of the power MOS tube, the source electrode of the seventeenth PMOS tube P17 and the drain electrode of the twelfth NMOS tube N12 sequentially through the fourth resistor R4 and the third resistor R3; the grid electrode of a seventeenth PMOS tube P17 is connected with the connection point of the fourth resistor R4 and the third resistor R3, and the drain electrode of the seventeenth PMOS tube P17 is connected with the drain electrode of the eleventh NMOS tube N11, one end of the fifth resistor R5 and the grid electrode of the twelfth NMOS tube N12; the source electrode of the ninth NMOS transistor N9, the source electrode of the tenth NMOS transistor N10, the source electrode of the eleventh NMOS transistor N11, the other end of the fifth resistor and the source electrode of the twelfth NMOS transistor N12 are all connected with an OUT pin; the gate of the fifteenth PMOS transistor P15 is configured to receive the second delay time signal Tdelay2.

8. The high-side MOSFET switch chip with short-circuit protection of claim 7, wherein:

the enabling signal generating circuit comprises an enabling starting unit, a first-stage hysteresis unit, a shaping and second-stage hysteresis unit and a delay unit; the enabling and starting unit comprises a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, an eighteenth PMOS tube P18 and a ninth resistor R9; the first-stage hysteresis unit comprises a seventeenth NMOS tube N17; the shaping and second-stage hysteresis unit comprises a nineteenth PMOS tube P19, a thirteenth field effect tube N13, a fourteenth NMOS tube N14, a fifteenth NMOS tube N15, an eighth NOT gate inv8 and a ninth NOT gate inv9;

the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are sequentially connected in series, and the other end of the sixth resistor R6, the source electrode of the eighteenth PMOS tube P18 and the source electrode of the nineteenth PMOS tube P19 are connected with the VBB pin; the drain of the eighteenth PMOS transistor P18 is connected to one end of the ninth resistor R9, the gate of the nineteenth PMOS transistor P19 and the gate of the thirteenth NMOS transistor N13; the grid electrode of the eighteenth PMOS pipe P18 is connected with the connection point of the sixth resistor R6 and the seventh resistor R7; a connection point of the seventh resistor R7 and the eighth resistor R8 is connected to a drain of a seventeenth NMOS transistor N17, and a gate of the seventeenth NMOS transistor N17 is connected to an output terminal of the eighth not gate inv 8; the drain electrode of the nineteenth PMOS tube P19 and the drain electrode of the thirteenth NMOS tube N13 are both connected with the input end of the eighth NOT gate inv 8; the source electrode of the thirteenth NMOS tube N13 and the drain electrode of the fifteenth NMOS tube N15 are both connected with the drain electrode and the grid electrode of the fourteenth NMOS tube N14; the grid electrode of the fifteenth NMOS tube N15 and the output end of the eighth NOT gate inv8 are both connected with the input end of the ninth NOT gate inv9; the output end of the ninth not gate inv9 is connected with the input end of the delay unit; the delay unit is used for delaying an output enable signal EN;

9. The high-side MOSFET switch chip with short-circuit protection of claim 8, wherein:

the delay unit comprises a fourth current source I4, a twentieth PMOS (P-channel metal oxide semiconductor) tube P20, a sixteenth NMOS (N-channel metal oxide semiconductor) tube N16, a fourth capacitor C4, a tenth NOT gate inv10 and an eleventh NOT gate inv11;

10. The high-side MOSFET switch chip with short-circuit protection of claim 9, wherein:

the linear voltage stabilizer is a low dropout linear voltage stabilizer and comprises a first voltage stabilizing tube Dz1, a first field effect tube N1, a first PMOS tube P1 and a first capacitor C1; wherein: the negative electrode of the first voltage-regulator tube Dz1 is connected with a VBB pin and one end of a first capacitor C1, the other end of the first capacitor C1 is connected with the source electrode of a first PMOS tube P1, the grid electrode of the first PMOS tube P1 is connected with the positive electrode of the first voltage-regulator tube Dz1 and the drain electrode of a first field-effect tube N1, and the grid electrode and the source electrode of the first field-effect tube N1 are both connected with an IN pin and the drain electrode of the first PMOS tube P1; the source electrode of the first PMOS pipe P1 is used for outputting a high-side power supply voltage Vs;

the sixteenth PMOS tube P16 is a high-voltage PMOS tube;