CN115732586A - Battery array and power supply system - Google Patents

Abstract

The application discloses battery array and electrical power generating system, include the base plate and be located a plurality of groups of parallelly connected on the base plate, every group battery includes a plurality of battery cell, thereby realize the arraying of battery cell and arrange, and, in every group battery, be provided with selection circuit between every two adjacent battery cell, selection circuit makes two adjacent battery cell series connection when the first control signal of receipt is the active level period, when the second control signal of receipt is the active battery period, make two adjacent battery cell parallel connection, thereby can realize every group battery output voltage's change through the series-parallel connection relation that changes each battery cell in every group battery, the change of rethread battery array output voltage is realized to the parallel connection of each group battery, in order to match different operating voltage's electronic equipment, need not to set up complicated power management system, reduce thin film battery system's volume and complexity, be favorable to thin film battery system's miniaturization.

Description

Battery array and power supply system

Technical Field

The application relates to the technical field of thin film batteries, in particular to a battery array and a power supply system.

Background

The thin film battery system can be used as a main energy source of portable electronic equipment and sensors due to the characteristics of easy miniaturization and flexibility, and the thin film battery systems with different output voltages need to be matched due to different requirements of the portable electronic equipment and the sensors on working voltages.

However, in the conventional thin film battery system, since the output voltage of a single thin film battery is determined by the electrochemical reaction therein, and cannot be changed after the manufacturing is completed, and the electrical connection relationship between different thin film batteries is usually determined at the time of factory shipment and cannot be changed, a complicated power management system needs to be provided to change the output voltage of the thin film battery system in order to match portable electronic devices and sensors with different operating voltages, which inevitably increases the volume and complexity of the thin film battery system, and is not favorable for the miniaturization of the thin film battery system.

Disclosure of Invention

In order to solve the above technical problem, embodiments of the present application provide a battery array and a power supply system to implement an array arrangement of battery units, and implement a series-parallel relationship control between different battery units through an array circuit design, thereby implementing a change of an output voltage.

In order to achieve the above object, the embodiments of the present application provide the following technical solutions:

a battery array, comprising:

a substrate;

the battery pack comprises a plurality of battery units which are arranged on a substrate and connected in parallel, each battery unit comprises a plurality of battery units, a selection circuit is arranged between every two adjacent battery units in each battery unit, the selection circuit receives a first control signal and a second control signal, the selection circuit enables the two adjacent battery units to be connected in series when the first control signal reaches an effective level time interval, the selection circuit enables the two adjacent battery units to be connected in parallel when the second control signal reaches the effective level time interval, and the effective level time interval of the first control signal and the effective level time interval of the second control signal do not overlap.

A power supply system comprises the battery array.

Compared with the prior art, the technical scheme has the following advantages:

the battery array provided by the embodiment of the application comprises a substrate and a plurality of battery packs which are positioned on the substrate and connected in parallel, wherein each battery pack comprises a plurality of battery units, so that arrayed arrangement of the battery units is realized, in each battery pack, a selection circuit is arranged between every two adjacent battery units, when a received first control signal is in an effective level time period, the two adjacent battery units are connected in series through the selection circuit, when a received second control signal is in an effective battery time period, the two adjacent battery units are connected in parallel, the effective level time period of the first control signal and the effective level time period of the second control signal are not overlapped, so that the change of the output voltage of each battery pack can be realized by changing the series-parallel relation of each battery unit in each battery pack, the change of the output voltage of the battery array is realized through the parallel connection of each battery pack, the portable electronic equipment and sensors with different working voltages are matched, a complex power management system is not required to be arranged, the volume and the complexity of the thin film battery system are reduced, and the miniaturization of the thin film battery system is facilitated.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic top view of a battery array according to an embodiment of the present disclosure;

fig. 2 is a schematic top view of another battery array provided in an embodiment of the present application;

fig. 3 is a schematic top view of another battery array provided in the embodiments of the present application;

fig. 4 is a schematic diagram of a selection circuit in a battery array according to an embodiment of the present disclosure;

fig. 5 is a schematic top view of another battery array provided in an embodiment of the present application;

fig. 6 is a schematic top view of another battery array provided in the embodiments of the present application;

fig. 7 is a schematic structural diagram of another selection circuit in the battery array according to the embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of another selection circuit in the battery array according to the embodiment of the present application;

fig. 9 is a schematic layout diagram of an entirety including a battery cell and a selection circuit electrically connected to the battery cell in the battery array according to the embodiment of the present disclosure;

FIG. 10 is a schematic cross-sectional view of FIG. 9 taken at the AA' line.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be appreciated by those skilled in the art that the present application may be practiced without departing from the spirit and scope of the present application, and that the present application is not limited to the specific embodiments disclosed below.

Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

As described in the background section, in the conventional thin film battery system, in order to match portable electronic devices and sensors with different operating voltages, a complicated power management system needs to be arranged to change the output voltage of the thin film battery system, which inevitably increases the volume and complexity of the thin film battery system, and is not beneficial to the miniaturization of the thin film battery system.

In view of the above, an embodiment of the present application provides a battery array, and fig. 1 is a schematic top view of the battery array provided in the embodiment of the present application, as shown in fig. 1, the battery array includes:

a substrate 100;

the battery pack comprises a plurality of battery packs 10 connected in parallel on a substrate, each battery pack 10 comprises a plurality of battery units 11, a selection circuit 12 is arranged between every two adjacent battery units 11 in each battery pack 10, the selection circuit 12 receives a first control signal D1 and a second control signal D2, the selection circuit 12 enables the two adjacent battery units 11 to be connected in series when the first control signal D1 reaches an effective level period, the selection circuit 12 enables the two adjacent battery units 11 to be connected in parallel when the second control signal D2 reaches the effective level period, and the effective level period of the first control signal D1 and the effective level period of the second control signal D2 do not overlap.

In the embodiment of the present application, the substrate 100 may be a rigid substrate or a flexible substrate, as the case may be.

In the embodiment of the present application, the battery packs 10 are connected in parallel, and each battery pack 10 includes a plurality of battery cells 11, so that the array arrangement of the battery cells 11 is realized to form a battery cell array. In fig. 1 and subsequent drawings, only 3 battery cells 11 are shown in each battery pack 10 for clarity of the drawings, but the number of battery cells 11 in each battery pack 10 is not limited in the present application, and may be more than 2.

In the embodiment of the present application, as shown in fig. 1, different battery packs 10 are connected in parallel, and are finally connected to the input/output circuit 20, so that the output voltage of the battery array is the parallel value of the output voltage of each battery pack 10 and is output by the input/output circuit 20. Each battery pack 10 can realize series-parallel connection of a plurality of battery units 11 therein through the selection circuit 12, and change of output voltage of each battery pack 10 can be realized by adjusting series-parallel connection relationship of a plurality of battery units 11 in each battery pack 10, for example, increasing the battery units 11 connected in series in the battery pack 10 so that the output voltage of the battery pack 10 is increased; for another example, the battery cells 11 connected in parallel in the battery pack 10 are increased so that the output voltage of the battery pack 10 is decreased, and at this time, the total current of the battery pack 10 is increased to increase the capacity, whereby the change in the output voltage of the battery array and the change in the capacity can be realized.

In the embodiment of the present application, the first control signal D1 and the second control signal D2 are both periodic square wave signals that are arranged according to a certain duration and sequence by a high level and a low level, and their active level periods may be high level periods or low level periods, as the case may be.

The active level period of the first control signal D1 and the active level period of the second control signal D1 do not overlap, that is, when the first control signal D1 reaches the active level period, the second control signal D2 is a non-active level period, and when the second control signal D2 reaches the active level period, the first control signal D1 is a non-active level period. Specifically, when the first control signal D1 reaches the active level period, the first control signal D1 controls the selection circuit 12 to be in the first connection mode, so that the two adjacent battery cells 11 connected to the selection circuit 12 are connected in series, and similarly, when the second control signal D2 reaches the active level period, the second control signal D2 controls the selection circuit 12 to be in the second connection mode, so that the two adjacent battery cells 11 connected to the selection circuit 12 are connected in parallel.

It should be noted that the specific circuit structure of the selection circuit 12 is not limited in the present application, as long as the selection circuit 12 is controlled by two control signals, and when one control signal reaches an active level period, two adjacent battery cells 11 connected to the selection circuit 12 are connected in series, and when the other control signal reaches an active level period, two adjacent battery cells 11 connected to the selection circuit 12 are connected in parallel.

It can be seen that the battery array provided in the embodiment of the present application includes a substrate 100 and a plurality of battery packs 10 disposed on the substrate 100 and connected in parallel, each battery pack 10 includes a plurality of battery cells 11, so as to implement an arrayed arrangement of the battery cells 11, and in each battery pack 10, a selection circuit 12 is disposed between every two adjacent battery cells 11, the selection circuit connects two adjacent battery cells 11 in series when the received first control signal D1 is in an active level period, and connects two adjacent battery cells 11 in parallel when the received second control signal D2 is in an active level period, so that the active level period of the first control signal D1 and the active level period of the second control signal D2 do not overlap, thereby implementing a change in output voltage of each battery pack 10 by changing a series-parallel relationship of the plurality of battery cells 11 in each battery pack 10, and implementing a change in output voltage of the battery array by parallel connection of the battery packs 10, so as to match portable electronic devices and sensors with different operating voltages, without providing a complex power management system, reducing the volume and complexity of the thin film battery system, and facilitating miniaturization of the thin film battery system.

Alternatively, in an embodiment of the present application, as shown in fig. 2, a plurality of battery packs 10 are arranged along a first direction X, a plurality of battery units 11 in each battery pack 10 are arranged along a second direction Y, and the selection circuits 12 between two adjacent battery units 11 in each battery pack 10 are arranged along the first direction X, where the first direction X intersects with the second direction Y;

the battery array further includes: a plurality of groups of control signal lines 30, wherein the selection circuits 12 between two adjacent battery units 11 in each battery pack 10 are electrically connected with one group of control signal lines 30 in common;

each set of control signal lines 30 includes a first control signal line 31 and a second control signal line 32, the first control signal line 31 being configured to provide a first control signal D1 to the selection circuit 12, the second control signal line 32 being configured to provide a second control signal D2 to the selection circuit 12.

In the present embodiment, a plurality of battery packs 10 are arranged in the first direction X, and a plurality of battery cells 11 in each battery pack 10 are arranged in the second direction Y. Referring to fig. 2, assuming that the battery array includes M battery packs 10, where M is an integer greater than or equal to 2, the 1 st battery pack 10 to the mth battery pack 10 are arranged along the first direction X, each battery pack 10 includes N battery units 11, where N is an integer greater than or equal to 2, the 1 st battery unit 11 to the nth battery unit 11 are arranged along the second direction Y, then the ith battery unit 11 in each battery pack 10 is arranged along the first direction X, where i is an integer greater than or equal to 1 and less than N, the i +1 th battery unit 11 in each battery pack 10 is also arranged along the first direction X, and the selection circuit 12 between the i-th battery unit 11 and the i +1 th battery unit 11 in each battery pack 10 is also arranged along the first direction X, that is, the selection circuit 12 between two adjacent battery units 11 in each battery pack 10 is arranged along the first direction X. Also, in each battery pack 10, a selection circuit 12 is provided between each adjacent two of the battery cells 11, that is, the selection circuits 12 between the adjacent two of the battery cells 11 in each battery pack 10 are arranged in the second direction Y. As can be seen, in the battery array provided in the present embodiment, not only the battery cells 11 but also the selection circuits 12 are arranged in an array.

In this embodiment, optionally, as shown in fig. 2, the first direction X and the second direction Y intersect perpendicularly.

It should be noted that, in each battery pack 10, the selection circuit 12 is only disposed between two adjacent battery units 11, and the selection circuit 12 is not disposed on the side of the 1 st battery unit 11 away from the 2 nd battery unit 11, and on the side of the nth battery unit 11 away from the N-1 st battery unit 11, but is connected to the input/output circuit 20 of the battery array to output the voltage.

In the present embodiment, since the selection circuits between two adjacent battery cells 11 in each battery pack 10 are arranged along the first direction X, the selection circuits 12 between two adjacent battery cells 11 in each battery pack 10 may electrically connect a group of control signal lines 30 in common, that is, the selection circuits 12 between the i-th battery cell 11 and the i + 1-th battery cell 11 in each battery pack 10 receive the first control signal D1 simultaneously through the first control signal line 31 in the group of control signal lines 30 electrically connected in common, then when the first control signal D1 reaches an active level period, the i-th battery cell 11 and the i + 1-th battery cell 11 in each battery pack 10 are connected in series through the selection circuits 12 therebetween, and when the first control signal D1 reaches an active level period, the selection circuits 12 between the i-th battery cell 11 and the i + 1-th battery cell 11 in each battery pack 10 are connected in series through the selection circuits 12 in the group of control signal lines 30 electrically connected in common, and when the second control signals D1 and 11 reach an active level, the second control signal line 32 in each battery pack 10, and the selection circuits 12 receive the control signal lines 2 in parallel. In this case, the plurality of battery cells 11 in each battery pack 10 are connected in series or in parallel in the same manner, and the output voltages of the battery packs 10 are the same.

In this embodiment, since the output voltages of the battery packs 10 are the same, and the output voltage of the battery array is the voltage value of the battery packs with the same output voltage after the battery packs are connected in parallel, if the output voltage of the battery array is the preset voltage, the same output voltage value of each battery pack required by the preset voltage of the battery packs with the same output voltage after the battery packs are connected in parallel is obtained first, and then the first control signal D1 provided by the first control signal line 31 in each battery pack control signal line 30 and the second control signal D2 provided by the second control signal line 32 are controlled to simultaneously change the serial-parallel connection relationship of the plurality of battery units 11 in each battery pack 10, thereby simultaneously changing the output voltage of each battery pack 10, and further enabling the battery array to output the preset voltage.

As can be seen, in the battery array provided in the present embodiment, the control of the plurality of selection circuits 12 in each battery pack 10 is the same, so that the control of each selection circuit 12 is simpler, and the wiring of the plurality of sets of control signal lines 30 is also simpler.

Alternatively, in another embodiment of the present application, as shown in fig. 1, each selection circuit 12 may also be electrically connected to a group of control signal lines 30, that is, each selection circuit 12 is individually controlled.

Alternatively, in another embodiment of the present application, referring to fig. 2, the selection circuits 12 between two adjacent battery cells 11 in a partial battery pack 10 may be electrically connected to a group of control signal lines 30 in common, that is, the selection circuits 12 in the partial battery pack 10 are controlled simultaneously.

On the basis that several ways for controlling the selection circuits 12 are listed above, a person skilled in the art may derive more control ways, as long as any selection circuit 12 adjusts the serial-parallel connection relationship between two adjacent battery units 11 under the control of the first control signal D1 and the second control signal D2 received by the selection circuit, and which selection circuits 12 are controlled simultaneously, that is, receive the same first control signal and second control signal, which is not limited.

On the basis that the same column selection circuit 12 shares one group of control signal lines 30, in an embodiment of the present application, as shown in fig. 3, the battery array further includes: and a column selection circuit 40, the column selection circuit 40 being electrically connected to each group of the control signal lines 30, the column selection circuit 40 being configured to supply a first control signal to the first control signal line 31 in each group of the control signal lines 30 and to supply a second control signal D2 to the second control signal line 32 in each group of the control signal lines 30.

It can be seen that, in the battery array provided in the present embodiment, the column selection circuit 40 is arranged, so as to control the first control signal D1 provided by the first control signal line 31 in each group control signal line 30 according to the voltage value required to be output by the battery array, and the second control signal D2 provided by the second control signal line 32 in each group control signal line 30 changes the series-parallel connection relationship of the plurality of battery cells 11 in each battery pack 10, so as to change the output voltage of each battery pack 10, and enable the battery array to output the required voltage value. However, the present application is not limited to whether the column selection circuit 40 or a control circuit similar to the column selection circuit 40 is disposed in the battery array for providing the first control signal D1 and the second control signal D2, and in other embodiments of the present application, the column selection circuit 40 or a control circuit similar to the column selection circuit 40 for providing the first control signal D1 and the second control signal D2 may be disposed outside the battery array, and provide the first control signal D1 to the first control signal line 31 in each group of control signal lines 30 and provide the second control signal D2 to the second control signal line 32 in each group of control signal lines 30, as the case may be.

As can be seen from the foregoing embodiments, the selection circuits 12 between two adjacent battery cells 11 in each battery pack 10 are arranged along the first direction X, and based on this, optionally, in one embodiment of the present application, as shown in fig. 2 and 3, the first control signal line 31 and the second control signal line 32 both extend along the first direction, that is, the extending direction of the first control signal line 31 and the second control signal line 31 is the same as the arrangement direction of the selection circuits 12 between two adjacent battery cells 21 in each battery pack 10, so that the first control signal line 31 and the second control signal line 32 are reasonably arranged in the battery array, the wiring is short, and the occupied area is small.

In order to more clearly understand how the selection circuit arranged between every two adjacent battery units in each battery pack realizes series and parallel connection between the two adjacent batteries, a specific circuit structure of the selection circuit is listed below.

Specifically, in one embodiment of the present application, as shown in fig. 4, in the battery pack, each battery unit has a first pole and a second pole, two adjacent battery units are a first battery unit 111 and a second battery unit 112, respectively, and the selection circuit 12 between the two adjacent battery units includes:

a first transistor T1, a first pole of the first transistor T1 is electrically connected to the first pole of the first battery unit 111, a second pole of the first transistor T1 is electrically connected to the second pole of the second battery unit 112, and a control pole of the first transistor T1 is electrically connected to the first control signal line 31;

a second transistor T2, a first pole of the second transistor T2 is electrically connected to a second pole of the first battery cell 111, the second pole is electrically connected to a second pole of the second battery cell 112, and a control pole is electrically connected to the second control signal line 32;

and a third transistor T3 having a first electrode of the third transistor T3 connected to the first electrode of the first battery cell 111, a second electrode connected to the first electrode of the second battery cell 112, and a control electrode electrically connected to the second control signal line 32.

In specific operation, as shown in fig. 4, when the first control signal D1 provided by the first control signal line 31 is at an active level, the first transistor T1 is turned on, as shown by a solid arrow in fig. 4, a first pole of the first battery unit 111 is electrically connected to a second pole of the second battery unit 112 through the turned-on first transistor T1, that is, the first battery unit 111 and the second battery unit 112 are connected in series through the turned-on first transistor T1, and at this time, the second control signal D2 provided by the second control signal line 32 is at an inactive level, and both the second transistor T2 and the third transistor T3 are turned off;

as shown in fig. 4, when the second control signal D2 provided by the second control signal line 32 is at an active level, the second transistor T2 and the third transistor T3 are both turned on, as shown by a dotted arrow in fig. 4, the first pole of the first battery unit 111 is electrically connected to the first pole of the second battery unit 112 through the turned-on third transistor T3, and the second pole of the first battery unit 111 is electrically connected to the second pole of the second battery unit 112 through the turned-on second transistor T2, that is, the first battery unit 111 and the second battery unit 112 are connected in parallel through the turned-on second transistor T2 and the turned-on third transistor T3, and at this time, the first control signal D1 provided by the first control signal line 31 is at an inactive level, and the first transistor T1 is turned off.

In this embodiment, the first pole of the battery unit may be a positive pole, and the second pole of the battery unit may be a negative pole.

In this embodiment, the first electrode of the transistor may be a source, and the second electrode of the transistor is a drain, but of course, the first electrode of the battery cell may also be a drain, and the second electrode of the transistor is a source, and the control electrodes of the transistors are gates.

On the basis of any of the above embodiments, optionally, in an embodiment of the present application, as shown in fig. 5, the battery array further includes: a plurality of scanning signal lines 50, each scanning signal line 50 being electrically connected to a respective selection circuit 12 in one of the battery packs 10, the scanning signal lines 50 being configured to supply a scanning signal S1 to the selection circuits 12, the selection circuits 12 being electrically connected to the first control signal lines 31 and the second control signal lines 32 when the scanning signal S1 reaches an active level period.

In the present embodiment, the scan signal lines 50 correspond to the battery packs 10 one to one, one scan signal line 50 is electrically connected to each selection circuit 12 in one battery pack 10, and the scan signal S1 is provided to each selection circuit 12 in the battery pack 10, so that when the scan signal S1 reaches an active level period, each selection circuit 12 in the battery pack 10 is electrically connected to the corresponding first control signal line 31 and second control signal line 32, so as to adjust the serial-parallel connection relationship of the battery cells 11 in the battery pack 10 by using the first control signal D1 provided by the first control signal line 31 and the second control signal D2 provided by the second control signal line 32, thereby adjusting the output voltage of the battery pack 10. When the scanning signal S1 provided by one scanning signal line 50 reaches an active level period, each selection circuit 12 in the battery pack 10 corresponding to the scanning signal line 50 is electrically connected to the corresponding first control signal line 31 and second control signal line 32, so that the serial-parallel connection relationship of the plurality of battery cells 11 in the battery pack 10 can be adjusted, and the battery pack 10 can be regarded as being opened.

For example, as shown in fig. 5, each battery pack 10 includes 3 battery cells 11, the output voltage of each battery cell 11 is 3V, the scanning signal S1 controls one battery pack 10 to be turned on in one period, each selection circuit 12 is electrically connected to the corresponding first control signal line 31 and second control signal line 32 in the one battery pack 10, receives the first control signal D1 and second control signal D2, such that two battery cells 11 in the one battery pack 10 are connected in parallel and then connected in series to one battery cell 11, the output voltage of the one battery pack in the current period is 6V, and in another period, the scanning signal S1 may control another battery pack 10 to be turned on, each selection circuit 12 is electrically connected to the corresponding first control signal line 31 and second control signal line 32 in the other battery pack 10, receives the first control signal D1 and second control signal D2, such that three battery cells in the other battery pack 10 are connected in series, and the output voltage of the other battery pack in the current period is 9V.

In this embodiment, the scanning signal S1 is also a periodic square wave signal having a high level and a low level arranged according to a certain duration and sequence, and its active level period may be a high level period or a low level period, as the case may be.

Therefore, in the battery array provided in this embodiment, the battery pack 10 can be selected by the scanning signal S1 provided by each scanning signal line 50, and then the series-parallel connection relationship of the plurality of battery units 11 in the selected battery pack 10 is adjusted by the first control signal D1 provided by the first control signal line 31 in each group of control signal lines 30 and the second control signal D2 provided by the second control signal line 32 in each group of control signal lines 30, that is, the series-parallel connection relationship of the plurality of battery units 11 in different battery packs 10 can be different in different periods, so that different battery packs 10 can provide different output voltages in different periods, or part of the battery packs 10 are controlled to be turned on to control the capacity provided by the battery array, the larger the number of the battery packs 10 are turned on, the larger the total current of the battery packs after being connected in parallel is, and the larger the capacity provided by the battery array is.

In the present application, the selection method of the battery pack by the scanning signal S1 supplied to each scanning signal line 50 is not limited, and the following description will be given by way of example.

Optionally, in an embodiment of the present application, in a period of time, only one scanning signal S1 provided by one scanning signal line 50 is at an active level, and the scanning signals S1 provided by the other scanning signal lines 50 are at inactive levels, so that in the battery pack 10 corresponding to the scanning signal line 50 providing the active level scanning signal S1, each selection circuit 12 is electrically connected to the corresponding first control signal line 31 and second control signal line 32, so as to adjust the serial-parallel relationship of the multiple battery units 11 in the battery pack 10, and output a required voltage value.

Since the plurality of battery packs 10 are arranged along the first direction X to form a plurality of rows, optionally, in an embodiment of the present application, the scanning signal lines 50 may be scanned line by line, that is, along the first direction X, the scanning signals S1 received by the 1 st battery pack to the mth battery pack sequentially become an active level, so that the serial-parallel relationship of the plurality of battery cells in the 1 st battery pack to the mth battery pack is sequentially adjusted. However, this is not limited in this application, and optionally, in another embodiment of this application, scanning may also be performed according to a preset rule, for example, scanning the battery packs in odd rows line by line, or scanning the battery packs in even rows line by line; optionally, in another embodiment of the present application, the battery pack may also be scanned randomly, that is, the battery pack whose received scanning signal is at an active level is randomly changed, as the case may be.

Optionally, in another embodiment of the present application, in a period of time, the scan signal S1 provided by a part of the scan signal lines 50 is at an active level, and the scan signals S1 provided by the other scan signal lines 50 are at an inactive level, then in the battery pack 10 corresponding to the scan signal line 50 providing the active level scan signal S1, each selection circuit 12 is electrically connected to the corresponding first control signal line 31 and second control signal line 32, so as to adjust the serial-parallel relationship of the plurality of battery cells 11 in the battery pack 10, and output a required voltage value.

Similarly, the present application does not limit which battery packs are turned on by the scanning signal S1 in a time period, and the battery packs 10 that are turned on simultaneously in a time period may be randomly arranged or arranged according to a certain rule, as the case may be.

Alternatively, in another embodiment of the present application, during a period of time, all the scanning signals S1 provided by the scanning signal lines 50 may be at an active level, that is, all the battery packs 10 are turned on. It can be understood that the more the battery packs 10 are turned on by the scanning signal S1, the greater the number of battery packs 10 connected in parallel, the greater the output current of each battery pack 10 connected in parallel, and the greater the capacity of the battery array.

On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 6, the battery array further includes: a row scanning circuit 60, the row scanning circuit 60 being electrically connected to each scanning signal line 50, the row scanning circuit 60 being configured to supply a scanning signal S1 to each scanning signal line 50.

As can be seen, in the battery array provided in the present embodiment, the row scanning circuit 60 is provided, so as to control the scanning signal S1 provided by each scanning signal line 50, and further select each battery pack 10. However, the present application is not limited to whether the line scanning circuit 60 or the control circuit similar to the line scanning circuit 60 is disposed in the battery array to provide the scanning signal to each scanning signal line 50, and in other embodiments of the present application, the line scanning circuit 60 or the control circuit similar to the line scanning circuit 60 to provide the scanning signal S1 to each scanning signal line 50 may be disposed outside the battery array to provide the scanning signal S1 to each scanning signal line 50, as the case may be.

Alternatively, the line scan circuit 60 may be a GOA (Gate on Array) circuit or an integrated circuit chip.

As can be seen from the foregoing embodiments, the selection circuits 12 between two adjacent battery cells 11 in each battery pack 10 are arranged along the second direction Y, and optionally, in an embodiment of the present application, each scanning signal line 50 extends along the second direction Y, and the row scanning circuit 60 is located on the same side of each battery pack 10, that is, the extending direction of each scanning signal line 50 is the same as the arrangement direction of the plurality of selection circuits 12 in each battery pack 10, so that each scanning signal line 50 is reasonably arranged in the battery array, and has a shorter wiring and a smaller occupied area.

It should be noted that, in the present embodiment, the line scanning circuit 60 is located on the same side of each battery pack 10, but the present application is not limited thereto, and in other embodiments of the present application, a part of the line scanning circuit 60 may be located on one side of each battery pack 10, and another part of the line scanning circuit 60 is located on the other side of each battery pack 10, that is, the line scanning circuit 60 is located on two opposite sides of each battery pack 10, as the case may be.

In order to more clearly understand the selection of each battery pack by the scanning signals provided by the plurality of scanning signal lines in the present application, a specific circuit structure of the selection circuit is listed below.

Specifically, in one embodiment of the present application, as shown in fig. 7, in the battery pack 10, each battery unit 11 has a first pole and a second pole, two adjacent battery units are a first battery unit 111 and a second battery unit 112, respectively, and the selection circuit 12 between the two adjacent battery units includes:

a first transistor T1, a first pole of the first transistor T1 being electrically connected to the first pole of the first battery cell 111, and a second pole being electrically connected to the second pole of the second battery cell 112;

a second transistor T2, a first pole of the second transistor T2 being electrically connected to a second pole of the first battery cell 111, and the second pole being electrically connected to a second pole of the second battery cell 112;

a third transistor T3, a first pole of the third transistor T3 being electrically connected to the first pole of the first battery cell 111, and a second pole being electrically connected to the first pole of the second battery cell 112;

a fourth transistor T4, a first electrode of the fourth transistor T4 being electrically connected to the first control signal line 31, a second electrode thereof being electrically connected to the control electrode of the first transistor T1, and the control electrode thereof being electrically connected to the scanning signal line 50;

a fifth transistor T5, a first electrode of the fifth transistor T5 is electrically connected to the second control signal line 32, a second electrode is electrically connected to the control electrode of the second transistor T2 and the control electrode of the third transistor T3, and the control electrode is electrically connected to the scanning signal line 50

When the scan signal S1 reaches the active level period, both the fourth transistor T4 and the fifth transistor T5 are turned on.

In specific operation, when the scan signal S1 provided by the scan signal line 50 reaches an active level period, the fourth transistor T4 and the fifth transistor T5 are both turned on, and at this time, if the first control signal D1 provided by the first control signal line 31 is at an active level and the second control signal D2 provided by the second control signal line 32 is at an inactive level, the first transistor T1 is turned on, the second transistor T2 and the third transistor T3 are both turned off, as shown by solid arrows in fig. 7, a first pole of the first battery unit 111 is electrically connected through the turned-on first transistor T1 and a second pole of the second battery unit 112, that is, the first battery unit 111 and the second battery unit 112 are connected in series through the turned-on first transistor T1;

if the second control signal D2 provided by the second control signal line 32 is at an active level and the first control signal D1 provided by the first control signal line 31 is at an inactive level, the second transistor T2 and the third transistor T3 are both turned on, the first transistor T1 is turned off, as shown by a dotted arrow in fig. 7, the first pole of the first battery unit 111 is electrically connected to the first pole of the second battery unit 112 through the turned-on third transistor T3, and the second pole of the first battery unit 111 is electrically connected to the second pole of the second battery unit 112 through the turned-on second transistor T2, that is, the first battery unit 111 and the second battery unit 112 are electrically connected in parallel through the turned-on second transistor T2 and the turned-on third transistor T3.

In this embodiment, the first pole of the battery unit may be a positive pole, and the second pole of the battery unit may be a negative pole.

In this embodiment, the first pole of the transistor may be a source, and the second pole of the transistor is a drain, but of course, the first pole of the battery cell may also be a drain, and the second pole of the transistor is a source, and the control electrodes of the transistors are gates.

Note that each Transistor in the selection circuit 12 is a Thin Film Transistor (TFT), and may be manufactured by a panel process such as an a-Si process, an IGZO (Indium Gallium nitride) process, or an LTPS (Low Temperature Poly-Silicon) process, and the control signal line 30 and the scan signal line 50 may be manufactured at the same time.

On the basis of the selection circuits shown in fig. 4 and fig. 7, optionally, in an embodiment of the present application, the first transistor T1 is a first type transistor, the second transistor T2 and the third transistor T3 are both second type transistors, and polarities of the first type transistor and the second type transistor are opposite.

In this embodiment, the polarities of the first type transistor and the second type transistor are opposite, that is, when the first transistor T1 is an N-type transistor, the second transistor T2 and the third transistor T3 are both P-type transistors, whereas when the first transistor T1 is a P-type transistor, the second transistor T2 and the third transistor T3 are both N-type transistors, and then the active levels of the first control signal D1 and the second control signal D2 are also opposite.

Specifically, for example, the first transistor T1 is a P-type transistor, and the second transistor T2 and the third transistor T2 are both N-type transistors, when the first control signal D1 is at a low level, the active level period of the first control signal D1 is defined, at this time, the first transistor T1 is turned on, the first battery unit 111 and the second battery unit 112 are connected in series, the second control signal D2 is also at a low level, and the inactive level period of the second control signal D2 is defined, so that both the second transistor T2 and the third transistor T3 are turned off; when the second control signal D2 is at a high level, which is an active level period of the second control signal D2, at this time, the second transistor T2 and the third transistor T3 are turned on, the first battery cell 111 and the second battery cell 112 are connected in parallel, the first control signal is also at a high level, which is a non-active level period of the first control signal D1, and the first transistor T1 is turned off.

Taking the first transistor T1 as an N-type transistor, and the second transistor T2 and the third transistor T3 as P-type transistors as an example, when the first control signal D1 is at a high level, the first control signal D1 is at an active level period of the first control signal D1, at this time, the first transistor T1 is turned on, the first battery unit 111 and the second battery unit 112 are connected in series, the second control signal D2 is also at a high level, and the second control signal D2 is at a non-active level period of the second control signal D2, so that the second transistor T2 and the third transistor T3 are both turned off; when the second control signal D2 is at a low level, it is an active level period of the second control signal D2, at this time, the second transistor T2 and the third transistor T3 are turned on, the first battery unit 111 and the second battery unit 112 are connected in parallel, the first control signal D1 is also at a low level, and is a non-active level period of the first control signal D1, so that the first transistor T1 is turned off.

Since the active level of the first control signal D1 and the active level of the second control signal D2 are opposite, and the active level period of the first control signal D1 and the active level period of the second control signal D2 do not overlap, optionally, in an embodiment of the present application, as shown in fig. 8, the first control signal line 31 and the second control signal line 32 are the same control signal line, and the first control signal D1 and the second control signal D2 are the same control signal.

As shown in fig. 8, in the present embodiment, the first transistor T1, the second transistor T2 and the third transistor T3 are electrically connected to a control signal line 31/32, when the control signal D1/D2 inputted from the control signal line 31/32 is at a first level, the first transistor T1 is turned on, the first battery unit 111 and the second battery unit 112 are connected in series, and at this time, the second transistor T2 and the third transistor T3 are turned off; when the control signal D1/D2 inputted from the control signal line 31/32 is at the second level, the second transistor T2 and the third transistor T3 are turned on, and the first battery unit 111 and the second battery unit 112 are connected in parallel, and at this time, the first transistor T1 is turned off.

It is understood that, when the first transistor T1 is a P-type transistor, the second transistor T2 and the third transistor T3 are both N-type transistors, the first level is a low level, and the second level is a high level; when the first transistor T1 is an N-type transistor, the second transistor T2 and the third transistor T3 are both P-type transistors, the first level is a high level, and the second level is a low level.

Therefore, in the battery array provided by the embodiment, the series-parallel selection circuit adopts a complementary design, so that the first control signal line 31 and the second control signal line 32 are the same control signal line, the number of wires can be greatly reduced, and the cost is saved.

It should be noted that, currently, the thin film transistors manufactured by the a-Si process and the IGZO process are only of one type, for example, the thin film transistors manufactured by the a-Si process only have N-type thin film transistors or thin film transistors of intrinsic bias N-type, and therefore, each transistor, particularly the first transistor T1, the second transistor T2, and the third transistor T3, in the selection circuit 12 are all of the same type, and therefore, in order to make the first transistor T1, the second transistor T2, and the third transistor T3 not be turned on at the same time, it is necessary to include two control signal lines in one set of control signal lines, one control signal line 31 is electrically connected to the first transistor, and the other control signal line 32 is electrically connected to the second transistor T2 and the third transistor T3, so that the first control signal D1 provided to the first transistor T1 and the second control signal D2 provided to the second transistor T2 and the third transistor T3 are not turned on at the same time, so that the first transistor T1, the second transistor T2, and the third transistor T3 are not turned on at the same time.

At present, the thin film transistor manufactured by the LTPS process may be of a P-type and an N-type, in the selection circuit 12, the first transistor T1 may be a first-type transistor, the second transistor T2 and the third transistor T3 may be both second-type transistors, and polarities of the first-type transistor and the second-type transistor are opposite, further, the first control signal line 31 and the second control signal line 32 may be the same control signal line, and the first control signal D1 and the second control signal D2 may be the same control signal.

Therefore, optionally, in an embodiment of the present application, each transistor in the selection circuit 12 is an LTPS transistor, so that the first transistor T1 is a first type transistor, the second transistor T2 and the third transistor T3 are both second type transistors, and polarities of the first type transistor and the second type transistor are opposite, further, the first control signal line 31 and the second control signal line 32 are the same control signal line, and the first control signal D1 and the second control signal D2 are the same control signal line. However, the present application is not limited thereto, and if the first transistor, the second transistor, and the third transistor of different types can be prepared by using an a-Si process, an IGZO process, or other panel processes, the present application should also be within the scope of the present application, that is, the present application does not limit the preparation process of the transistors.

In the above embodiment, the electrical connection relationship between each transistor in the selection circuit and the battery unit, the control signal line and the scanning signal line is described, and in the selection circuit, each transistor has a gate, a source and a drain, the battery unit has a positive electrode and a negative electrode, the control signal line and the scanning signal line are also metal wires, and the arrangement of each metal layer in the battery array is further described below.

Optionally, in an embodiment of the present application, as shown in fig. 9 and fig. 10, fig. 9 is a schematic layout diagram of an entirety composed of a battery unit and a selection circuit electrically connected to the battery unit in the battery array provided in this embodiment, fig. 10 further is a schematic cross-sectional diagram of a position of an AA' line in fig. 9, where the battery array includes a first metal layer M1, a second metal layer M2, and a third metal layer M3 that are disposed in different layers;

the control electrode g of each transistor of the selection circuit 12 is located in the first metal layer M1, and the first electrode d1 and the second electrode d2 of each transistor of the selection circuit 12 are located in the second metal layer M2;

the first pole c1 and the second pole c2 of the battery unit 11 are located in the third metal layer M3, a through hole k1 is provided between the second metal layer M2 and the third metal layer M3, the first pole c1 of the battery unit 11 is electrically connected to the first pole d1 or the second pole d2 of the corresponding transistor in the selection circuit 12 through the through hole k1, and the second pole c2 of the battery unit 11 is electrically connected to the first pole d1 or the second pole d2 of the corresponding transistor in the selection circuit 12 through the through hole k 1.

In this embodiment, the first pole c1 and the second pole c2 of the battery unit 11 are located in the third metal layer M3, the first pole d1 and the second pole d2 of each transistor in the selection circuit 12 are located in the second metal layer M2, the second metal layer M2 and the third metal layer M3 are different layers, and a through hole k1 is provided between the second metal layer M2 and the third metal layer M3, so that the first pole c1 of the battery unit 11 is electrically connected to the first pole d1 or the second pole d2 of the corresponding transistor in the selection circuit 12 through the through hole k1, and the second pole c2 of the battery unit 11 is electrically connected to the first pole d1 or the second pole d2 of the corresponding transistor in the selection circuit 12 through the through hole k1, thereby electrically connecting the battery unit 11 and the corresponding transistor in the selection circuit 12.

In the present embodiment, the first and second poles c1 and c2 of the battery cell may be Mo or ITO.

In the present embodiment, the first metal layer M1, the second metal layer M2 and the third metal layer M3 are isolated from each other by an insulating layer, that is, the empty area not marked in fig. 10 is an insulating layer, and the insulating layer may be a SiNx layer. In fig. 10, b denotes an active layer.

The arrangement order of the first metal layer M1, the second metal layer M2, and the third metal layer M3 is not limited in this application. Optionally, in an embodiment of the present application, as shown in fig. 10, the first metal layer M1, the second metal layer M2, and the third metal layer M3 are sequentially arranged along a direction away from the substrate 100, that is, in the embodiment, the transistor in the selection circuit 12 is a bottom gate structure, and may be formed by a conventional panel process-a-Si process.

The metal layer on which the control signal line 30 is located is not limited in this application. Considering that the control signal line 30 is electrically connected to the control electrodes (i.e., the gates g) of the corresponding transistors (e.g., the first transistor T1, the second transistor T2, and the third transistor T3) in the selection circuit 12, optionally, in an embodiment of the present application, as shown in fig. 9 and 10, the first control signal line 31 and the second control signal line 32 are both located in the first metal layer M1, that is, in the embodiment, the first control signal line 31 and the second control signal line 32 are located in the same metal layer M1 as the control electrodes g of the transistors in the selection circuit 12, so that the first control signal line 31 and the second control signal line 32 are electrically connected to the control electrodes g of the corresponding transistors in the selection circuit 12. Optionally, in other embodiments of the present application, the first control signal line 31 and the second control signal line 32 may not be located in the first metal layer M1, that is, not located in the same metal layer as the control electrode g of each transistor in the selection circuit 12, at this time, a through hole needs to be disposed between the metal layer where the first control signal line 31 and the second control signal line 32 are located and the first metal layer M1, so that the first control signal line 31 and the second control signal line 32 are electrically connected to the control electrode g of the corresponding transistor in the selection circuit 12 through the through hole between the metal layer where the first control signal line 31 and the second control signal line 32 are located and the first metal layer M1.

Similarly, the metal layer on which the scan signal line 50 is disposed is not limited in this application. Considering that the scan signal line 50 is electrically connected to the control electrodes (i.e., the gates g) of the corresponding transistors (the fourth transistor T4 and the fifth transistor T5) in the selection circuit 12, optionally, in an embodiment of the present application, the scan signal line 50 is located in the first metal layer M1, that is, in the present embodiment, the scan signal line 50 and the control electrode g of each transistor in the selection circuit 12 are located in the same metal layer M1, so that the scan signal line 50 is electrically connected to the control electrode g of the corresponding transistor in the selection circuit 12. Optionally, in other embodiments of the present application, the scanning signal line 50 may not be located in the first metal layer M1, that is, not located in the same metal layer as the control electrode g of each transistor in the selection circuit 12, at this time, a through hole needs to be provided between the metal layer where the scanning signal line 50 is located and the first metal layer M1, so that the scanning signal line 50 is electrically connected to the control electrode g of the corresponding transistor in the selection circuit 12 through the through hole between the metal layer where the scanning signal line 50 is located and the first metal layer M1.

On the basis of any of the above embodiments, optionally, in an embodiment of the present application, the battery unit 11 is prepared by a panel process for preparing each thin film transistor TFT in the selection circuit 12, that is, the preparation process of each thin film transistor in the selection circuit 12 is the same as that of the battery unit 11, and the battery unit prepared by the TFT panel process is a thin film battery unit, which can be applied to a flexible substrate to form a flexible battery array, unlike a conventional battery, such as a pouch battery, in which a sub-battery is in a column shape.

Alternatively, in another embodiment of the present application, each battery unit 11 may also be prepared independently of a TFT panel process, that is, each thin film transistor and each signal line of the selection circuit are prepared on the substrate by using the TFT panel process, a plurality of battery units 11 are prepared by using a single process, and then the prepared battery units 11 are electrically connected to the substrate 100 carrying the plurality of selection circuits 12 and the plurality of signal lines by welding or attaching.

On the basis of any of the above embodiments, optionally, in an embodiment of the present application, as shown in fig. 2, the battery array further includes: the input/output circuit 20 is electrically connected to the input/output circuit 20 after the battery packs 10 are connected in parallel, and causes the input/output circuit 20 to output voltages after the battery packs 10 are connected in parallel.

Optionally, the input/output circuit 20 includes at least one of an overcurrent protection function, an overtemperature protection function, and a battery-to-battery stored charge balancing function.

The embodiment of the application further provides a power supply system, and the power supply system comprises the battery array provided by any one of the embodiments.

Since the battery array has been described in detail in the above embodiments, it is not described herein again.

To sum up, the battery array and the power supply system provided by the embodiment of the application include a substrate and a plurality of battery packs located on the substrate and connected in parallel, each battery pack includes a plurality of battery units, thereby realizing the arrayed arrangement of the battery units, and in each battery pack, a selection circuit is arranged between every two adjacent battery units, the selection circuit enables the two adjacent battery units to be connected in series when the received first control signal is in an effective level period, the two adjacent battery units are connected in parallel when the received second control signal is in an effective battery period, the effective level period of the first control signal and the effective level period of the second control signal are not overlapped, thereby realizing the change of the output voltage of each battery pack by changing the series and parallel relation of each battery unit in each battery pack, and realizing the change of the output voltage of the battery array by the parallel connection of each battery pack, so as to match with the portable electronic devices and sensors with different working voltages, without setting a complex power supply management system, reducing the volume and complexity of the thin film battery system, and being beneficial to the miniaturization of the thin film battery system.

All parts in the specification are described in a mode of combining parallel and progressive, each part is mainly described to be different from other parts, and the same and similar parts among all parts can be referred to each other.

In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (19)

1. A battery array, comprising:

a substrate;

the battery pack comprises a plurality of battery units, each battery unit comprises a plurality of battery units, a selection circuit is arranged between every two adjacent battery units in each battery pack, the selection circuit receives a first control signal and a second control signal, when the first control signal reaches an effective level time period, the selection circuit enables the two adjacent battery units to be connected in series, when the second control signal reaches the effective level time period, the selection circuit enables the two adjacent battery units to be connected in parallel, and the effective level time period of the first control signal and the effective level time period of the second control signal are not overlapped.

2. The battery array of claim 1, wherein the plurality of battery packs are arranged in a first direction, the plurality of battery cells in each battery pack are arranged in a second direction, and the selection circuit between two adjacent battery cells in each battery pack is arranged in the first direction, and the first direction and the second direction intersect;

the battery array further includes: the selection circuit between two adjacent battery units in each battery pack is electrically connected with one group of control signal lines together;

each set of the control signal lines includes a first control signal line configured to provide the first control signal to the selection circuit and a second control signal line configured to provide the second control signal to the selection circuit.

3. The battery array of claim 2, further comprising: a column selection circuit electrically connected to the control signal lines of the respective groups, the column selection circuit configured to supply the first control signal to a first control signal line of the control signal lines of the respective groups and to supply the second control signal to a second control signal line of the control signal lines of the respective groups.

4. The battery array of claim 2, wherein the first control signal line and the second control signal line each extend along the first direction.

5. The battery array of claim 2, wherein in the battery pack, each battery cell has a first pole and a second pole, two adjacent battery cells are a first battery cell and a second battery cell, respectively, and the selection circuit between two adjacent battery cells comprises:

a first transistor, a first pole of which is electrically connected with the first pole of the first battery unit, a second pole of which is electrically connected with the second pole of the second battery unit, and a control pole of which is electrically connected with the first control signal line;

a first pole of the second transistor is electrically connected with a second pole of the first battery unit, the second pole of the second transistor is electrically connected with a second pole of the second battery unit, and a control pole of the second transistor is electrically connected with the second control signal line;

and a third transistor having a first electrode electrically connected to the first electrode of the first battery cell, a second electrode electrically connected to the first electrode of the second battery cell, and a control electrode electrically connected to the second control signal line.

6. The battery array of claim 2, further comprising: a plurality of scan signal lines each electrically connected to a respective selection circuit in one of the battery packs, the scan signal lines configured to provide a scan signal to the selection circuits, the selection circuits electrically connected to the first control signal lines and the second control signal lines when the scan signal reaches an active level period.

7. The battery array of claim 6, further comprising: a row scanning circuit electrically connected to each of the scanning signal lines, the row scanning circuit configured to supply the scanning signal to each of the scanning signal lines.

8. The battery array of claim 7, wherein each of the scanning signal lines extends along the second direction, and the row scanning circuit is located on the same side of each of the battery packs.

9. The battery array of claim 6, wherein in the battery pack, each battery cell has a first pole and a second pole, two adjacent battery cells are a first battery cell and a second battery cell, respectively, and the selection circuit between two adjacent battery cells comprises:

a first transistor having a first pole electrically connected to the first pole of the first battery cell and a second pole electrically connected to the second pole of the second battery cell;

a second transistor, a first pole of the second transistor being electrically connected to a second pole of the first battery cell, the second pole being electrically connected to a second pole of the second battery cell;

a third transistor having a first electrode electrically connected to the first electrode of the first battery cell and a second electrode electrically connected to the first electrode of the second battery cell;

a fourth transistor having a first electrode electrically connected to the first control signal line, a second electrode electrically connected to a control electrode of the first transistor, and a control electrode electrically connected to the scanning signal line;

a fifth transistor having a first electrode electrically connected to the second control signal line, a second electrode electrically connected to a control electrode of the second transistor and a control electrode of the third transistor, and a control electrode electrically connected to the scanning signal line;

when the scan signal reaches an active level period, both the fourth transistor and the fifth transistor are turned on.

10. The battery array of claim 5 or 9, wherein the first transistor is a first type transistor, and the second transistor and the third transistor are both a second type transistor, and wherein the first type transistor and the second type transistor have opposite polarities.

11. The battery array of claim 10, wherein the first control signal line and the second control signal line are the same control signal line, and the first control signal and the second control signal are the same control signal.

12. The battery array of claim 10, wherein each transistor in the selection circuit is an LTPS transistor.

13. The battery array according to claim 5 or 9, wherein the battery array comprises a first metal layer, a second metal layer and a third metal layer which are arranged in different layers;

the control electrode of each transistor of the selection circuit is positioned in the first metal layer, and the first electrode and the second electrode of each transistor of the selection circuit are positioned in the second metal layer;

the first pole and the second pole of the battery unit are located on the third metal layer, a through hole is formed between the second metal layer and the third metal layer, the first pole of the battery unit is electrically connected with the first pole or the second pole of the corresponding transistor in the selection circuit through the through hole, and the second pole of the battery unit is electrically connected with the first pole or the second pole of the corresponding transistor in the selection circuit through the through hole.

14. The battery array of claim 13, wherein the first metal layer, the second metal layer, and the third metal layer are arranged in sequence in a direction away from the substrate.

15. The battery array of claim 13, wherein the first control signal line and the second control signal line are both located in the first metal layer.

16. The battery array of claim 1, wherein the battery cells are fabricated by a TFT panel process.

17. The battery array of claim 1, further comprising: and the input and output circuit is electrically connected with the battery packs after the battery packs are connected in parallel, so that the input and output circuit outputs the voltages of the battery packs after the battery packs are connected in parallel.

18. The battery array of claim 17, wherein the input/output circuitry comprises at least one of over-current protection, over-temperature protection, and inter-cell charge balancing.

19. A power supply system comprising the battery array of any one of claims 1-18.

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