CN115732555A

CN115732555A - Nitride semiconductor device, interconnection structure and manufacturing method thereof

Info

Publication number: CN115732555A
Application number: CN202211330574.6A
Authority: CN
Inventors: 陈邦星; 曹凯; 张雷
Original assignee: Innoscience Zhuhai Technology Co Ltd
Current assignee: Innoscience Zhuhai Technology Co Ltd
Priority date: 2022-10-27
Filing date: 2022-10-27
Publication date: 2023-03-03
Anticipated expiration: 2042-10-27
Also published as: CN115732555B

Abstract

The nitride semiconductor device includes a nitride epitaxial stack, at least one electrode, an insulating layer, a conductive via, a first metal layer, a second metal layer, and a redistribution layer. At least one electrode is disposed on the nitride epitaxial stack. The insulating layer covers the electrode and the nitride epitaxial lamination. The conductive via is disposed on the electrode and extends within the insulating layer. The first metal layer and the second metal layer are arranged on the insulating layer. The first metal layer is positioned above the conductive through hole and electrically connected with the electrode through the conductive through hole, and the first metal layer is separated from the second metal layer. The reconfiguration line layer is arranged between the first metal layer and the second metal layer and is connected with the first metal layer and the second metal layer, wherein the reconfiguration line layer is provided with a first end part and a second end part which are opposite, the first end part covers the first metal layer, the second end part covers the second metal layer, and the material of the reconfiguration line layer is different from the material of the first metal layer and the second metal layer.

Description

Nitride semiconductor device, interconnection structure and manufacturing method thereof

Technical Field

The present invention relates generally to semiconductor devices and interconnect structures for use in such semiconductor devices. More particularly, the present invention relates to an interconnect structure which avoids warpage due to thermal expansion, and which is suitable for connecting electrodes of a semiconductor structure and a connection structure, thereby improving the reliability of a semiconductor device.

Background

In recent years, intensive research into High Electron Mobility Transistors (HEMTs) has become widespread, particularly in high power switching and high frequency applications. The HEMT utilizes a heterojunction interface between two different band gap materials to form a quasi-quantum well structure, can accommodate a two-dimensional electron gas (2 DEG) region, and meets the requirements of high-power/frequency devices. Examples of devices having heterostructures other than HEMTs include Heterojunction Bipolar Transistors (HBTs), heterojunction Field Effect Transistors (HFETs), and modulation-doped FETs (MODFETs).

Disclosure of Invention

According to an aspect of the present invention, there is provided a nitride semiconductor device. The nitride semiconductor device includes a nitride epitaxial stack, at least one electrode, an insulating layer, a conductive via, a first metal layer, a second metal layer, and a redistribution layer. At least one electrode is disposed on the nitride epitaxial stack. The insulating layer covers the electrode and the nitride epitaxial lamination. The conductive through hole is arranged on the electrode. The first metal layer and the second metal layer are arranged on the insulating layer. The first metal layer is located above the conductive through hole and electrically connected with the electrode through the conductive through hole, and the first metal layer is separated from the second metal layer. The reconfiguration line layer is arranged between the first metal layer and the second metal layer and is connected with the first metal layer and the second metal layer, wherein the reconfiguration line layer is provided with a first end part and a second end part which are opposite, the first end part covers the first metal layer, the second end part covers the second metal layer, and the material of the reconfiguration line layer is different from the material of the first metal layer and the second metal layer.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device. The method comprises the following steps. A nitride epitaxial stack is formed. At least one electrode is formed on the nitride epitaxial stack. An insulating layer is formed to cover the at least one electrode and the nitride epitaxial stack. And forming a conductive through hole in the insulating layer so as to be in contact with at least one electrode. A first metal layer is formed on the insulating layer and the conductive via. A second metal layer is formed on the insulating layer and separated from the first metal layer. Forming a redistribution layer between the first metal layer and the second metal layer to electrically connect the first metal layer and the second metal layer through the redistribution layer, wherein the material of the redistribution layer is different from the materials of the first metal layer and the second metal layer.

According to one aspect of the present invention, an interconnect structure is provided on a semiconductor structure. The interconnect structure includes an insulating layer, a first conductive layer, a second conductive layer, a redistribution line layer, and a connection structure. The insulating layer covers the semiconductor structure and has a plurality of portions with different thicknesses. The first conductive layer is disposed on the thin portion of the insulating layer and connected to the electrode of the semiconductor structure. The second conductive layer is disposed on a portion of the insulating layer having a thicker thickness. The redistribution line layer extends between the first conductive layer and the second conductive layer. The connection structure is arranged on the second metal layer, and the reconfiguration line layer and the connection structure are not overlapped in the longitudinal direction.

According to the above configuration, in the embodiment of the present invention, the nitride semiconductor device is provided with two metal layers with the redistribution line layer interposed therebetween. The redistribution layer covers a portion of each of the two metal layers and the two metal layers are connected to each other by the redistribution layer. In other words, the redistribution layer may act as a bridge structure between two metal layers. With this configuration, two opposite edges of the redistribution layer are respectively within the respective extension ranges of the two metal layers, so that the thermal stress warpage phenomenon caused by the excessive area thereof can be avoided, and the nitride semiconductor device can have good reliability.

Drawings

Aspects of this disclosure can be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

fig. 2A, 2B, 2C, 2D, 2E, 2F depict different stage diagrams of a method for manufacturing a semiconductor device; and

fig. 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention.

Detailed Description

The same reference indicators will be used throughout the drawings and the detailed description to refer to the same or like parts. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

In the spatial description, terms such as "upper," "lower," "above," "left," "right," "below," "top," "bottom," "longitudinal," "lateral," "side," "upper," "lower," "upper," "lower," and the like are defined with respect to a particular element or plane of a group of elements as oriented in the respective figures. It will be appreciated that the spatial description used herein is for illustrative purposes only, and that the structures described herein may be embodied in any suitable manner or arrangement within space, provided that the advantages of embodiments of the present disclosure are not necessarily so configured or distorted.

Further, it is to be noted that for the actual shape of the various structures depicted as approximately rectangular, in an actual device it may be curved, have rounded edges, or have some non-uniform thickness, etc., due to the manufacturing conditions of the device. In the present disclosure, the straight line and the right angle are only used for conveniently representing the layer body and the technical features.

In the following description, a semiconductor device, a method of manufacturing the same, and the like are listed as preferred examples. Those skilled in the art will appreciate that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the present invention. Specific details may be omitted in order to avoid obscuring the invention; this summary is, however, intended to enable those skilled in the art to practice the teachings herein without undue experimentation.

Fig. 1 is a cross-sectional view of a semiconductor device 1A according to some embodiments of the present invention. Referring to fig. 1, a semiconductor device 1A includes a substrate 10, a nitride epitaxial stack ES (including a plurality of nitride semiconductor layers 12, 14),

electrodes

20, 22,

conductive vias

24, 26, metal layers M1, M2, a doped nitride semiconductor layer 32, a gate electrode 34, an insulating layer 40, a dielectric layer 60, an encapsulation material layer 70, and a connection structure CS. The following paragraphs will describe each component and the configuration relationship among the components in detail.

The substrate 10 may be a semiconductor substrate. Exemplary materials for substrate 10 may include, for example, but are not limited to, silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), p-doped silicon, n-doped silicon, sapphire, a semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)), or other suitable semiconductor materials. In some embodiments, the substrate 10 may include, for example, but not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound). In other embodiments, the substrate 10 may include, for example, but not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epitaxiy) layers, or combinations thereof.

In some embodiments, the semiconductor device 1A includes a buffer layer (not shown). A buffer layer may be disposed over the substrate 10. The buffer layer may be configured to reduce lattice and thermal mismatch (lattice and thermal mismatches) between the substrate 10 and a layer formed on the substrate 10, such as the nitride semiconductor layer 12, thereby reducing defects due to the mismatch/difference. The buffer layer 104 may include a III-V compound. The III-V compounds may include, for example, but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Thus, exemplary materials of the buffer layer may further include, for example, but not limited to, gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), or a combination thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown). A nucleation layer may be formed between the substrate 10 and the buffer layer. The nucleation layer may be configured to act as a transition layer (transition) to accommodate mismatches/differences between the substrate 10 and the group III-nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, but are not limited to, aluminum nitride (AlN) or any alloy thereof.

The nitride semiconductor layer 12 is disposed on/over/on the substrate 10. The nitride semiconductor layer 14 is disposed on/over/on the nitride semiconductor layer 12. Exemplary materials for the nitride semiconductor layer 12 may include, but are not limited to, nitrides or III-V compounds, such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), in _x Al _y Ga _(1–x–y) N (wherein x + y is less than or equal to 1) and Al _y Ga _(1–y) N (wherein y is less than or equal to 1). Exemplary materials for nitride semiconductor layer 14 may include, but are not limited to, nitrides or III-V compounds, such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), in _x Al _y Ga _(1–x–y) N (wherein x + y is less than or equal to 1) and Al _y Ga _(1–y) N (wherein y is less than or equal to 1).

Exemplary materials for the nitride semiconductor layers 12 and 14 may be selected such that the nitride semiconductor layer 14 has a band gap (i.e., a forbidden band width) greater than that of the nitride semiconductor layer 12, which makes electron affinities different therebetween, and forms a heterojunction (heterojunction) therebetween. For example, when the nitride semiconductor layer 12 is an undoped gallium nitride layer (having a band gap of about 3.4 ev), the nitride semiconductor layer 14 may be selected as an aluminum gallium nitride layer (having a band gap of about 4.0 ev). Therefore, the nitride semiconductor layers 12 and 14 can function as a channel layer (channel layer) and an energy barrier layer (barrier layer), respectively. The semiconductor device 1A may thus include at least one gallium nitride-based (GaN-based) High Electron Mobility Transistor (HEMT) because a triangular well potential is generated at the junction interface between the channel layer and the energy barrier layer, causing electrons to accumulate in the triangular well potential, thereby creating a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction.

The

electrodes

20, 22 are disposed on/over/on the nitride semiconductor layer 14. The

electrodes

20, 22 are in contact with the nitride semiconductor layer 14. In some embodiments, electrode 20 may serve as a source (source) and electrode 22 may serve as a drain (drain). In some embodiments, electrode 20 may serve as a drain and electrode 22 may serve as a source. The use of the electrodes depends on the requirements of the semiconductor device.

In some embodiments, each

electrode

20, 22 may comprise, for example, but not limited to, a metal, an alloy, a doped semiconductor material (e.g., doped crystalline silicon), a compound such as a silicide and nitride, other conductive material, or combinations thereof. Exemplary materials for each

electrode

20, 22 may include, for example, but are not limited to, titanium (Ti), aluminum silicon (AlSi), titanium nitride (TiN), or combinations thereof. Each

electrode

20, 22 may be a single layer or multiple layers of the same or different composition. In some embodiments,

electrodes

20, 22 form ohmic contacts with nitride semiconductor layer 14. Ohmic contact may be achieved by applying titanium (Ti), aluminum (Al), or other suitable materials to the

electrodes

20, 22. In some embodiments, each of the

electrodes

20, 22 is comprised of at least one conformal layer and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials for the conformal layer are, for example, but not limited to, titanium (Ti), tantalum (Ta), titanium nitride (TiN), aluminum (Al), gold (Au), aluminum silicon (AlSi), nickel (Ni), platinum (Pt), or combinations thereof. Exemplary materials for the conductive filler may include, for example, but are not limited to, aluminum silicon (AlSi), aluminum copper (AlCu), or combinations thereof.

Conductive vias

24, 26 are disposed on/over/on

electrodes

22, 20, respectively.

Conductive vias

24, 26 contact the top surfaces of

electrodes

22, 20, respectively, such that

conductive vias

24, 26 are electrically connected/coupled to

electrodes

22, 20, respectively. In the present embodiment, the

conductive vias

24, 26 may comprise a conductive material.

The doped nitride semiconductor layer 32 is disposed on/over/on the nitride semiconductor layer 14. The doped nitride semiconductor layer 32 is in contact with the nitride semiconductor layer 14. The profile of the doped nitride semiconductor layer 32 is, for example, a rectangular profile. The gate electrode 34 is disposed on/over/on the doped nitride semiconductor layer 32. The gate electrode 34 contacts the doped nitride semiconductor layer 32. The profile of the gate 34 is, for example, a rectangular profile. In some embodiments, the profile of the gate 34 may be a trapezoidal or other suitably shaped profile. The width of the gate electrode 34 is smaller than the width of the doped nitride semiconductor layer 32. In some embodiments, the width of the gate electrode 34 is substantially the same as the width of the doped nitride semiconductor layer 32. A gate electrode 34 and a doped nitride semiconductor layer 32 are disposed between the

electrodes

20, 22.

In the exemplary illustration of fig. 1, the semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate 34 is at approximately zero bias. Specifically, the doped nitride semiconductor layer 32 may form at least one p-n junction with the nitride semiconductor layer 14 to deplete the 2DEG region such that a region corresponding to the 2DEG region at a position below the gate electrode 34 has different characteristics (e.g., different electron concentration) from the remaining region of the 2DEG region and thus is blocked.

Due to this mechanism, the semiconductor device 1A has a normally-off characteristic. In other words, when the gate electrode 34 is not applied with a voltage or a voltage applied to the gate electrode 34 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer (inversion layer) under the gate electrode 34), a block of the 2DEG region under the gate electrode 34 is blocked, and thus no current flows through this block.

In some embodiments, the doped nitride semiconductor layer 32 may be omitted such that the semiconductor device 1A is a depletion-mode device (depletion-mode device), which represents that the semiconductor device 1A is in a normally-on state at zero gate-source voltage (zero-source voltage).

The doped nitride semiconductor layer 32 may be a p-type doped III-V semiconductor layer. Exemplary materials of doped nitride semiconductor layer 32 may include, for example, but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type gallium nitride (p-GaN), p-type aluminum gallium nitride (p-AlGaN), p-type indium nitride (p-InGaN), p-type aluminum indium nitride (p-AlInN), p-type indium gallium nitride (p-InGaN), p-type aluminum indium gallium nitride (p-AlInGaN), or combinations thereof. In some embodiments, the p-type doping material is achieved by using p-type impurities, such as beryllium (Be), (Zn), cadmium (Cd), and magnesium (Mg). In some embodiments, nitride semiconductor layer 12 includes undoped gallium nitride (GaN), nitride semiconductor layer 14 includes aluminum gallium nitride (AlGaN), and doped nitride semiconductor layer 32 is a p-type gallium nitride layer that can bend upward the band structure located thereunder and deplete a corresponding region of the 2DEG region, thereby placing semiconductor device 1A in an off state.

Exemplary materials for gate 34 may include metals or metal compounds. The gate electrode 34 may be formed as a single layer or a plurality of layers having the same or different compositions. Exemplary materials of the metal or metal compound may include, for example, but are not limited to, tungsten (W), gold (Au), platinum (Pd), titanium (Ti), thallium (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), thallium nitride (TaN), a metal alloy or compound thereof, or other metal compounds.

In a general semiconductor device, a wiring layer is usually disposed inside the device to connect electrodes with an external electronic device. However, depending on the design of the device, the horizontal distance between the external contact and the electrode may be too large, and the wiring layer may need to extend across the region between the two, resulting in an excessively large area of the wiring layer. During the operation of the device, the expansion and warpage of the circuit layer with an excessively large area caused by heating can cause the failure of the chip, thereby reducing the reliability of the semiconductor device.

Embodiments of the present invention provide a new structure to solve at least the above problems.

Embodiments of the present invention provide an interconnect structure for a semiconductor device, wherein the interconnect structure is adapted to be connected to electrode 20 (or electrode 22) and to connection structure CS. In detail, the interconnect structure includes a dielectric layer 40 (or insulating layer), metal layers M1 and M2, and a redistribution layer RDL. The arrangement between the above components is described in detail in the following paragraphs.

The dielectric layer 40 includes two portions, specifically a bottom portion 42 and a top portion 44. The bottom portion 42 is located below the top portion 44. Bottom portion 42 is disposed on/above/over nitride semiconductor layer 14. The bottom portion 42 covers the

electrodes

20, 22, the doped nitride semiconductor layer 32, the gate electrode 34, and the nitride semiconductor layer 14 of the nitride epitaxial stack ES, and provides these component protection functions.

Conductive vias

24, 26 extend through bottom portion 42 to electrically connect with

electrodes

22, 20, respectively.

The top portion 44 of the dielectric layer 40 has a mesa 442 and recesses 444 on both sides thereof, the recesses 444 extending from both sides of the mesa 442. In the top portion 44, the top surface TS2 of the land 442 is higher than the top surface TS3 of the recess 444. The top surface TS3 of the recess 444 is higher than the top surface TS1 of the bottom portion.

Two metal layers M1 are disposed on/over/above the conductive vias 24/26, respectively, and on the bottom portion 42 of the dielectric layer 40. A metal layer M1 contacts the conductive via 24 and is thus electrically connected to the electrode 22. The other metal layer M1 is in contact with the conductive via 26, thereby electrically connecting with the electrode 20.

The metal layer M1 is disposed in a thinner portion (i.e., the bottom portion 42) of the dielectric layer 40. The top surface of the metal layer M1 is substantially coplanar with the top surface of the recess 444, for example. Two metal layers M2 are disposed on/over/on the mesa portion 442 of the top portion 44. Two metal layers M2 are disposed on the thicker portions (i.e., the top portion 44 and the bottom portion 42) of the dielectric layer 40, so that the height of the metal layer M2 is higher than that of the metal layer M1. The connection structure CS is disposed on the metal layer M2 and is used for connecting/coupling with an external electronic device. The connection structure CS includes a conductive pad 52 and a conductive bump (bump) 54. The conductive pad 52 is disposed on/above/over the metal layer M2. The semiconductor device 1A can be disposed on an external electronic device in a flip-chip manner through the conductive bumps 54 in the connection structure CS, so as to achieve connection between the semiconductor device 1A and the external electronic device.

The redistribution layer RDL is disposed between the metal layers M1 and M2. The redistribution layer RDL does not overlap the connection structure CS in the longitudinal direction. The redistribution line layer RDL extends between and connects both metal layers M1, M2 to form an interface with the corresponding metal layer. The interface comprises a discernible boundary. That is, there is a distinguishable boundary between the redistribution layer RDL and the metal layer M1, or between the redistribution layer RDL and the metal layer M2. In detail, the redistribution layer RDL has two opposite ends, one of which covers/contacts the metal layer M1 to form an interface IF1 therebetween, and the other of which covers/contacts the metal layer M2 to form another interface IF2 therebetween. The redistribution line layer RDL extends from the top surface of the metal layer M2 along the side surface of the metal layer M2, the side surface of the mesa 442, the top surface of the recess 444, onto the top surface of the metal layer M1 to enable connection between the metal layers M1, M2. In other words, the redistribution layer RDL may serve as a bridge structure between the metal layers M1, M2.

The metal layers M1 and M2 are made of, for example, metal, and the material of the metal layers is the same. In some embodiments, the material of the metal layers M1, M2 comprises, for example, aluminum or an alloy thereof. The material of the redistribution layer RDL is, for example, metal, and the material of the redistribution layer RDL is, for example, copper. Thus, the interfaces IF1, IF2 may be, for example, copper-aluminum interfaces. In some embodiments, the material of the conductive pad 52 may include a nickel-platinum-gold (Ni/Pt/Au) alloy, which is not limited in the disclosure. In some embodiments, the material of the conductive bump 54 may include tin (Sn), gold (Au) or an alloy thereof, which is not limited in the present invention.

In view of the above, in the embodiment of the present invention, an interconnect structure having a double-intersection interface is adopted between the electrodes 20/22 and the connection structure CS, wherein one metal layer M1 in the interconnect structure is connected to the electrode 22 (or the electrode 20) through the conductive via 24 (or the conductive via 26), and the other metal layer M2 in the interconnect structure is connected to the connection structure CS. The semiconductor device 1A can be connected to an external electronic device through the connection structure CS. The redistribution layer RDL, which is located between the metal layers M1, M2, serves to connect the two together to make the connection between the electrodes and the external electronic device. Therefore, in the region between the connection structure CS and the electrode 20 (or the electrode 22), the metal layer M1, the redistribution layer RDL, and the metal layer M2 are provided, respectively. By such an arrangement, the size of any one of the three components is not excessively large, and the thermal warping phenomenon caused by heat of any one of the three components is further reduced.

Further, the metal layer M1 has two opposite edges E1, E2, and defines an extension ER1 of the metal layer M1. The metal layer M2 also has two opposite edges E3, E4, and defines an extension ER2 of the metal layer M2. The extension referred to is the lateral extension. The extension ranges ER1 and ER2 do not overlap or overlap with each other, or the extension ranges ER1 and ER2 are staggered with each other. The redistribution layer RDL also has two opposite edges E5, E6, and defines an extension ER3 of the redistribution layer RDL. One edge E5 of the redistribution layer RDL is located between two edges E1, E2 of the metal layer M1, and the other edge E6 of the redistribution layer RDL is located between two edges E3, E4 of the metal layer M2. Therefore, the extension range of the redistribution layer RDL does not exceed the maximum extension range formed by two edges E1 and E4 of the four edges E1 to E4 of the metal layers M1 and M2. By such an arrangement it may further be ensured that the size of the re-configuration line layer RDL is not too large. Therefore, the thermal expansion warpage of the redistribution layer RDL caused by heat generated during the operation of the device can be avoided or almost negligible, so that the reliability of the semiconductor device 1A in high power/high junction temperature applications can be greatly improved.

Dielectric layer 60 covers partial metal layer M1, partial metal layer M2, and top portion 44, wherein two metal layers M2 are separated by a portion of dielectric layer 60. The dielectric layer 60 together with the redistribution line layer RDL covers the top surface of the metal layer M1. The material of the dielectric layer 60 may be, but is not limited to, a dielectric material. For example, the material of the dielectric layer 60 may include, for example, but not limited to, silicon oxide (SiOx), silicon oxide nitride (SiON), silicon carbide (SiC), boron nitride (SiBN), carbon boron nitride (SiCBN), an oxide, a nitride, a Plasma Enhanced Oxide (PEOX), or a combination thereof, which is not limited in this disclosure.

The encapsulation material layer 70 covers the redistribution layer RDL, the metal layers M1, M2, and a portion of the metal layer M2 is not covered by the encapsulation material layer 70. The connection structure CS is disposed on the metal layer M2 of this portion. The conductive pads 52 and the conductive bumps 54 in the connection structure CS are separated from the redistribution layer RDL by the packaging material layer 70. The material of the packaging material layer 70 is, for example, polyimide (PI) or other suitable packaging materials, which the invention is not limited to.

Fig. 2A, 2B, 2C, 2D, 2E and 2F show different phase diagrams of a method for manufacturing the semiconductor device 1A, as follows. Hereinafter, the deposition technique may include, but is not limited to, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), metal Organic CVD (MOCVD), plasma Enhanced CVD (PECVD), low-pressure CVD (LPCVD), plasma-assisted vapor deposition (LPCVD), epitaxial growth (epitaxial growth), or other suitable processes, for example.

Referring to fig. 2A, a substrate 10 is provided. A nitride epitaxial stack ES is formed on/over/on the substrate 10. In detail, the nitride epitaxial stack ES includes nitride semiconductor layers 12 and 14. The nitride semiconductor layer 12 is on/over/on the substrate 10. A nitride semiconductor layer 14 is formed on/over/on the nitride semiconductor layer 12.

Electrodes

20, 22 are formed on/over/on nitride semiconductor layer 14. The bottom portion 42 of the insulating layer is formed to cover the

electrodes

20, 22 and the nitride epitaxial stack ES (nitride semiconductor layer 14).

Conductive vias

24, 26 are formed in the bottom portion 42 of the insulating layer to contact the

electrodes

20, 22. A metal layer M1 is formed on/over the bottom portion 42 of the insulating layer and the

conductive vias

24, 26.

Referring to fig. 2B, an intermediate top portion 44' of the insulating layer is formed to cover the metal layer M1 and the bottom portion 42.

Referring to fig. 2C, a portion of the middle top portion 44' is removed to expose the top surface of the metal layer M1, thereby forming a top portion 44 having a mesa 442 and a recess 444.

Referring to fig. 2D, a dielectric layer 60 is formed to cover the partial metal layer M1 and the top portion 44, wherein the two metal layers M2 are separated by a portion of the dielectric layer 60.

Referring to fig. 2E, a redistribution layer RDL is formed between the metal layers M1 and M2, so that the metal layer M1 and the metal layer M2 are electrically connected through the redistribution layer RDL. The material of the redistribution layer RDL is different from the material of the metal layers M1, M2.

Referring to fig. 2F, an encapsulation material layer 70 is formed to cover the redistribution layer RDL and the dielectric layer 60, wherein the encapsulation material layer 70 is formed with a via hole to expose at least a portion of the metal layer M2. A connection structure CS including a conductive pad 52 and a conductive bump 54 is formed. To this end, the semiconductor device 1A in fig. 1 is substantially completed.

Fig. 3 is a cross-sectional view of a semiconductor device 1B according to some embodiments of the present invention. Referring to fig. 3, a semiconductor device 1B of fig. 3 is substantially similar to the semiconductor device 1A of fig. 1, and the main differences are: differences in the connecting structure. In detail, in the semiconductor device 1B, the connection structure includes the bonding wire BL. The bonding wire BL is provided on the metal layer M2. That is, the semiconductor device 1B can be connected to an external electronic device by wire bonding.

Note that, in the present embodiment, the material of the metal layer M2 is, for example, aluminum or an alloy thereof. The bonding lead BL is bonded on the metal layer M2 by the wire bonding method, so that the workability and reliability of the wire bonding method can be improved.

In summary, in the embodiments of the present invention, an interconnection structure is disposed between the electrode and the connection structure, wherein the interconnection structure includes: a metal layer connected to the electrode, another metal layer connected to the connection structure, and a redistribution layer located between the two metal layers. The materials of the redistribution layer and the two metal layers are different from each other, so that at least two interfaces can be formed therebetween. With this configuration, the size of the three components can be further reduced without each component occupying too large an area, thereby avoiding the thermal warpage phenomenon caused by overheating of a single component or making the thermal warpage phenomenon almost negligible. The semiconductor device of the embodiment of the invention has good reliability.

The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed above. It is intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations will be apparent to practitioners skilled in the art.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.

Terms used herein, and not otherwise defined, such as "substantially," "approximately," and "about," are used for descriptive purposes and to explain minor variations. When used with an event or condition, the term can include instances where the event or condition occurs precisely, as well as instances where the event or condition occurs approximately. For example, when used with numerical values, the term can encompass a range of variation of less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. By the term "substantially coplanar," it can refer to two surfaces located along the same plane within a few micrometers (μm), such as within 40 micrometers (μm), within 30 μm, within 20 μm, within 10 μm, or within 1 μm.

As used herein, the singular terms "a", "an" and "the" may include the plural reference unless the context clearly dictates otherwise. In the description of some embodiments, a component that is provided "above" or "on top of" another component may include situations where the former component is directly on (e.g., in physical contact with) the latter component, and situations where one or more intervening components are located between the former and the latter component. While the present disclosure has been described and illustrated with reference to specific embodiments thereof, the description and illustration are not intended to be construed in a limiting sense. It will be understood by those skilled in the art that various changes may be made and equivalents substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined in the following claims. The drawings are not necessarily to scale. Due to manufacturing process and tolerances, there may be differences between the processes presented in this summary and the actual devices. Other embodiments of the inventive content may not be specifically described. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein are described by performing particular operations in a particular order, it will be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of such operations is not limited.

Claims

1. A nitride semiconductor device comprising:

a nitride epitaxial stack;

at least one electrode disposed on the nitride epitaxial stack;

an insulating layer covering the electrode and the nitride epitaxial stack;

the conductive through hole is arranged on the electrode;

a first metal layer and a second metal layer disposed on the insulating layer, wherein the first metal layer is disposed above the conductive via and electrically connected to the electrode through the conductive via, and the first metal layer is separated from the second metal layer; and

and a redistribution layer disposed between and connecting the first metal layer and the second metal layer, wherein the redistribution layer has a first end and a second end opposite to each other, the first end covers the first metal layer, and the second end covers the second metal layer, and a material of the redistribution layer is different from a material of the first metal layer and the second metal layer.

2. The nitride semiconductor device according to claim 1, wherein a first extension of the first metal layer on the insulating layer and a second extension of the second metal layer on the insulating layer do not overlap each other.

3. The nitride semiconductor device according to claim 1, wherein the insulating layer has a first portion and a second portion, a height of a top surface of the first portion is greater than a height of a top surface of the second portion, and the first metal layer and the second metal layer are provided on the top surface of the first portion and the top surface of the second portion, respectively.

4. The nitride semiconductor device according to claim 1, further comprising a layer of encapsulation material covering said redistribution line layer, said first metal layer and said second metal layer.

5. The nitride semiconductor device according to claim 1, further comprising a dielectric layer covering the first metal layer and the second metal layer.

6. The nitride semiconductor device according to claim 1, further comprising:

and the connecting structure is arranged on the second metal layer.

7. The nitride semiconductor device according to claim 6, wherein the connection structure further comprises:

and the bonding lead is arranged on the second metal layer.

8. The nitride semiconductor device according to claim 6, further comprising:

the conductive connecting pad is arranged on the second metal layer; and

and the conductive bump is arranged on the conductive contact pad.

9. The nitride semiconductor device of claim 8, wherein the conductive pad is spaced apart from the redistribution line layer.

10. The nitride semiconductor device according to claim 8, wherein a material of the conductive pad comprises a nickel-platinum-gold alloy.

11. The nitride semiconductor device according to claim 1, wherein a material of the redistribution line layer comprises copper.

12. The nitride semiconductor device according to claim 1, wherein the first metal layer and the second metal layer are the same material.

13. The nitride semiconductor device according to claim 12, wherein a material of the first metal layer and the second metal layer includes aluminum or an alloy thereof.

14. The nitride semiconductor device according to claim 1, wherein the nitride epitaxial stack comprises:

a first nitride semiconductor layer; and

and a second nitride semiconductor layer which is provided above the first nitride semiconductor layer and has an energy gap larger than that of the first nitride semiconductor layer to form a heterojunction and a two-dimensional electron gas region adjacent to the heterojunction, wherein the at least one electrode is provided on the second nitride semiconductor layer, and the insulating layer covers the second nitride semiconductor layer.

15. The nitride semiconductor device of claim 1, further comprising a gate structure disposed on the nitride epitaxial stack.

16. A method of manufacturing a nitride semiconductor device, comprising:

forming a nitride epitaxial stack;

forming at least one electrode on the nitride epitaxial stack;

forming an insulating layer to cover the at least one electrode and the nitride epitaxial stack;

forming a conductive via in the insulating layer to contact the at least one electrode;

forming a first metal layer on the insulating layer and the conductive via;

forming a second metal layer on the insulating layer and separated from the first metal layer; and

forming a redistribution layer between the first metal layer and the second metal layer such that the first metal layer and the second metal layer are electrically connected through the redistribution layer, wherein the material of the redistribution layer is different from the material of the first metal layer and the second metal layer.

17. The manufacturing method of claim 16, wherein the step of forming the insulating layer comprises:

forming a bottom portion of the insulating layer to encapsulate the at least one electrode and the nitride epitaxial stack prior to the step of forming the first metal layer;

after the step of forming the first metal layer, forming a top portion of the insulating layer to cover the first metal layer and a bottom portion of the insulating layer; and

removing a portion of the top portion of the insulating layer to expose a top surface of the first metal layer.

18. The method of manufacturing of claim 17, wherein the first metal layer is formed on a top surface of the bottom portion of the insulating layer and the second metal layer is formed on a top surface of the top portion of the insulating layer.

19. The method of manufacturing of claim 16, further comprising:

forming a dielectric layer to cover the first metal layer and the second metal layer.

20. The method of manufacturing of claim 16, further comprising:

and forming a connecting structure on the second metal layer.

21. An interconnect structure disposed on a semiconductor structure, the interconnect structure comprising:

an insulating layer covering the semiconductor structure and having a plurality of portions of different thicknesses,

a first conductive layer disposed on the thin portion of the insulating layer and connected to an electrode of the semiconductor structure;

the second conducting layer is arranged on the part of the insulating layer with thicker thickness;

a redistribution line layer extending between the first conductive layer and the second conductive layer; and

and the connecting structure is arranged on the second metal layer, and the reconfiguration line layer and the connecting structure are not overlapped in the longitudinal direction.

22. The interconnect structure of claim 21, wherein said redistribution line layer extends from a top surface of said second conductive layer onto a top surface of said first conductive layer along a side surface of said second conductive layer and a side surface of said insulating layer.

23. The interconnect structure of claim 21 wherein,

the first conductive layer is provided with a first edge and a second edge which are opposite to each other, and the first edge and the second edge define a first extension range of the first conductive layer;

the second conductive layer is provided with a third edge and a fourth edge which are opposite to each other, and the third edge and the fourth edge define a second extension range of the second conductive layer;

wherein the first extension range is staggered from the second extension range.

24. The interconnect structure of claim 23, wherein the reconfiguration line layer has a fifth edge and a sixth edge opposite each other, wherein the fifth edge falls within the first extension and the sixth edge falls within the second extension.

25. The interconnect structure of claim 21, wherein said electrode of said semiconductor structure is interconnected to said connection structure disposed on said second conductive layer by said interconnect structure.