CN115732553A

CN115732553A - IGBT device and preparation method thereof

Info

Publication number: CN115732553A
Application number: CN202211407171.7A
Authority: CN
Inventors: 侯晓伟; 郭依腾; 罗杰馨; 柴展
Original assignee: Shanghai Gongcheng Semiconductor Technology Co Ltd
Current assignee: Shanghai Gongcheng Semiconductor Technology Co Ltd
Priority date: 2022-11-10
Filing date: 2022-11-10
Publication date: 2023-03-03
Anticipated expiration: 2042-11-10
Also published as: CN115732553B

Abstract

The invention provides an IGBT device and a preparation method thereof, and the device comprises: the IGBT device comprises a substrate, wherein an IGBT emitter, an IGBT grid and an IGBT collector are formed on the substrate; the dummy grid is arranged between the grid and the IGBT emitter; the NMOS tube is arranged between the IGBT grid and the dummy grid, the source electrode and the grid of the NMOS tube are electrically connected with the IGBT grid, and the drain electrode is electrically connected with the dummy grid; and the PNP triode is arranged between the dummy grid and the IGBT emitter, the collector of the PNP triode is electrically connected with the dummy grid, the emitter is electrically connected with the IGBT emitter, and the base is electrically connected with the IGBT emitter through an inductor. According to the invention, the potential change of the dummy grid is controlled in different working states (conducting state and opening process) of the device, so that the heating of the device can be effectively improved, the power density is improved, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.

Description

IGBT device and preparation method thereof

Technical Field

The invention belongs to the field of design and manufacture of semiconductor integrated circuits, and particularly relates to an IGBT device and a preparation method thereof.

Background

An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of BJT (Bipolar junction Transistor) and MOS (Insulated Gate field effect Transistor). The IGBT device has the advantages of low saturation voltage, high current density, low driving power and high switching speed, and is suitable for a power supply management system with the withstand voltage of over 600V.

Losses of the IGBT device generally include conduction losses and switching losses, and in device design, a compromise needs to be made between the conduction losses and the switching losses, and in order to optimize the switching losses of the device, the device switching losses are generally reduced by using a dummy gate, but the conduction losses of the IGBT device are increased by the dummy gate.

It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. These solutions are not considered to be known to the person skilled in the art merely because they are set forth in the background section of the present application.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an IGBT device and a method for manufacturing the IGBT device, which are used to solve the problem of large turn-on loss or/and switching loss of the IGBT device in the prior art.

To achieve the above and other related objects, the present invention provides an IGBT device including: the IGBT device comprises a substrate, wherein an IGBT emitter, an IGBT grid and an IGBT collector of the IGBT device are formed on the substrate; a dummy gate disposed between the gate and the IGBT emitter; the NMOS tube is arranged on the substrate and is arranged between the IGBT grid and the dummy grid, the source electrode and the grid of the NMOS tube are electrically connected with the IGBT grid, and the drain electrode is electrically connected with the dummy grid; the PNP triode is arranged on the substrate and is arranged between the dummy grid and the IGBT emitting electrode, a collector electrode of the PNP triode is electrically connected with the dummy grid, the emitting electrode of the PNP triode is electrically connected with the IGBT emitting electrode, and a base electrode of the PNP triode is electrically connected with the IGBT emitting electrode through an inductor.

Optionally, when the IGBT device is turned on, the IGBT gate applies a threshold voltage, and the threshold voltage is simultaneously applied to the gate of the NMOS transistor to turn on the NMOS transistor, so that the IGBT gate is connected to the dummy gate, and a channel is formed below the dummy gate to reduce the turn-on loss of the IGBT device.

Optionally, when the IGBT device is turned on, the current of the IGBT emitter rises, and there is a voltage change in the inductance between the PNP triode and the IGBT emitter, so that the PNP triode is in an amplified state and turned on, and the dummy gate is connected to the IGBT emitter, thereby reducing the turn-on loss of the IGBT device.

Optionally, the threshold voltage of the NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the difference between the threshold voltage of the IGBT gate and the threshold voltage of the NMOS transistor is less than or equal to 5V.

Optionally, the IGBT gate and the dummy gate are arranged in a ring shape, the dummy gate surrounds the IGBT emitter, and the IGBT gate surrounds the dummy gate.

Optionally, the substrate includes a first surface and a second surface opposite to each other, the IGBT emitter and the IGBT gate are disposed on the first surface of the substrate, and the IGBT collector is disposed on the second surface of the substrate, or/and the IGBT device further includes a field stop layer disposed in the substrate and disposed close to the IGBT collector.

Optionally, the inductance value of the inductor is 10 nH-20 nH.

The invention also provides a preparation method of the IGBT device, which comprises the following steps: providing a substrate, and forming an IGBT emitter, an IGBT grid, an IGBT collector and a dummy grid of an IGBT device on the substrate, wherein the dummy grid is arranged between the grid and the IGBT emitter; arranging an NMOS tube on the substrate, wherein the NMOS tube is arranged between the IGBT grid and the dummy grid, the source electrode and the grid electrode of the NMOS tube are electrically connected with the IGBT grid, and the drain electrode is electrically connected with the dummy grid; and a PNP triode is arranged on the substrate and is arranged between the dummy grid and the IGBT emitting electrode, the collector electrode of the PNP triode is electrically connected with the dummy grid, the emitting electrode of the PNP triode is electrically connected with the IGBT emitting electrode, and the base electrode of the PNP triode is electrically connected with the IGBT emitting electrode through an inductor.

Optionally, the step of disposing an NMOS transistor and a PNP triode on the substrate includes: forming a first P well and a second P well in the substrate through an ion implantation process; forming a gate dielectric layer and a gate layer on the substrate, and forming an IGBT gate, a dummy gate and a gate of an NMOS tube through a patterning process; forming a source electrode and a drain electrode of an NMOS (N-channel metal oxide semiconductor) tube in the first P trap through an ion implantation process, and forming a base electrode and an emitting electrode of a PNP triode in the second P trap; forming an insulating layer on the substrate, forming a contact hole in the insulating layer, forming a metal layer on the contact hole and the insulating layer, forming a wiring layer through a patterning process, and enabling a source electrode and a grid electrode of the NMOS tube to be electrically connected with the IGBT grid electrode, a drain electrode to be electrically connected with the dummy grid electrode, a collector electrode of the PNP triode to be electrically connected with the dummy grid electrode, an emitter electrode to be electrically connected with the IGBT emitter electrode, and a base electrode to be connected with a contact point.

Optionally, the method further comprises the steps of: an inductor is connected between a contact point of the base electrode of the PNP triode and the emitting electrode of the IGBT through an external pin, and the inductance value of the inductor is 10 nH-20 nH.

Optionally, when the IGBT device is turned on, the IGBT grid electrode applies a threshold voltage, the threshold voltage is simultaneously applied to the grid electrode of the NMOS tube to turn on the NMOS tube, so that the IGBT grid electrode is connected with the dummy grid electrode, and a channel is formed below the dummy grid electrode to reduce the turn-on loss of the IGBT device; when the IGBT device is switched on, the current of the IGBT emitting electrode rises, and the voltage of the inductor between the PNP triode and the IGBT emitting electrode changes, so that the PNP triode is in an amplification state and is conducted, the dummy grid is connected with the IGBT emitting electrode, and the switching-on loss of the IGBT device is reduced.

Optionally, the substrate includes a first side and a second side opposite to each other, the IGBT emitter and the IGBT gate are disposed on the first side of the substrate, and the IGBT collector is disposed on the second side of the substrate, or/and the IGBT device further includes a field stop layer disposed in the substrate and disposed close to the IGBT collector.

As described above, the IGBT device and the method for manufacturing the same according to the present invention have the following advantageous effects:

according to the invention, when the IGBT device is conducted, the IGBT grid electrode applies threshold voltage, and the threshold voltage is simultaneously applied to the grid electrode of the NMOS tube to conduct the NMOS tube, so that the IGBT grid electrode is connected with the dummy grid electrode, and a channel is formed below the dummy grid electrode to reduce the conduction loss of the IGBT device. When the IGBT device is switched on, the current of the IGBT emitting electrode rises, and the voltage change exists in the inductance between the PNP triode and the IGBT emitting electrode, so that the PNP triode is in an amplification state and is conducted, the dummy grid is connected with the IGBT emitting electrode, and the switching loss of the IGBT device is reduced. According to the invention, the change of the electric potential of the dummy grid is controlled when the device is in different working states, so that the heating of the device can be effectively improved, the power density is improved, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.

The NMOS tube and the PNP triode are arranged among the IGBT grid electrode, the dummy grid electrode and the IGBT emitting electrode, the area of a device is not required to be occupied additionally, the turn-on loss and the turn-on loss of the device can be reduced simultaneously under the condition of smaller volume, the NMOS tube and the PNP triode are compatible with the manufacturing process of the conventional IGBT device, additional manufacturing equipment is not required to be added, and the manufacturing cost of the device can be effectively controlled.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is to be understood that the drawings in the following description are of some embodiments of the application only.

Fig. 1 shows a schematic layout structure of an IGBT device according to an embodiment of the present invention.

Fig. 2 shows a schematic circuit diagram of an IGBT device according to an embodiment of the present invention.

Fig. 3 to fig. 8 show schematic structural diagrams presented in steps of a method for manufacturing an IGBT device according to an embodiment of the present invention.

Description of the element reference numerals

10 IGBT grid

11. Dummy gate

12 IGBT emitter

13 NMOS tube

14 PNP triode

15. Inductance

101. Substrate

102. First P well

103. Second P well

104 NMOS gate

106 NMOS source electrode

107 NMOS drain electrode

108. Base electrode

109. Emitter electrode

110. Insulating layer

111. First wiring

112. Second wiring

113. Contact point

Detailed Description

The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be emphasized that the term "comprises/comprising" when used herein, is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.

Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments, in combination with or instead of the features of the other embodiments.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Spatially relative terms, such as "under," "below," "lower," "below," "over," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

As shown in fig. 1 to 8, the present embodiment provides an IGBT device including: the IGBT device comprises a substrate 101, wherein an IGBT emitter 12, an IGBT gate 10 and an IGBT collector of the IGBT device are formed on the substrate 101; a dummy gate 11 disposed between the gate and the IGBT emitter 12; the NMOS tube 13 is arranged on the substrate 101 and is arranged between the IGBT grid 10 and the dummy grid 11, the source 109 and the grid 104 of the NMOS tube 13 are electrically connected with the IGBT grid 10, and the drain 107 is electrically connected with the dummy grid 11; the PNP triode 14 is arranged on the substrate 101 and is arranged between the dummy gate 11 and the IGBT emitter 12, a collector 108 of the PNP triode 14 is electrically connected with the dummy gate 11, an emitter 109 is electrically connected with the IGBT emitter 12, and a base 108 is electrically connected with the IGBT emitter 12 through an inductor 15.

The substrate 101 may be, for example, a silicon substrate 101, and the substrate 101 may further include other semiconductors, such as germanium, silicon carbide (SiC), or silicon germanium (SiGe). The substrate 101 may include a compound semiconductor and/or an alloy semiconductor such as gallium nitride, gallium arsenide, or the like. In addition, the substrate 101 may include an epitaxial layer (epi layer) and may also be strained to improve performance. In this embodiment, the substrate 101 includes a drift region, such as an N-type lightly doped drift region.

The substrate 101 includes a first surface and a second surface opposite to each other, the IGBT emitter 12 and the IGBT gate 10 are disposed on the first surface of the substrate 101, and the IGBT collector is disposed on the second surface of the substrate 101, or/and the IGBT device further includes a field stop layer disposed in the substrate 101 and disposed close to the IGBT collector.

In one embodiment, the IGBT emitter 12 of the IGBT device includes an N + -type emitter region, and a P-type body region disposed between the N + -type emitter region and an N-type drift region, which is not shown.

As shown in fig. 1, the IGBT gate 10 and the dummy gate 11 are arranged in a ring shape, such as a rectangular ring, a rounded rectangular ring, an elliptical ring, a circular ring, etc., the dummy gate 11 surrounds the IGBT emitter 12, the IGBT gate 10 surrounds the dummy gate 11, the IGBT gate 10 and the dummy gate 11 have a space therebetween, and the dummy gate 11 and the IGBT emitter 12 have a space therebetween.

As shown in fig. 1 and 8, wherein fig. 8 is a schematic cross-sectional structure diagram of a dotted line in fig. 1, the NMOS transistor 13 is disposed on the substrate 101 and between the IGBT gate 10 and the dummy gate 11, the NMOS transistor 13 includes a first P well 102 disposed in the substrate 101, an NMOS gate 104 disposed on the first P well 102, and a source 106 and a drain 107 disposed in the first P well 102 at two sides of the NMOS gate 104. In one embodiment, the threshold voltage of the NMOS transistor 13 is less than or equal to the threshold voltage of the IGBT gate 10, and the difference between the threshold voltage of the IGBT gate 10 and the threshold voltage of the NMOS transistor 13 is less than or equal to 5V. For example, the threshold voltage of the gate of the IGBT device may be 15V, and the threshold voltage of the gate of the NMOS transistor 13 may be set to be 13.5V to 15V.

As shown in fig. 1 and 8, the PNP transistor 14 is disposed on the substrate 101 and between the dummy gate 11 and the IGBT emitter 12, the PNP transistor 14 includes a second P-well 103 (serving as a collector of the PNP transistor) disposed in the substrate 101, a PNP base 108 on the second P-well 103, and an emitter 109 disposed in the PNP base 108, and the base 108 separates the emitter 109 from the second P-well 103.

According to the invention, through controlling the change of the electric potential of the dummy grid electrode when the device is in different working states, the heating of the device can be effectively improved, the power density is improved, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.

As shown in fig. 8, the source and gate of the NMOS transistor 13 are electrically connected to the IGBT gate 10 through a first wiring 111, the drain of the dummy gate 11 is electrically connected to the collector of the PNP transistor 14 through a second wiring 112, the emitter 109 of the PNP transistor 14 is electrically connected to the IGBT emitter 12, a contact point 113 is provided on the base 108 through a wiring, and when a pin is subsequently provided, the contact point 113 is electrically connected to the IGBT emitter 12 through an inductor 15.

In one embodiment, the inductance value of the inductor 15 is 10nH to 20nH, for example, the inductance value of the inductor 15 may be 13nH.

In one embodiment, when the IGBT device is turned on, the IGBT gate 10 applies a threshold voltage, which is simultaneously applied to the gate of the NMOS transistor 13 to turn on the NMOS transistor 13, so that the IGBT gate 10 is connected to the dummy gate 11, and a channel is formed below the dummy gate 11 to reduce the turn-on loss of the IGBT device.

In one embodiment, when the IGBT device is turned on, the current of the IGBT emitter 12 rises, and there is a voltage change in the inductor 15 between the PNP transistor 14 and the IGBT emitter 12, so that the PNP transistor 14 is in an amplified state and is turned on, so that the dummy gate 11 is connected to the IGBT emitter 12, thereby reducing the turn-on loss of the IGBT device.

Fig. 2 shows a schematic circuit diagram of the IGBT device of this embodiment, specifically, when the IGBT device is in an on state, a voltage of a normal gate is about 15V, at this time, a drain of the NMOS transistor 13 is shorted with the IGBT gate 10, the dummy gate 11 is shorted with a source, when a voltage of the NMOS gate 104 is 15V, the NMOS transistor 13 is turned on, potentials of the IGBT gate 10 and the dummy gate 11 are the same, at this time, channels on two sides of the dummy gate 11 of the device are opened, and a VCESAT of the device is reduced, thereby reducing a conduction loss of the device.

The IGBT emitter 12 of the IGBT device of this embodiment has an inductance 15, for example, the internal integrated inductance 15 of TO247 is about 13nH, when the device is in the turn-on process, the current of the IGBT emitter 12 rises, taking the IGBT device of 650V15A as an example, during the turn-on process of the device, the current change di/dt in the inductance 15 is about 130A/us TO 300A/us, so that the voltage across the inductance 15 of the IGBT emitter 12 changes TO 1.69V TO 3.9V, and the PNP triode 14 is in the amplification state and is turned on, so as TO connect the dummy gate 11 and the IGBT emitter 12 together, thereby effectively reducing the turn-on loss of the device.

As shown in fig. 1 to fig. 8, the present embodiment further provides a method for manufacturing an IGBT device, where the method includes the following steps: providing a substrate 101, and forming an IGBT emitter 12, an IGBT gate 10, an IGBT collector and a dummy gate 11 of an IGBT device on the substrate 101, wherein the dummy gate 11 is arranged between the IGBT gate 10 and the IGBT emitter 12; arranging an NMOS tube 13 on the substrate 101, wherein the NMOS tube 13 is arranged between the IGBT grid 10 and the dummy grid 11, a source 106 and a grid 104 of the NMOS tube 13 are electrically connected with the IGBT grid 10, and a drain 107 is electrically connected with the dummy grid 11; a PNP transistor 14 is disposed on the substrate 101, the PNP transistor 14 is disposed between the dummy gate 11 and the IGBT emitter 12, a collector of the PNP transistor 14 is electrically connected to the dummy gate 11, an emitter 109 is electrically connected to the IGBT emitter 12, and a base 108 is electrically connected to the IGBT emitter 12 through an inductor 15.

In one embodiment, as shown in fig. 3 to 8, the disposing of the NMOS transistor 13 and the PNP transistor 14 on the substrate 101 includes the following steps:

as shown in fig. 3 to 4, step 1) is first performed to form a first P well 102 and a second P well 103 in the substrate 101 by an ion implantation process; certainly, in the process, structures such as a P-type body region of the IGBT device can be prepared at the same time, so that the process cost is saved.

As shown in fig. 5, step 2) is then performed to form a gate dielectric layer and a gate layer on the substrate 101, and form an IGBT gate 10, a dummy gate 11, and a gate of the NMOS transistor 13 through a patterning process. The gate dielectric layer may be, for example, silicon dioxide or the like, or may be a high-k dielectric such as hafnium oxide or the like, and the gate layer may be polysilicon or metal or the like.

As shown in fig. 6, step 3) is then performed to form source 106 and drain 107 of NMOS transistor 13 in first P-well 102 by ion implantation, and form base 108 and emitter 109 of PNP transistor 14 in second P-well 103. Certainly, in the process, structures such as an emitter region of the IGBT and the like can be prepared at the same time, so that the process cost is saved.

As shown in fig. 7 to 8, step 4) is finally performed to form an insulating layer 110 on the substrate 101, form a contact hole in the insulating layer 110, form a metal layer on the contact hole and the insulating layer 110, and form a wiring layer through a patterning process, so that the source and the gate of the NMOS transistor 13 are electrically connected to the IGBT gate 10, the drain is electrically connected to the dummy gate 11, the collector of the PNP triode 14 is electrically connected to the dummy gate 11, the emitter 109 is electrically connected to the IGBT emitter 12, and the base 108 is connected to the contact point 113.

In one embodiment, the method further comprises the steps of: an inductor 15 is connected between a contact point 113 of the base 108 of the PNP triode 14 and the IGBT emitter 12 through an external pin, and the inductance value of the inductor 15 is 10 nH-20 nH.

In one embodiment, when the IGBT device is turned on, the IGBT gate 10 applies a threshold voltage, which is simultaneously applied to the gate of the NMOS transistor 13 to turn on the NMOS transistor 13, so that the IGBT gate 10 is connected to the dummy gate 11, and a channel is formed below the dummy gate 11 to reduce the turn-on loss of the IGBT device; when the IGBT device is switched on, the current of the IGBT emitter 12 rises, and the voltage of the inductor 15 between the PNP triode 14 and the IGBT emitter 12 changes, so that the PNP triode 14 is in an amplification state and is conducted, the dummy gate 11 is connected with the IGBT emitter 12, and the switching loss of the IGBT device is reduced.

In one embodiment, the threshold voltage of the NMOS transistor 13 is less than or equal to the threshold voltage of the IGBT gate 10, and the difference between the threshold voltage of the IGBT gate 10 and the threshold voltage of the NMOS transistor 13 is less than or equal to 5V.

In one embodiment, the IGBT gate 10 and the dummy gate 11 are arranged in a ring shape, the dummy gate 11 surrounds the IGBT emitter 12, and the IGBT gate 10 surrounds the dummy gate 11.

In one embodiment, the substrate 101 includes a first side and a second side opposite to each other, the IGBT emitter 12 and the IGBT gate 10 are disposed on the first side of the substrate 101, and the IGBT collector is disposed on the second side of the substrate 101, or/and the IGBT device further includes a field stop layer disposed in the substrate 101 and disposed near the IGBT collector.

according to the invention, when the IGBT device is conducted, the IGBT grid 10 applies threshold voltage, and the threshold voltage is simultaneously applied to the grid of the NMOS tube 13 to conduct the NMOS tube 13, so that the IGBT grid 10 is connected with the dummy grid 11, and a channel is formed below the dummy grid 11 to reduce the conduction loss of the IGBT device. When the IGBT device is switched on, the current of the IGBT emitting electrode 12 rises, and the voltage change exists in the inductor 15 between the PNP triode 14 and the IGBT emitting electrode 12, so that the PNP triode 14 is in an amplification state and is conducted, the dummy grid 11 is connected with the IGBT emitting electrode 12, and the switching-on loss of the IGBT device is reduced. According to the invention, the change of the electric potential of the dummy grid 11 is controlled when the device is in different working states, so that the heating of the device can be effectively improved, the power density is improved, the performance of the device is further improved, and the IGBT device can be used for higher-frequency application.

The NMOS tube 13 and the PNP triode 14 are arranged among the IGBT grid 10, the dummy grid 11 and the IGBT emitter 12, the area of a device does not need to be occupied additionally, the turn-on loss and the turn-on loss of the device can be reduced simultaneously under the condition of smaller volume, the manufacturing process of the IGBT device is compatible with the conventional manufacturing process of the IGBT device, additional manufacturing equipment does not need to be added, and the manufacturing cost of the device can be effectively controlled.

Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. An IGBT device, characterized in that the IGBT device comprises:

the IGBT device comprises a substrate, wherein an IGBT emitter, an IGBT grid and an IGBT collector of the IGBT device are formed on the substrate;

a dummy gate disposed between the gate and the IGBT emitter;

the NMOS tube is arranged on the substrate and is arranged between the IGBT grid and the dummy grid, the source electrode and the grid of the NMOS tube are electrically connected with the IGBT grid, and the drain electrode is electrically connected with the dummy grid;

the PNP triode is arranged on the substrate and between the dummy grid and the IGBT emitting electrode, the collector electrode of the PNP triode is electrically connected with the dummy grid, the emitting electrode of the PNP triode is electrically connected with the IGBT emitting electrode, and the base electrode of the PNP triode is electrically connected with the IGBT emitting electrode through an inductor.

2. The IGBT device of claim 1, wherein: when the IGBT device is conducted, the IGBT grid electrode applies threshold voltage, the threshold voltage is simultaneously applied to the grid electrode of the NMOS tube to conduct the NMOS tube, so that the IGBT grid electrode is connected with the dummy grid electrode, and a channel is formed below the dummy grid electrode to reduce conduction loss of the IGBT device.

3. The IGBT device of claim 1, wherein: when the IGBT device is switched on, the current of the IGBT emitting electrode rises, and the voltage of the inductor between the PNP triode and the IGBT emitting electrode changes, so that the PNP triode is in an amplification state and is conducted, the dummy grid is connected with the IGBT emitting electrode, and the switching-on loss of the IGBT device is reduced.

4. The IGBT device of claim 1, wherein: the threshold voltage of the NMOS tube is smaller than or equal to that of the IGBT grid, and the difference between the threshold voltage of the IGBT grid and the threshold voltage of the NMOS tube is smaller than or equal to 5V.

5. The IGBT device of claim 1, wherein: the IGBT grid and the dummy grid are arranged in a ring shape, the dummy grid surrounds the periphery of the IGBT emitter, and the IGBT grid surrounds the periphery of the dummy grid.

6. The IGBT device of claim 1, wherein: the substrate comprises a first surface and a second surface which are opposite, the IGBT emitter and the IGBT grid electrode are arranged on the first surface of the substrate, the IGBT collector electrode is arranged on the second surface of the substrate, or/and the IGBT device further comprises a field stop layer which is arranged in the substrate and is close to the IGBT collector electrode.

7. The IGBT device of claim 1, wherein: the inductance value of the inductor is 10 nH-20 nH.

8. A preparation method of an IGBT device is characterized by comprising the following steps:

providing a substrate, and forming an IGBT emitter, an IGBT grid, an IGBT collector and a dummy grid of an IGBT device on the substrate, wherein the dummy grid is arranged between the IGBT grid and the IGBT emitter;

arranging an NMOS tube on the substrate, wherein the NMOS tube is arranged between the IGBT grid and the dummy grid, the source electrode and the grid of the NMOS tube are electrically connected with the IGBT grid, and the drain electrode is electrically connected with the dummy grid;

and a PNP triode is arranged on the substrate and is arranged between the dummy grid and the IGBT emitting electrode, the collector electrode of the PNP triode is electrically connected with the dummy grid, the emitting electrode of the PNP triode is electrically connected with the IGBT emitting electrode, and the base electrode of the PNP triode is electrically connected with the IGBT emitting electrode through an inductor.

9. The method for manufacturing an IGBT device according to claim 8, characterized in that: the method for arranging the NMOS transistor and the PNP triode on the substrate comprises the following steps:

forming a first P well and a second P well in the substrate through an ion implantation process;

forming a gate dielectric layer and a gate layer on the substrate, and forming an IGBT gate, a dummy gate and a gate of an NMOS tube through a patterning process;

forming a source electrode and a drain electrode of an NMOS (N-channel metal oxide semiconductor) tube in the first P trap through an ion implantation process, and forming a base electrode and an emitting electrode of a PNP triode in the second P trap;

forming an insulating layer on the substrate, forming a contact hole in the insulating layer, forming a metal layer on the contact hole and the insulating layer, forming a wiring layer through a patterning process, and enabling a source electrode and a grid electrode of the NMOS tube to be electrically connected with the IGBT grid electrode, a drain electrode to be electrically connected with the dummy grid electrode, a collector electrode of the PNP triode to be electrically connected with the dummy grid electrode, an emitter electrode to be electrically connected with the IGBT emitter electrode, and a base electrode to be connected with a contact point.

10. The method for manufacturing an IGBT device according to claim 9, characterized in that: further comprising the steps of: an inductor is connected between a contact point of the base electrode of the PNP triode and the emitting electrode of the IGBT through an external pin, and the inductance value of the inductor is 10 nH-20 nH.

11. The method for manufacturing an IGBT device according to claim 10, characterized in that: when the IGBT device is conducted, the IGBT grid electrode applies a threshold voltage, the threshold voltage is simultaneously applied to the grid electrode of the NMOS tube to conduct the NMOS tube, so that the IGBT grid electrode is connected with the dummy grid electrode, and a channel is formed below the dummy grid electrode to reduce the conduction loss of the IGBT device; when the IGBT device is switched on, the current of the IGBT emitting electrode rises, and the voltage of the inductor between the PNP triode and the IGBT emitting electrode changes, so that the PNP triode is in an amplification state and is conducted, the dummy grid is connected with the IGBT emitting electrode, and the switching-on loss of the IGBT device is reduced.

12. The method for manufacturing an IGBT device according to claim 8, characterized in that: the threshold voltage of the NMOS tube is smaller than or equal to that of the IGBT grid electrode, and the difference between the threshold voltage of the IGBT grid electrode and the threshold voltage of the NMOS tube is smaller than or equal to 5V.

13. The method for manufacturing an IGBT device according to claim 8, characterized in that: the IGBT grid and the dummy grid are arranged in a ring shape, the dummy grid surrounds the periphery of the IGBT emitter, and the IGBT grid surrounds the periphery of the dummy grid.

14. The method for manufacturing an IGBT device according to claim 8, characterized in that: the substrate comprises a first surface and a second surface which are opposite, the IGBT emitting electrode and the IGBT grid electrode are arranged on the first surface of the substrate, the IGBT collector electrode is arranged on the second surface of the substrate, or/and the IGBT device further comprises a field stop layer which is arranged in the substrate and is close to the IGBT collector electrode.