CN115729860A - Processing system, processing method and electronic equipment - Google Patents

Abstract

A processing system, a processing method and an electronic device are provided. The processing system comprises: a processor; the buffer is arranged between the processor and the off-chip memory and used for buffering the data in the off-chip memory, and comprises a cache data storage partition and an eviction buffer partition; wherein, the buffer is used for executing the following operations: in response to a first data in a cache data storage partition being evicted, storing the first data to the eviction buffer partition; in response to the second data in the eviction buffer partition being revisited, the cache data storage partition is updated according to the second data. The embodiment of the application sets the eviction buffer partition on the cache, can buffer recently evicted data, does not need to set an independent eviction buffer, and is favorable for reducing the area overhead of a chip.

Description

Processing system, processing method and electronic equipment

Technical Field

The present disclosure relates to the field of data storage technologies, and in particular, to a processing system, a processing method, and an electronic device.

Background

Caches are currently widely found in processors and systems on a chip. Caches are typically smaller in size, storing data that is accessed more frequently by the CPU, but at a much higher speed than memory, which can significantly increase the processing speed of the computing system. If the accessed data has been evicted from the on-chip cache, which again results in the need to access off-chip memory to re-update the data back to the on-chip cache, latency and power consumption are wasted. Typically some on-chip caches will add an eviction buffer to alleviate this. Adding a separate eviction buffer to the on-chip cache, which is equivalent to adding one more buffer area on the chip, will increase the overhead of the chip area.

Disclosure of Invention

The embodiment of the application provides a processing system, a processing method and electronic equipment. Various aspects of embodiments of the present application are described below.

In a first aspect, a processing system is provided, comprising: a processor; the cache is arranged between the processor and the off-chip memory and used for caching data in the off-chip memory, and comprises a cache data storage partition and an eviction buffer partition; wherein the buffer is configured to: in response to a first data in the cache data storage partition being evicted, storing the first data to the eviction buffer partition; in response to the second data in the eviction buffer partition being revisited, updating the cache data storage partition according to the second data.

In a second aspect, an electronic device is provided, comprising the processing system according to the first aspect, and an off-chip memory.

In a third aspect, a processing method is provided, which is applied to a processing system, where the processing system includes: a processor; the cache is arranged between the processor and the off-chip memory and used for caching data in the off-chip memory, and comprises a cache data storage partition and an eviction buffer partition; the processing method comprises the following steps: in response to a first data in the cache data storage partition being evicted, storing the first data to the eviction buffer partition; in response to the second data in the eviction buffer partition being revisited, updating the cache data storage partition according to the second data.

In a fourth aspect, there is provided a computer-readable storage medium having stored thereon a computer program for executing the processing method of the first aspect.

The embodiment of the application sets the eviction buffer partition on the cache, can buffer the evicted data, and avoids the performance loss and power consumption waste caused by short-term evicted data short-time off-chip memory access. According to the embodiment of the application, the independent eviction buffer is not required to be arranged, so that the area overhead of a chip is reduced.

Drawings

FIG. 1 is a schematic diagram of a memory system with independent eviction buffers.

Fig. 2 is a schematic diagram of a processing system provided in an embodiment of the present application.

FIG. 3 is a schematic diagram of one possible implementation of the processing system of FIG. 2.

Fig. 4 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.

Fig. 5 is a schematic flowchart of a processing method according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.

Caches are currently widely found in processors and systems on chip (SoC). Caches are also known as System Level Caches (SLC), on-chip caches, buffers, often simply caches. The cache is a storage unit located at a higher level in a computer storage hierarchy, and mainly functions as a bridge between a low-level storage unit and a Central Processing Unit (CPU), so as to reduce the time delay of the CPU for directly accessing data from the low-level storage unit (such as a main memory or a hard disk). Caches are typically smaller in size, storing data that is more frequently accessed by the CPU, but at a much higher speed than the memory, and exchanging data with the CPU prior to the memory can significantly increase the processing speed of the computing system.

The cache may be implemented by a volatile memory such as a Static Random Access Memory (SRAM) or a DRAM, or may be implemented by a Solid State Drive (SSD), a phase-change memory (PCM), a variable resistance memory (RRAM), or the like. The Cache generally comprises several independent Cache modules, including an instruction Cache (I-Cache), a data Cache (D-Cache), and a Translation Lookaside Buffer (TLB).

A system on chip, also called a system-on-chip, refers to a group of interconnected electronic circuits, which are integrated into a complete system on a single chip. Socs typically include, but are not limited to: hardware cores, memory, peripheral circuits, and communication interfaces. The hardware cores may include various different types of processors, such as general purpose processors, CPUs, digital Signal Processors (DSPs), graphics Processing Units (GPUs), accelerated Processing Units (APUs), auxiliary processors, single-core processors, and multi-core processors. In addition, the hardware cores may also be embodied in other hardware and combinations of hardware, such as Application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs), other programmable logic devices, split gate logic devices, transistor logic devices, performance monitoring hardware, watchdog hardware and timing references, and the like. An integrated circuit may be configured such that components of the integrated circuit are located on a single piece of semiconductor material (e.g., silicon).

Currently, processors usually have multiple levels of on-chip cache, which may be three levels, for example, so that data can be quickly looked up in the on-chip cache, avoiding long delays caused by accessing off-chip storage, which in turn causes long stalls or waiting of the processor pipeline. On-chip caches may not only reduce latency of memory access requests, but also may reduce power consumption penalties associated with accessing off-chip memory.

The working principle of the cache is as follows: when the processor executes the memory access instruction, a corresponding memory access request is generated. The memory access request is firstly received by the on-chip cache, and the on-chip cache searches the data stored by the on-chip cache according to the address of the memory access request. If the needed data is not found in the self storage, the memory access request can be continuously sent to the on-chip cache of the next level for searching the data. If none of the multi-level on-chip caches stores the needed data, then the relatively slower rate off-chip memory is accessed. The required data found in the off-chip memory is transferred into the cache, and the data block where the data is located is transferred into the cache, so that the whole data can be read from the cache in the future without transferring the off-chip memory. It is this read mechanism that makes the hit rate of the CPU read cache very high (most CPUs can reach about 90%), that is, 90% of the data to be read next time by the CPU is in the CPU cache, and only about 10% needs to be read from the memory.

Since on-chip caches are limited by area overhead, the capacity of each level of on-chip cache is limited. When the on-chip cache capacity is insufficient, replacement of data may occur. The newly accessed data in the on-chip cache updates old data that is evicted from the on-chip cache.

Since processor access requests do not necessarily have excellent temporal locality, i.e., the processor is not aware that the address most recently accessed by the program is likely to be accessed again in the near future. And the capacity of the on-chip cache is limited, the evicted data in the on-chip cache is likely to be accessed again in the near future. In this case, if the accessed data has been evicted from the on-chip cache and cannot be found, which would result in the need to access off-chip memory again to refresh the data back to the on-chip cache, a waste of latency and power consumption would result.

In addition, in the data circulation process, the data speeds of different layers are inconsistent. For example, when the cached data is written into the memory, the memory reads a small amount of data at regular intervals, which increases the number of I/O operations and reduces the efficiency of the CPU.

Therefore, some on-chip caches typically add a eviction buffer (VB) to mitigate this situation. The eviction buffer is also referred to as an eviction buffer, victim buffer, or discard buffer. Since the cache is a limited resource, the newly retrieved data may be displaced or evicted from the cache, the evicted entry also being referred to as a discard (victim). For example, a discarder of the L2 cache may be stored in the eviction buffer, and any discarder of the eviction buffer may be stored or discarded in a higher level cache.

FIG. 1 is a schematic diagram of a memory system with independent eviction buffers. As shown in fig. 1, the memory system may include a processor 110, a cache 120, an eviction buffer 130, and a double speed dynamic random access memory (DDR) 140. Data is evicted from cache 120 without being immediately written back to off-chip storage 140, but rather is first entered into eviction buffer 130. If the data is accessed again shortly after being evicted, the on-chip cache 120 is retrieved and updated directly from the eviction buffer 130, thus saving the overhead of accessing the off-chip storage 140.

Eviction buffer 130 may be utilized to alleviate speed issues between different memories. For example: when data in the cache 120 is written back to the DDR140, the data is written into the eviction buffer 130 first, and the DDR140 reads and writes from the eviction buffer 130 directly, which helps to reduce IO times, increase speed, and reduce wear.

With the development of miniaturization and miniaturization of chips, the allowable space occupied by components is very limited. The addition of a separately configured eviction buffer to the on-chip cache is equivalent to adding one more buffer on the chip, which inevitably increases the overhead of the on-chip area.

Therefore, how to develop a smaller-occupied-area eviction buffer scheme is a problem to be solved.

Based on this, this application embodiment proposes a processing system. Fig. 2 is a schematic diagram of a processing system provided in an embodiment of the present application. The processing system in the embodiment of the present application will be described in detail with reference to fig. 2. As shown in fig. 2, the processing system may include a processor 210 and a buffer 220.

The processor 210 is an operation and control core of the processing system, and is a final execution unit for information processing and program operation. Processor 210 may be a general-purpose processor including a central processing unit, a micro-control unit, a network processor, or other conventional processor. And may be a special purpose processor including a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components.

The processing system may also typically include off-chip memory. Off-chip memory may be understood as memory located outside of the die (die) where the application processor is located. That is, the off-chip memory and the integrated chip may be assigned to different die. When the chip is packaged, the die where the off-chip memory is located and the die where the integrated chip is located may be packaged in different chips or may be packaged in the same chip. The off-chip memory may be, for example, a Dynamic Random Access Memory (DRAM), a Flash memory (Flash). Among other things, DRAM may be used to store dynamic data during operation of the chip. Flash can also save data after the system is powered off, so that Flash can be used for saving mirror image programs and data which are expected to be saved continuously after the program is powered off. Of course, the off-chip memory may be other memories, such as Synchronous Dynamic Random Access Memory (SDRAM), double data rate SDRAM (DDR SDRAM), DDR2, DDR3, and so on. This is not particularly limited in the embodiments of the present application.

A buffer 220 is disposed between the processor 210 and the off-chip memory for buffering data in the off-chip memory. The buffer 220 may include a cache data storage partition 221 and an eviction buffer partition 222.

Cache data storage partition 221 is used to store data that is accessed more frequently by processor 210.

Eviction buffer partition 222 is used to store data evicted from cache data storage partition 221.

Upon data update and eviction, evicted data is not written back directly from the cache 220 to off-chip memory, but is moved into the partitioned eviction buffer partition 222 by the partition mode of the cache. The eviction buffer partition 222 may write data to off-chip memory together, concentrating the distributed write operations, thereby improving system performance.

The buffer 220 may be used to perform the following operations: in response to the first data in the cache data storage partition 221 being evicted, the first data is stored to the eviction buffer partition 222. In response to the second data in the eviction buffer partition 222 being re-accessed, the second data is retrieved from the eviction buffer partition 222, and the cache data storage partition 221 is updated according to the second data. As the processor runs, the data in cache data storage partition 221 will become data that is not accessed by processor 210 more recently, and the first data is any data or data segment in the cache data storage partition that is not accessed frequently in the near future. Part of the data in the eviction buffer partition 222 needs to be updated to the cache data storage partition 221 if it is re-accessed, and the second data is any data or data segment in the eviction buffer partition that is re-accessed. The eviction buffer partition can buffer recently evicted data, performance loss and power consumption waste caused by the fact that the recently evicted data go to the off-chip memory again in a short time are avoided, and expenditure caused by accessing the off-chip memory is saved.

The capacity of the eviction buffer partition 222 may be fixed or adjustable.

Different memory access modes need eviction buffers with different sizes, some memory access modes may not need to increase the eviction buffer, and some memory access modes need larger eviction buffers. The space of the preset independent eviction buffer is fixed and not flexible, and the space cannot meet the eviction buffer requirements of different application scenes. For example, if the eviction buffer space is set too large, it may cause a waste of area, and if it is too small, it may not achieve the expected buffering effect at all.

The cache 220 may dynamically adjust the capacity of the eviction buffer partition 222. In some implementations, eviction buffer partition 222 may not be partitioned for space capacity if no eviction buffer is needed in the current memory mode. If the current access mode requires an eviction buffer, the cache 220 allocates the appropriate capacity for the eviction buffer partition 222. The size of the eviction buffer partition 220 is dynamically adjusted, the capacity of the eviction buffer partition is reasonably configured, and the utilization efficiency of the eviction buffer partition is improved.

Optionally, the capacity of the eviction buffer partition 222 may be adjusted based on one or more of the following: the access mode of the cache 220; the data hit rate of the cache 220; the probability that data in eviction buffer partition 222 is revisited. According to the buffering requirement of the access scene, the capacity of the eviction buffer partition is dynamically adjusted, so that the higher utilization efficiency of the eviction buffer partition is achieved.

The access mode of the buffer 220 may include a bypass cache mode, a read pass-through mode, a write pass-through mode, an asynchronous cache write mode, and the like. For example, in a Read Through Pattern (RTP) suitable for a workload with a large read load, a large eviction buffer partition may be required when a large amount of different data is requested to be read.

In some embodiments, if the data hit rate of the buffer 220 is high, less off-chip memory data need to be read in and a smaller capacity eviction buffer partition 222 may be provided. In some embodiments, if the cache 220 has a low data hit rate and requires more off-chip memory data to be read, a larger eviction buffer partition 222 may be provided.

Alternatively, the capacity of eviction buffer partition 220 may be dynamically adjusted to achieve higher utilization efficiency, weighted by the fact that eviction buffer partition 222 data is being re-accessed. In some embodiments, eviction buffer partition 222 may be set to a smaller capacity because of a smaller probability that data will be revisited, and most of the data will be written back to off-chip memory for a short period of time.

There are several types of data in eviction buffer partition 222, some will be called back to cache data storage partition 221 by re-access, some will not be written back to off-chip memory by re-access, and some will be dirty data. Therefore, it is necessary to reasonably schedule and manage the data in the eviction buffer partition 222 to improve the utilization efficiency of the eviction buffer partition, and to set an appropriate capacity of the eviction buffer partition.

The data of the eviction buffer partition may be maintained according to a preset scheduling method, such as a First Input First Output (FIFO), a Least Recently Used (LRU), a random policy, and the like. FIFO refers to the removal of the data that entered first when the utilization of the eviction buffer partition reaches a certain threshold. LRU refers to the removal of the least used data over the last period of time.

When data is accessed in eviction buffer partition 222, cache data storage partition 221 is re-entered according to the cache replacement policy. Data is written back to off-chip memory if it is still evicted in eviction buffer 222.

Some of the data evicted by the buffer is dirty data that needs to be written back to off-chip memory. Dirty data refers to data that is read and changed during concurrent operations, but the changed data does not reach the external memory and then the changed data is canceled, which affects the accuracy of the result. In addition, data evicted by the buffer is often disordered, the scheduling of the off-chip memory is complex, and performance loss and power consumption waste caused by frequent switching of the off-chip memory may be caused.

In some implementations, the cache 220 may be used to perform the following operations: in response to a target dirty data in the eviction buffer partition needing to be written back to the off-chip memory, writing back to the off-chip memory a set of dirty data in the eviction buffer partition that contains the target dirty data, the dirty data in the set of dirty data belonging to a same physical page of the off-chip memory.

The portion of data may be reordered in the eviction buffer partition in a manner that facilitates off-chip storage to improve off-chip memory efficiency. For example, when a dirty data of the eviction buffer partition needs to be written back to the off-chip memory, the dirty data of the same physical page in the off-chip memory can be written back preferentially, which is helpful to reduce the overhead caused by page replacement of the off-chip memory, and can effectively improve the efficiency and performance of the off-chip memory.

The embodiment of the application does not need to set an independent eviction buffer, divides the eviction buffer partition on the cache, can buffer recently evicted data, and avoids the performance loss and power consumption waste caused by short-time evicted data removal of off-chip memory access. According to the embodiment of the application, because no independent eviction buffer is arranged, the area overhead of a chip is reduced.

FIG. 3 is a schematic diagram of one possible implementation of the processing system of FIG. 2. The processing system may include a processor 310, a buffer 320, and a DDR330.

The processor 310 is an operation and control core of the processing system, and is a final execution unit for information processing and program operation.

DDR330 is off-chip memory that may be used to store dynamic data during processor operation.

The buffer 320 is disposed between the processor 310 and the DDR330, and buffers data in the off-chip memory DDR330. The buffer 320 may include a cache data storage partition 321 and an eviction buffer partition 322.

Cache data storage partition 321 is used to store dynamic data that processor 210 accesses more frequently in the near future. Eviction buffer partition 322 is used to store data evicted from cache data storage partition 221.

Upon data update and eviction, evicted data is not written back to off-chip memory directly from the cache 320, but is moved into the partitioned eviction buffer partition 322 by the cached partition pattern. The eviction buffer partition 322, when writing data to the off-chip memory DDR330, typically writes to the DDR330 together, concentrating the scattered write operations, thereby improving system performance.

The buffer 320 may be used to perform the following operations: in response to the first data in the cache data storage partition 321 being evicted, the first data is stored to the eviction buffer partition 322. In response to the second data in the eviction buffer partition 322 being re-accessed, the second data is retrieved directly from the eviction buffer partition 322, and the cache data storage partition 321 is updated based on the second data. The eviction buffer partition can buffer recently evicted data, avoiding performance and power consumption waste caused by the evicted data being accessed again for a short time.

The capacity of the eviction buffer partition 222 may be fixed or adjustable.

Different memory access modes require eviction buffers of different sizes, some memory access modes may not need to increase the eviction buffer, and some memory access modes need more eviction buffers. The cache 320 may dynamically adjust the capacity of the eviction buffer partition 322. In some implementations, eviction buffer partition 322 may not be partitioned for space capacity if no eviction buffer is needed in the current access mode. If the current access mode requires an eviction buffer, the cache 320 allocates the appropriate capacity for the eviction buffer partition 322. The size of the eviction buffer partition is dynamically adjusted, the capacity of the eviction buffer partition is reasonably configured, and the utilization efficiency of the eviction buffer partition is improved.

Optionally, the capacity of the eviction buffer partition 322 may be adjusted based on one or more of the following: the access mode of the buffer 320; the data hit rate of the cache 320; the probability that the data in eviction buffer partition 322 is revisited. According to the requirement of accessing the scene, the capacity of the eviction buffer partition is dynamically adjusted to achieve higher utilization efficiency.

The data in the eviction buffer partition 322 may be of various types, some will be brought back into cache by re-access, some will not need to be written back to off-chip memory by re-access, and some will be dirty data. Therefore, it is desirable to properly schedule and manage data in eviction buffer partition 322 to improve the utilization efficiency of the eviction buffer partition.

The data of the eviction buffer partition can be maintained according to a preset scheduling method. For example, when data is accessed in eviction buffer partition 322, cache data storage partition 321 may be re-entered according to the replacement policy of the cache. Data is written back to off-chip memory if it is still evicted in the eviction buffer partition 322.

Some of the data evicted by the on-chip cache is dirty data, which needs to be written back to off-chip storage. The portion of data may be reordered in the eviction buffer partition in a manner that facilitates off-chip storage to improve off-chip memory efficiency. For example, when a dirty data of the eviction buffer partition needs to be written back to the off-chip memory, the dirty data of the same physical page in the off-chip memory can be written back preferentially, which is helpful for reducing extra overhead caused by page replacement of the off-chip memory, and the like, and can effectively improve efficiency and performance of the off-chip memory.

With regard to the implementation effect of the embodiment of the application, the delay condition can be monitored and checked by setting a data access mode in which eviction occurs frequently but eviction data is accessed for a short time. If the delay does not drop significantly, an eviction buffer may be employed and the capacity of the eviction buffer is set reasonably.

The embodiment of the application does not need to set up independent eviction buffer, divides the eviction buffer partition on the cache, and dynamically adjusts the capacity of the eviction buffer partition, so that the recently evicted data can be buffered, and the performance loss and power consumption waste caused by the short-time evicted data access to the off-chip memory are avoided. The embodiment of the application is favorable for reducing the area overhead of the chip, dynamically adjusting the capacity of the eviction buffer partition and improving the utilization efficiency of the eviction buffer partition.

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device 400 may include a processing system 410 as described in any of the previous paragraphs, and an off-chip memory 420.

Off-chip memory 420 is used to store dynamic data during operation of processing system 410; and can also be used to save mirrored programs and data that can be saved further after the program is powered down. The off-chip memory 420 may be, for example, a DRAM, a flash memory, an SDRAM, and a DDR, which is not specifically limited in this embodiment.

Off-chip memory 420 may include one or more memories.

Embodiments of the processing system and apparatus of the present application are described in detail above in conjunction with fig. 1-4, and embodiments of the method of the present application are described in detail below in conjunction with fig. 5. It is to be understood that the description of the method embodiments corresponds to the description of the system embodiments, and therefore reference may be made to the previous system embodiments for portions that are not described in detail.

Fig. 5 is a schematic flowchart of a processing method according to an embodiment of the present application. The processing method of fig. 5 is applied to a processing system, which may include a processor and a buffer. The cache is arranged between the processor and the off-chip memory and used for caching data in the off-chip memory, and comprises a cache data storage partition and an eviction buffer partition.

As shown in fig. 5, the processing method may mainly include steps S510 to S520, which are described in detail below. It should be noted that the division of steps in the method is for convenience of description, and there is no time or control over the division of time between steps in the method.

In step S510, in normal operation of the cache, in response to the first data in the cache data storage partition being evicted, the first data is stored to the eviction buffer partition.

In response to the second data in the eviction buffer being revisited, the second data is retrieved from the eviction buffer and the cache data storage partition is updated according to the second data, step S520.

Alternatively, the capacity of the eviction buffer partition may be dynamically adjusted.

Optionally, the capacity of the eviction buffer partition may be adjusted based on one or more of: the access mode of the buffer; the data hit rate of the cache; the probability of data in the eviction buffer being revisited.

Optionally, the processing method further includes: in response to the target dirty data in the eviction buffer partition needing to be written back to the off-chip memory, writing back to the off-chip memory a set of dirty data in the eviction buffer partition that contains the target dirty data, the dirty data in the set of dirty data belonging to a same physical page of the off-chip memory.

Embodiments of the present application further provide a computer-readable storage medium, on which a computer program is stored, where the computer program is used to execute the processing method described in any one of the foregoing descriptions.

In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware or any other combination. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions described in accordance with the embodiments of the disclosure are all or partially produced when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a machine-readable storage medium or transmitted from one machine-readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The machine-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Video Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

It should be understood that, in the various embodiments of the present application, "first", "second", and the like are used for distinguishing different objects, and are not used for describing a specific order, the order of execution of the above-mentioned processes is not meant to imply any order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not be construed as limiting the implementation processes of the embodiments of the present application.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, apparatus, and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

In the several embodiments provided in this application, it should be understood that when a portion is referred to as being "connected" or "coupled" to another portion, it is intended that the portion can be not only "directly connected," but also "electrically connected," with another element interposed therebetween. In addition, the term "connected" also means that the parts are "physically connected" as well as "wirelessly connected". In addition, when a portion is referred to as "comprising" an element, it is meant that the portion may include another element without precluding the other element, unless otherwise stated.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (10)

1. A processing system, comprising:

a processor;

the cache is arranged between the processor and the off-chip memory and used for caching data in the off-chip memory, and comprises a cache data storage partition and an eviction buffer partition;

wherein the buffer is configured to:

in response to a first data in the cache data storage partition being evicted, storing the first data to the eviction buffer partition;

in response to the second data in the eviction buffer partition being revisited, updating the cache data storage partition according to the second data.

2. The processing system of claim 1, wherein the cache is to dynamically adjust a capacity of the eviction buffer partition.

3. The processing system of claim 2, wherein the capacity of the eviction buffer partition is adjusted based on one or more of:

the access mode of the buffer;

a data hit rate of the cache;

a probability of data in the eviction buffer partition being revisited.

4. The processing system of claim 2, wherein the buffer is further configured to:

in response to a target dirty data in the eviction buffer partition needing to be written back to the off-chip memory, writing back a set of dirty data in the eviction buffer partition that includes the target dirty data to the off-chip memory, the dirty data in the set of dirty data belonging to a same physical page of the off-chip memory.

5. An electronic device comprising the processing system of any of claims 1-4, and an off-chip memory.

6. A processing method applied to a processing system, the processing system comprising:

a processor;

the cache is arranged between the processor and the off-chip memory and used for caching data in the off-chip memory, and comprises a cache data storage partition and an eviction buffer partition;

the processing method comprises the following steps:

in response to a first data in the cache data storage partition being evicted, storing the first data to the eviction buffer partition;

in response to the second data in the eviction buffer partition being revisited, updating the cache data storage partition according to the second data.

7. The processing method according to claim 6, characterized in that it comprises:

dynamically adjusting a capacity of the eviction buffer partition.

8. The processing method of claim 7, wherein the capacity of the eviction buffer partition is adjusted based on one or more of:

the access mode of the buffer;

a data hit rate of the cache;

a probability that data in the eviction buffer partition is revisited.

9. The processing method according to claim 7, characterized in that it further comprises:

in response to a target dirty data in the eviction buffer partition needing to be written back to the off-chip memory, writing back a set of dirty data in the eviction buffer partition that includes the target dirty data to the off-chip memory, the dirty data in the set of dirty data belonging to a same physical page of the off-chip memory.

10. A computer-readable storage medium, characterized in that a computer program is stored thereon for performing the processing method of any one of claims 6-9.

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