CN115729368A

CN115729368A - Time sequence control circuit and time sequence control method

Info

Publication number: CN115729368A
Application number: CN202210479533.7A
Authority: CN
Inventors: 郑焕腾
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2021-08-31
Filing date: 2022-05-05
Publication date: 2023-03-03
Also published as: TWI817484B; TW202312119A

Abstract

The application discloses a timing control circuit which comprises a receiving circuit and a line memory coupled to the receiving circuit. The line memory is used for outputting a first data signal during a first frame period and outputting a second data signal during a second frame period. Wherein the ending time point of the first frame period coincides with the starting time point of the second frame period. One of the first data signal and the second data signal corresponds to a long horizontal scanning pause mode, and the other one of the first data signal and the second data signal corresponds to a long vertical scanning pause mode.

Description

Time sequence control circuit and time sequence control method

Technical Field

The present disclosure relates to timing control circuits and methods, and particularly to a timing control circuit and a method for improving display quality and reliability.

Background

In a touch and display driver integrated circuit (TDDI), display operation and touch operation are performed in a time-sharing manner to avoid noise interference from affecting touch sensing or generating an erroneous display result. There is still room for improvement in the operation of touch and display driver integrated circuits in order to improve display quality and reliability.

Disclosure of Invention

Therefore, the present application mainly provides a timing control circuit and a timing control method thereof to improve display quality and reliability.

The application discloses a sequential control circuit, which comprises a receiving circuit; and a line memory coupled to the receiving circuit, wherein the line memory is used for outputting a first data signal during a first frame; and outputting a second data signal during a second frame period, wherein an ending time point of the first frame period coincides with a starting time point of the second frame period, one of the first data signal and the second data signal corresponds to a long horizontal scanning pause mode, and the other one of the first data signal and the second data signal corresponds to a long vertical scanning pause mode.

The application also discloses a time sequence control method, which comprises the steps of outputting a first data signal during a first frame period; and outputting a second data signal during a second frame period, wherein an ending time point of the first frame period coincides with a starting time point of the second frame period, one of the first data signal and the second data signal corresponds to a long horizontal scanning pause mode, and the other one of the first data signal and the second data signal corresponds to a long vertical scanning pause mode.

Drawings

Fig. 1 is a schematic diagram of a touch display device according to an embodiment of the present application.

Fig. 2 is a timing diagram according to an embodiment of the present application.

Fig. 3 and 4 are partially enlarged schematic views of fig. 2.

Fig. 5 to 7 are timing diagrams of the present application, respectively.

Wherein the reference numerals are as follows:

10. touch display device

100. Video packet streaming

110. Driving circuit

111. Sequential control circuit

111a receiver circuit

111b line memory

111c timing generation circuit

111d oscillating circuit

112. Source driver

113. Gate driver

114. Touch circuit

120. Touch display panel

122. Touch electrode

122S, 122S1a-122S10b, 122S1c,122S2c touch signals

BLLP Low Power Blanking period

Delay of DL2 to DL4

Frames F1-F4, F12-F14, F22, F23

FP 1-FP 3, FP12, FP13 frame period

FP2DP, FP2DPr display operation period

FP2TP touch operation period

FP3DP 1-FP 3DP10, FP2DP 1-FP 2DPn display operator period

FP3TP 1-FP 3TP10 touch operation sub-period

HBP horizontal back porch

HFP horizontal leading edge

HS horizontal synchronous start

Hsync1 external horizontal synchronization signal

Hsync2 internal horizontal synchronization signal

LPM low power

RGB horizontal sync pulse line period

tL1 to tL3, tL2', tL3', tL12 to tL14 horizontal periods

tVBP2, tVBP3, tVBP2', tVBP3', tVBP13' vertical back porch time

tVFP2, tVFP3, tVFP2', tVFP3', tVFP12' vertical front porch time

VS vertical sync end

Vsync1 external vertical synchronization signal

Detailed Description

Fig. 1 is a schematic diagram of a touch display device 10 according to an embodiment of the present disclosure. The touch display device 10 includes a driving circuit 110 and a touch display panel 120. The driving circuit 110 may receive a video packet stream (video packet stream) 100 from a previous stage (not shown) (e.g., a processor, etc.) via a transmission interface. In a horizontal period (also referred to as 1H or line time) in which different frames of the video packet stream 100 may correspond to different time lengths, the driving circuit 110 can switch between a long horizontal scan pause mode (long H mode) and a long vertical scan pause mode (long V mode) to ensure display quality.

In detail, the driving circuit 110 may include a timing control circuit 111, a source driver 112, a gate driver 113, and a touch circuit 114. The timing control circuit 111 receives the video packet stream 100. The timing control circuit 111 may provide a vertical start signal or a gate clock signal to the gate driver 113 according to the video packet stream 100, so that the gate driver 113 may drive at least one gate line (not shown) of the touch display panel 120. The timing control circuit 111 may provide a vertical synchronization signal, a horizontal start signal, or a data signal to the source driver 112 according to the video packet stream 100, so that the source driver 112 may drive at least one data line (not shown) of the touch display panel 120. The timing control circuit 111 can control the touch circuit 114 such that the touch circuit 114 can provide a touch signal to drive at least one touch electrode 122 of the touch display panel 120.

The timing control circuit 111 may include a receiving circuit 111a, a line memory 111b, a timing generation circuit 111c, and an oscillation circuit 111d. Referring to fig. 1 to 4 together, fig. 2 is a timing diagram of an embodiment of the present application, and fig. 3 and 4 are partially enlarged diagrams of fig. 2, respectively.

The receiving circuit 111a may be configured to receive the video packet stream 100. In one embodiment, the receiving circuit 111a decodes the video packet stream 100 to generate the external vertical synchronization signal Vsync1, the external horizontal synchronization signal Hsync1, or the original data signal shown in fig. 2. The external vertical synchronization signal Vsync1 is used to indicate the start or end of one frame. As shown in fig. 2, the external horizontal synchronization signal Hsync1 may have a plurality of pulses (or lines) in one frame (e.g., one of the frames F1 to F4). The period of one pulse is one horizontal period (e.g., horizontal periods tL1, tL2, tL 3). The horizontal period (e.g., horizontal period tL 2) of each pulse of one frame (e.g., frame F2) is the same, but the horizontal periods (e.g., horizontal periods tL2, tL 3) of different frames (e.g., frames F2, F3) may be different.

The oscillating circuit 111d can be used to provide the internal clock signal to the timing generating circuit 111c or the touch circuit 114.

The timing generation circuit 111c is operable to receive the external horizontal synchronization signal Hsync1 from the reception circuit 111a, and convert the external horizontal synchronization signal Hsync1 into an internal horizontal synchronization signal Hsync2 based on the internal frequency signal from the oscillation circuit 111d. The timing generation circuit 111c is used to detect the time length of the horizontal period (e.g., the horizontal periods tL1 to tL 3) of the external horizontal synchronization signal Hsync1 to determine whether to switch to the long horizontal scan pause mode or the long vertical scan pause mode.

In one embodiment, the line memory 111b may be used to receive an external vertical synchronization signal Vsync1, an external horizontal synchronization signal Hsync1, or a raw data signal from the receiving circuit 111a, and may write pixel data (e.g., a raw data signal) into the line memory 111b according to the external horizontal synchronization signal Hsync 1. The line memory 111b may be configured to receive the internal horizontal synchronization signal Hsync2 from the timing generation circuit 111c, and may provide pixel data (e.g., a first data signal output by the FP2 during a frame period or a second data signal output by the FP3 during the frame period) to the source driver 112 according to the internal horizontal synchronization signal Hsync2. The first data signal and the second data signal can correspond to different scan pause modes. For example, the first data signal may correspond to a long vertical scan pause mode, and the second data signal may correspond to a long horizontal scan pause mode.

In short, the timing generation circuit 111c can be used to determine whether the time lengths of the external horizontal synchronization signal Hsync1 in the horizontal periods (e.g., the horizontal periods tL1 to tL 3) of two consecutive frames are the same. Based on the difference in time length between the horizontal periods tL2, tL3, the first data signal and the second data signal correspond to different ones of the long horizontal scanning pause mode and the long vertical scanning pause mode, respectively. Based on the absence of the time length difference between the horizontal periods tL1, tL2, the data signal output during the frame period FP1 corresponds to the same one of the long horizontal scanning pause mode and the long vertical scanning pause mode as the second data signal output during the frame period FP 2.

For example, the receiving circuit 111a receives a first external signal of the video packet stream 100 in the frame F2, extracts the external horizontal synchronization signal Hsync1 in the horizontal period tL2 of the frame F2 and the original data signal of the frame F2 from the first external signal, and writes the original data signal into the line memory 111b according to the external horizontal synchronization signal Hsync 1. Accordingly, the line memory 111b can provide the first data signal to the source driver 112 during the frame period FP2 according to the internal horizontal synchronization signal Hsync2. The frame period FP2 corresponds to the frame F2 and has the same time length as the frame F2. Also, the first data signal may correspond to a long vertical scan pause mode based on the horizontal period tL2 being short. Based on the horizontal period tL1 being equal to the horizontal period tL2, the data signal and the first data signal output by the FP1 during the frame period may both correspond to the long vertical scan pause pattern.

As shown in fig. 2, in the long vertical scan pause mode, the frame period FP2 is divided into a display operation period FP2DP and a touch operation period FP2TP. The display operation period FP2DP is used to output the pixel data to the touch display panel 120, and a consecutive one of the display operation periods FP2DP is used for all display operations of one frame. The FP2TP is used to transmit the touch signal 122S during the touch operation, and the scanning of the touch electrode 122 is continuously performed, and the touch signal 122S shown in fig. 3 is transmitted during the continuous touch operation FP2TP. The long vertical scan pause mode may perform the touch operation after the pixel data corresponding to all the gate lines are output, that is, the touch operation is performed after the display operation of a complete frame is completed. Since the display operation is continuously performed, display stripes in the long horizontal scan pause mode can be avoided and reliability (reliability) can be improved.

Similarly, the receiving circuit 111a receives the second external signal of the video packet stream 100 in the frame F3, extracts the external horizontal synchronization signal Hsync1 from the second external signal in the horizontal period tL3 of the frame F3 and the original data signal of the frame F3, and writes the original data signal into the line memory 111b according to the external horizontal synchronization signal Hsync 1. Accordingly, the line memory 111b can provide the second data signal to the source driver 112 during the frame period FP3 according to the internal horizontal synchronization signal Hsync2. The frame period FP3 corresponds to the frame F3 and has the same time length as the frame F3. Also, the second data signal may correspond to a long horizontal scanning pause mode based on the horizontal period tL3 being longer (compared to the horizontal period tL 2).

In the long horizontal scan pause mode, the frame period FP3 is divided into a plurality of time units (e.g., 10 time units). Each time unit has a display operation sub-period and a touch operation sub-period. The display operation sub-periods FP3DP 1-FP 3DP10 are used to output pixel data to the touch display panel 120. The touch operation sub-periods FP3TP1 to FP3TP10 are used to transmit touch signals. For example, the touch signals 122S1a to 122S10b shown in fig. 4 may be transmitted in the intermittent touch operation sub-periods FP3TP1 to FP3TP10, respectively, and since the time length of one touch operation sub-period cannot be too long, only a part of the touch electrodes 122 (e.g., one row (column)/one column (row) or several rows/columns of touch electrodes 122) are driven in one touch operation sub-period. One touch operation sub-period can be inserted between two adjacent display operation sub-periods. That is, in the long horizontal scan pause mode, the display operation sub-periods FP3DP1 to FP3DP10 and the touch operation sub-periods FP3TP1 to FP3TP10 are staggered with each other. That is, in the long horizontal scanning pause mode, the display operation may be paused for a long horizontal scanning pause period (i.e., one touch operation sub-period) after a fixed number of gate lines are driven (or pixel data corresponding to the gate lines are output) in order to perform the touch operation.

During the touch operation sub-period (e.g., the touch operation sub-period FP3TP 1), the pixel data written into the line memory 111b is read out from the line memory 111b during the next display operation sub-period (e.g., the display operation sub-period FP3DP 2) in response to the internal horizontal synchronization signal Hsync2. In one embodiment, the data lines FP3TP 1-FP 3TP10 are not necessarily equal to 0 volt (volt) during the touch operation sub-period, and the data lines may have a waveform with the same voltage difference/phase as the touch signal to reduce the load (Loading) (i.e., no load drive (LFD)) of the touch signal.

In the long horizontal scan pause mode, a long horizontal scan pause period usually occurs on the same gate line, so that the driving time of the gate line is much longer than that of other gate lines, and therefore, the decay rate of the circuit elements (e.g., thin film transistors) on the gate line is faster than that of the circuit elements on other gate lines, resulting in poor display efficiency of the gate line. For example, long-time turning on of thin film transistors on certain gate lines may cause the gate lines to be degraded, which may result in unrecoverable display stripes (also referred to as horizontal lines, longH stripes, or horizontal gate line stripes) on the touch display panel 120. By switching between the long horizontal scanning pause mode and the long vertical scanning pause mode, the touch display panel 120 can be prevented from generating unrecoverable display horizontal stripes.

High frame rate and low frame rate

In one embodiment, the long vertical scan pause mode may be employed at a High Frame Rate (HFR) and the long horizontal scan pause mode may be employed at a Low Frame Rate (LFR). For example, the frame period FP2 may be 8.33 milliseconds (ms), and the frame rate (refresh rate or frame rate or display frame rate) is the reciprocal of the frame period, so the frame rate corresponding to the frame period FP2 may be 120 Hertz (Hz), for example. The frame period FP3 may be, for example, 16.67 milliseconds, and the frame rate may be, for example, 60Hz. Based on the frame period FP2 of the first data signal being smaller than the frame period FP3 of the second data signal (i.e., the frame periods FP2 and FP3 correspond to the high frame rate and the low frame rate, respectively), the first data signal corresponds to the long vertical scanning pause mode, and the second data signal corresponds to the long horizontal scanning pause mode. The long vertical scan pause mode at the high frame rate can prevent the touch display panel 120 from generating unrecoverable display stripes when the horizontal period tL2 is short.

In an embodiment, based on the frame period FP2 of the first data signal being smaller than the frame period FP3 of the second data signal, the first data signal corresponds to the long vertical scan pause mode, and the second data signal corresponds to the long horizontal scan pause mode and the extended horizontal scan pause mode (extended H mode). The number of pulses (i.e., line count) corresponding to the frame period FP3 of the extended horizontal scanning pause mode does not change (e.g., is equal to the number of pulses of the frame period FP 2), on the other hand, the horizontal period tL3 corresponding to the extended horizontal scanning pause mode is longer (e.g., is greater than the horizontal period tL 2), and the frame period FP3 corresponding to the extended horizontal scanning pause mode is longer (e.g., is greater than the frame period FP 2), so that the frame period FP3 corresponds to a low frame rate (e.g., is lower than the frame rate corresponding to the frame period FP 2). In the extended horizontal scan pause mode, the Vertical blank period of the display operation is not less than one-half of the frame period FP3, wherein the Vertical blank period of one frame may include a Vertical Front Porch (VFP), a Vertical Back Porch (VBP) time, or a Vertical synchronization time corresponding to the external Vertical synchronization signal Vsync 1. The vertical front porch time tVFP3' of FP3 during a frame period in the extended horizontal scanning pause mode is not excessively long, so that the problem of a splash screen can be avoided. In addition, the horizontal period tL3 corresponding to the extended horizontal scan pause mode is long, so that the voltage is relatively easy to reach a predetermined level.

In another embodiment, the second data signal may also correspond to an extended vertical edge mode (extended Vproch mode). In the extended vertical edge mode, the vertical blank period of one frame is long, so that the non-driving time of each gate line is long, and the circuit elements (such as thin film transistors) on the gate lines are not turned on for a long time, so that the potential of the liquid crystal capacitor is reduced to affect the expected gray scale value. In the next frame, the circuit elements on the gate lines are turned on again and the liquid crystal capacitors are charged to adjust to the desired gray level, so that the touch display panel 120 may have a screen flash problem.

Touch point reporting rate

In an embodiment, the frame period FP2 is not equal to the frame period FP3, but the touch report rate corresponding to the frame period FP2 may be equal to a touch report rate (touch report rate or touch frame rate) corresponding to the frame period FP3. For example, the frame period FP2 and the frame period FP3 may be 8.33 milliseconds and 16.67 milliseconds, respectively, so that the frame rates are 120Hz and 60Hz, respectively, but the touch hit rates may be 120Hz, for example.

Specifically, in the long vertical scan pause mode, the touch hit rate may be equal to the frame rate. Therefore, all display operations of one frame are performed during one frame period (e.g., the frame period FP 2), and the touch operation may scan the touch display panel 120 once. For example, the touch electrode 122 is driven with the touch signal 122S only during the touch operation FP2TP.

In the long horizontal scan pause mode, the touch hit rate may not be equal to the frame rate, and the touch hit rate may be equal to an integer multiple (integer multiple) or fractional multiple (fractional multiple) of the frame rate. Therefore, all display operations of one frame are performed during one frame period (e.g., the frame period FP 3), and the touch operations may scan the entire touch display panel 120 an integer number of times or a non-integer number of times. For example, touch display panel 120 may include 10 rows (or 10 columns) of touch electrodes 122. The touch sub-periods FP3TP1 to FP3TP5 may be used to perform a first scan of the touch electrodes 122 from row 1 (column) to row 10 (column), and the touch sub-periods FP3TP6 to FP3TP10 may be used to perform a second scan of the touch electrodes 122 from row 1 (column) to row 10 (column). For example, the touch electrode 122 of the 1 st row (column) is driven by the touch signal 122S1a during the touch operation sub-period FP3TP1, and the touch electrode 122 of the 1 st row (column) is driven by the touch signal 122S1b during the touch operation sub-period FP3TP 6. That is, the touch operation may scan the entire touch display panel 120 twice. Accordingly, the long horizontal scanning pause mode can achieve a touch hit rate different from the frame rate.

In short, by switching between the long horizontal scanning pause mode and the long vertical scanning pause mode, even though the frame period FP2 is not equal to the frame period FP3, the frame rate corresponding to the frame period FP2 is not equal to the frame rate corresponding to the frame period FP3, but the touch hit rate corresponding to the frame period FP2 may be equal to the touch hit rate corresponding to the frame period FP3.

In one embodiment, the touch hit rate may be maintained at 120Hz when switching from the high frame rate (e.g., 120 Hz) to the low frame rate (e.g., 40 Hz), but the application is not limited thereto. In another embodiment, when switching from a high frame rate (e.g., 120 Hz) to a low frame rate (e.g., 40 Hz), the touch hit rate may vary depending on different design considerations (e.g., 120Hz to 60 Hz).

Delay

In one embodiment, in the long vertical scan pause mode, the pixel data may not be written to the line memory 111b. In another embodiment, the line memory 111b may be utilized for switching between the long horizontal scanning pause mode and the long vertical scanning pause mode. That is, in the long horizontal scanning pause mode, the pixel data may be written to the line memory 111b to extract a period used in the touch operation. Correspondingly, in the long vertical scan pause mode, the pixel data is also written into the line memory 111b.

Specifically, please refer to fig. 1 and fig. 4. In the long horizontal scan pause mode, the frequency of the internal horizontal synchronization signal Hsync2 may be higher than the frequency of the external horizontal synchronization signal Hsync 1. The receiving circuit 111a may write pixel data (e.g., raw data signals) into the line memory 111b in accordance with an external horizontal synchronization signal Hsync 1. Also, the pixel data can be read out from the line memory 111b at a faster data rate according to the internal horizontal synchronization signal Hsync2 during the frame period FP3. Therefore, the time for displaying the operation can be compressed, and the time period used for the touch operation is extracted.

As shown in fig. 4, the horizontal period tL3' corresponding to the display operation sub-period FP3DP1 is smaller than the horizontal period tL3 of the external horizontal synchronization signal Hsync1, so that the touch operation sub-period FP3TP1 used in the touch operation can be extracted. The horizontal period tL3 of the external horizontal synchronization signal Hsync1 may correspond to a time for writing pixel data corresponding to one gate line into the line memory 111b. The horizontal period tL3' may be a period time for applying a voltage to one column (row) of pixels of the touch display panel 120 (i.e., a time length between a start time point for applying a voltage to one column (row) of pixels and a start time point for applying a voltage to the other column (row) of pixels), that is, a period time for driving one gate line (i.e., a time length between a start time point for driving one gate line and a start time point for driving the other gate line). The horizontal period tL3' may correspond to a time when pixel data corresponding to one gate line is read out from the line memory 111b.

For example, in the long horizontal scan pause mode, the receiving circuit 111a can write the received pixel data corresponding to 20 gate lines into the line memory 111b in a time unit according to the external horizontal synchronization signal Hsync 1. The internal horizontal synchronization signal Hsync2 can be used to control the pixel data corresponding to 20 gate lines to be read out from the line memory 111b at a faster data rate and forwarded to the touch display panel 120, so as to perform the display operation of the pixel data corresponding to 20 gate lines in one display operation sub-period (e.g., the display operation sub-period FP3DP 1). That is, the number of pixel data received in a time unit is equal to the number of pixel data output in a time unit of the sub-period of the display operation.

For example, in the long horizontal scan pause mode, a specific amount of pixel data (e.g., pixel data corresponding to gate lines from row 1 to row 20) may be output to the touch display panel 120 in response to the internal horizontal synchronization signal Hsync2 during a display operation sub-period (e.g., the display operation sub-period FP3DP 1), and then, the touch operation sub-period (e.g., the touch operation sub-period FP3TP 1) is entered, and other pixel data (e.g., pixel data corresponding to gate lines from row 21 to row 27) are continuously written (temporarily stored) in the line memory 111b in response to the external horizontal synchronization signal Hsync1 during the touch operation sub-period FP3TP1. In addition, the pixel data (pixel data corresponding to the gate lines in the 21 st to 27 th columns) written into the line memory 111b will be read out from the line memory 111b in response to the internal horizontal synchronization signal Hsync2 in the next display operation sub-period (e.g., the display operation sub-period FP3DP 2), and other pixel data (e.g., pixel data corresponding to the gate lines in the 28 th to 40 th columns) will be written into the line memory 111b in response to the external horizontal synchronization signal Hsync1 in the display operation sub-period FP3DP2 and output to the touch display panel 120 in response to the internal horizontal synchronization signal Hsync2.

In the long horizontal scan pause mode, since part of the pixel data (e.g., the pixel data corresponding to the gate lines from the 1 st row (row) to the 7 th row (row)) needs to be written (temporarily stored) in the line memory 111b before the display operation sub-period (e.g., the display operation sub-period FP3DP 1), there may be a delay DL3 between (the frame F3 of) the external horizontal synchronization signal Hsync1 and (the frame FP3 of) the internal horizontal synchronization signal Hsync2, as shown in fig. 2. The delay DL3 may be greater than or equal to the writing time of the pixel data that needs to be written into the line memory 111b first, so as to avoid the need to read out the pixel data that has not been written into the line memory 111b during the display operation sub-period (e.g., the display operation sub-period FP3DP 1). For example, in the sub-period of the touch operation (e.g., the sub-period FP3TP 1) corresponding to 50 lines (i.e., writing the pixel data corresponding to 50 gate lines into the line memory 111 b), the line memory 111b may store the pixel data corresponding to 100 rows of gate lines, and the number of lines corresponding to the delay DL3 may be greater than or equal to 50 and less than 100.

In one embodiment, in the long vertical scan pause mode, as shown in fig. 2, there may be a delay DL2 between (the frame F2 of) the external horizontal synchronization signal Hsync1 and (the frame period FP2 of) the internal horizontal synchronization signal Hsync2. In one embodiment, in order to dynamically switch between the long horizontal scan pause mode and the long vertical scan pause mode, in the long vertical scan pause mode, as shown in fig. 2, there may be a delay DL4 between (the frame F4 of) the external horizontal synchronization signal Hsync1 and (the frame period FP4 of) the internal horizontal synchronization signal Hsync2.

In one embodiment, the delays DL2, DL3, DL4 between the external horizontal synchronization signal Hsync1 and the internal horizontal synchronization signal Hsync2 may correspond to the same number of lines (or pulses). For example, the delays DL2, DL3, DL4 may correspond to 50 lines, respectively. In one embodiment, delay DL2 is proportional to horizontal period tL2, delay DL3 is proportional to horizontal period tL3, and the ratio between delay DL2 and delay DL3 is equal to the ratio between horizontal period tL2 and horizontal period tL 3. In one embodiment, since the horizontal period tL2 is smaller than the horizontal period tL3, the time length of the delay DL3 may be longer than the time length of the delay DL2. In another embodiment, the number of lines corresponding to the delay DL2, DL4 may be greater than the number of lines corresponding to the delay DL3.

Detecting touch events or touch locations

In the long vertical scan pause mode, as shown in fig. 3, at the vertical leading edge time tVFP2' corresponding to FP2TP during the touch operation, the timing generation circuit 111c may control the touch circuit 114 to drive (time-share) the touch electrodes 122 of the touch display panel 120 so as to sense/detect the touch event and/or the touch position occurring on the touch display panel 120.

In another embodiment, in the long vertical scan pause mode, the time of the display operation may be compressed in order to further extract the period of time used in the touch operation. Referring to fig. 5, fig. 5 is a timing diagram according to an embodiment of the present application. As shown in fig. 5, the touch operation may be performed during the touch operation sub-periods FP2TP1 and FP2TP2, wherein the touch operation sub-period FP2TP2 corresponds to the vertical front porch time tVFP2', which is equivalent to the touch operation period FP2TP shown in fig. 3.

Specifically, in the long vertical scan pause mode, the frequency of the internal horizontal synchronization signal Hsync2 may be higher than the frequency of the external horizontal synchronization signal Hsync 1. The receiving circuit 111a may write pixel data (e.g., raw data signal) into the line memory 111b in accordance with an external horizontal synchronization signal Hsync 1. Also, the pixel data can be read out from the line memory 111b at a faster data rate during the frame period FP2 according to the internal horizontal synchronization signal Hsync2.

For example, in the long vertical scan pause mode, the time length of one display operation sub-period (e.g., the display operation sub-period FP2DP 1) corresponds to 32 horizontal periods tL2 '(corresponding to 32 pulses/line number) of the internal synchronization signal Hsync2 or 31 horizontal periods tL2' (corresponding to 31 pulses/line number) of the external horizontal synchronization signal Hsync 1. During a display operation sub-period (e.g., the display operation sub-period FP2DP 1), the receiving circuit 111a can write the received pixel data corresponding to 31 gate lines into the line memory 111b according to the external horizontal synchronization signal Hsync 1. Also, the pixel data corresponding to the 32 gate lines can be read out from the line memory 111b at a faster data rate according to the internal horizontal synchronization signal Hsync2 during the frame period FP 2.

In the long vertical scan pause mode, if 32 horizontal periods tL2' of the internal synchronization signal Hsync2 (corresponding to one display operation sub-period) are equivalent to 31 horizontal periods tL2 of the external horizontal synchronization signal Hsync1, and the display operation period FP2DPr can be divided into n (e.g., 45) display operation sub-periods FP2DP1 to FP2DPn, the display operation period FP2DPr is less than n (e.g., 45) horizontal periods tL2 of the external horizontal synchronization signal Hsync1 than the display operation period FP2DP shown in fig. 3, and can be used as the touch operation sub-period FP2TP1.

In other words, in the long vertical scan pause mode, as shown in fig. 5, the touch operation may be performed in the touch operation sub-period FP2TP1 and the touch operation sub-period FP2TP2 corresponding to the vertical front edge time tVFP 2'. During the touch operation sub-periods FP2TP1, FP2TP2, the timing generation circuit 111c may control the touch circuit 114 to drive (time-share) the touch electrodes 122 of the touch display panel 120 so as to sense/detect the touch event and/or the touch position occurring on the touch display panel 120. For example, the touch signal 122S1c of FIG. 5 can be utilized to drive the touch electrode 122 of row 1 (column), and the touch signal 122S2c of FIG. 5 can be utilized to drive the touch electrode 122 of row 2 (column). In the case of performing a touch operation using the touch operation sub-period FP2TP1, the vertical front porch time tVFP2' (or the number of lines of the vertical front porch) can be shortened, the bit rate (bit rate) can be reduced, the required bandwidth can be reduced, and power consumption can be saved.

In the long vertical scan pause mode, if 32 horizontal periods tL2' of the internal synchronization signal Hsync2 (corresponding to one display operation sub-period) are equivalent to 31 horizontal periods tL2 of the external horizontal synchronization signal Hsync1, the line memory 111b may need to temporarily store pixel data corresponding to 1 gate line (or pixel data corresponding to 1 line number) corresponding to one display operation sub-period (e.g., the display operation sub-period FP2DP 1). If the display operation period FP2DPr can be divided into 45 display operation sub-periods FP2DP 1-FP 2DPn, the line memory 111b may need to temporarily store the pixel data corresponding to 45 gate lines. If the line memory 111b can store pixel data corresponding to 100 rows (row) of gate lines, the number of lines corresponding to the delay DL2 can be greater than or equal to 45 and less than 100.

In another embodiment, in the long vertical scan pause mode, the touch operation may be performed only in the touch operation sub-period FP2TP1 shown in fig. 5, and not in the touch operation sub-period FP2TP2 corresponding to the vertical front edge time tVFP 2'. During the touch operation sub-period FP2TP1, the timing generation circuit 111c can control the touch circuit 114 to drive (simultaneously) the touch electrodes 122 (partial or mutually short-circuited) so as to sense/detect a touch event.

In an embodiment, the touch operation period FP2TP of fig. 3 corresponds to the vertical front edge time tVFP2 'and the touch operation sub-period FP2TP2 of fig. 5 corresponds to the vertical front edge time tVFP2', but the present disclosure is not limited thereto, and the touch operation period or the touch operation sub-period may also correspond to the vertical back edge time.

Synchronization

In one embodiment, the timing generation circuit 111c may be timed to perform a synchronization operation in order to synchronize the timing of the internal horizontal synchronization signal Hsync2 with the timing of the external horizontal synchronization signal Hsync1 and the timing of the external vertical synchronization signal Vsync 1.

For example, as shown in fig. 4, in the long horizontal scanning pause mode, the external horizontal synchronization signal Hsync1 and the internal horizontal synchronization signal Hsync2 can be synchronized at the start time point (indicated by the white arrow) of each time unit, for example, one synchronization can be performed every 20 horizontal periods tL3 of the external horizontal synchronization signal Hsync 1.

For example, as shown in fig. 5, in the long vertical scan pause mode, the external horizontal synchronization signal Hsync1 and the internal horizontal synchronization signal Hsync2 can be synchronized at a start time point (indicated by a white arrow) of each display operation sub-period (e.g., the display operation sub-period FP2DP 1), for example, one synchronization can be performed every 31 horizontal periods tL2 of the external horizontal synchronization signal Hsync 1.

In one embodiment, the vertical front edge times tVFP2, tVFP3 or the vertical back edge times tVBP2, tVBP3 of the frames F2, F3 of the external horizontal synchronization signal Hsync1 may be equal to the vertical front edge times tVFP2', tVFP3' or the vertical back edge times tVBP2', tVBP3' of the frame period FP2, respectively.

In an embodiment, the delay DL2, the vertical front porch time tVFP2, or the vertical back porch time tVBP2 corresponding to the frame F2 may not be equal to or equal to the delay DL3, the vertical front porch time tVFP3, or the vertical back porch time tVBP3 corresponding to the frame F3. Since the touch operation can be performed at the vertical front edge time tVFP2, increasing the vertical front edge time tVFP2 can increase the length of time for which the touch operation is performed. In one embodiment, the vertical front porch time tVFP2 of frame F2 may be greater than the vertical front porch time tVFP3 of frame F3.

In one embodiment, one display operation sub-period (e.g., the display operation sub-periods FP3DP1 to FP3DP10 shown in fig. 4 or the display operation sub-periods FP2DP1 to FP2DPn shown in fig. 5) can be used to output the pixel data corresponding to the same number of gate lines, so that the time length of each display operation sub-period can be equal. Similarly, the touch operation sub-periods (e.g., the touch operation sub-periods FP3TP1 to FP3TP10 shown in fig. 4) can be used to drive the same number of touch electrodes 122, so the time length of each touch operation sub-period can be equal. The number (e.g., 10) of the touch operation sub-periods (e.g., FP3TP1 to FP3TP10 shown in fig. 4) may be related to the number of rows (or columns) of the touch electrodes 122.

Same frame rate

In an embodiment, different ones of the long horizontal scanning pause mode and the long vertical scanning pause mode may be employed at the same frame rate. Referring to fig. 1 and fig. 6, fig. 6 is a timing diagram of an embodiment of the present application.

In one embodiment, the timing generation circuit 111c is configured to determine whether the time lengths of the Hsync1 in the horizontal periods (e.g., the horizontal periods tL12 to tL14 shown in fig. 6) of two consecutive frames (e.g., the frames F12 to F14 shown in fig. 6) are the same. Based on the horizontal period tL13 being longer (compared to the horizontal period tL 12), the data signal output by the FP12 during the frame period may correspond to the long vertical scanning pause mode, and the data signal output by the FP13 during the frame period may correspond to the long horizontal scanning pause mode.

In one embodiment, the frame period FP12 is equal to the frame period FP13, but the touch hit rate corresponding to the frame period FP2 may not be equal to the touch hit rate corresponding to the frame period FP3. For example, the frame period FP12 and the frame period FP13 may be 11.11 milliseconds each, such that the frame rate is 90Hz, but the touch report rate may be 90Hz and 180Hz, respectively, for example.

In another embodiment, a Microcontroller Unit (MCU) (not shown) of the driving circuit 110 may use an algorithm to interpolate the padding points, so that the touch hit rate in the long vertical scan pause mode may be different from the frame rate. For example, the frame period FP12 may be, for example, 11.11 milliseconds, such that the frame rate is 90Hz, but the touch hit rate may be, for example, 180Hz. Therefore, when the long vertical scanning pause mode is switched to the long horizontal scanning pause mode, the frame rate can be maintained at 90Hz, and the touch report rate can be maintained at 180Hz.

Dynamic switching between long vertical scan pause mode and long horizontal scan pause mode

As shown in fig. 2 or fig. 6, it is possible to dynamically switch between the long vertical scan pause mode and the long horizontal scan pause mode. That is, during the process of switching the long vertical scan pause mode to the long horizontal scan pause mode, it is not necessary to enter the sleep mode (or the Integrated Circuit (IC)) from the long vertical scan pause mode to pause or power off, and then end the sleep mode (or the IC is recovered or powered on) to switch to the long horizontal scan pause mode. Therefore, in the process of switching the long vertical scan pause mode to the long horizontal scan pause mode, the touch display panel 120 does not become dark, and the display screen can be continuously displayed. That is, a frame (for example, frame period FP 12) employing the long vertical scanning pause pattern and a frame (for example, frame period FP 13) employing the long horizontal scanning pause pattern are two consecutive frames, and (an end time point of) the frame (for example, frame period FP 12) employing the long vertical scanning pause pattern is connected to (a start time point of) the frame (for example, frame period FP 13) employing the long horizontal scanning pause pattern. For example, the vertical leading edge time tVFP12 'of the frame (e.g., frame period FP 12) employing the long vertical scanning pause mode is connected to the vertical trailing edge time tVBP13' of the frame (e.g., frame period FP 13) employing the long horizontal scanning pause mode.

In short, in one embodiment, the timing generation circuit 111c is configured to determine whether the time lengths of the Hsync1 signals in the horizontal periods (e.g., the horizontal periods tL12 and tL 13) of two consecutive frames are the same, so as to determine whether to switch to the long vertical scan pause mode or the long horizontal scan pause mode.

In another embodiment, the timing generation circuit 111c can determine whether to switch to the long vertical scan pause mode or the long horizontal scan pause mode by detecting the time length of the horizontal period (e.g., the horizontal period tL 12) according to the received external horizontal synchronization signal Hsync 1. For example, based on the time length of the horizontal period tL12, the data signal output by the FP12 during the frame may correspond to a long vertical scanning pause pattern. The data signal output by the FP13 during the frame may correspond to a long horizontal scanning pause pattern based on the time length of the horizontal period tL 13.

In another embodiment, the timing generation circuit 111c can determine whether to switch to the long vertical scan pause mode or the long horizontal scan pause mode according to the received command. For example, based on the command received by the timing generation circuit 111c, the data signal output by the FP12 during the frame period may correspond to the long vertical scan pause mode, and the data signal output by the FP13 during the frame period may correspond to the long horizontal scan pause mode.

FIG. 7 is a timing diagram according to an embodiment of the present application. In another embodiment, the timing generation circuit 111c may determine whether to switch to the long vertical scan pause mode or the long Horizontal scan pause mode by detecting time lengths tBLLP, thct, tHBP, and thp of a Low Power margin (available for introducing a Low Power state) BLLP, a Horizontal synchronization active line (HACT) RGB, a Horizontal Back Porch (HBP), or a Horizontal front porch (Horizontal on Power) HFP of a Horizontal period (e.g., horizontal periods tL22 and tL 23) based on the received external synchronization signal Hsync 1. The frames F22 and F23 may respectively include a Vertical Sync End packet (VS), a Horizontal Sync Start packet (HS), a Low Power Mode (LPM), a Low Power blank period (BLLP), a Horizontal Sync pulse line period (RGB), a Horizontal Back Porch (HBP), or a Horizontal Front Porch (HFP).

In one embodiment, the time duration of the horizontal periods tL22 and tL23, the low power blanking period BLLP, the horizontal synchronization pulse line period RGB, the horizontal back porch HBP or the horizontal front porch HFP is actually determined by a previous stage (not shown in fig. 1), and these time durations are known from the video packet stream 100 transmitted by the previous stage. In other words, the preceding stage circuit determines whether the frame rate varies. The timing generation circuit 111c passively switches internally (corresponding to the timing switching of the long vertical scan pause mode or the long horizontal scan pause mode) according to the video packet stream 100 from the previous stage.

In one embodiment, the touch display panel 120 may include a display panel for display operation and a touch screen for touch operation. The touch screen may be embedded inside the display panel.

In one embodiment, the driver circuit 110 may include a touch and display driver integrated circuit and/or other driver circuits. The transport Interface may include a Mobile Industry Processor Interface (MIPI) and/or other transport interfaces.

For convenience of illustration, the drawings are only schematic for easier understanding of the present application, and the detailed proportions thereof can be adjusted according to design requirements. In the present application, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The terms "first," "second," and the like, as used herein, are used for distinguishing between different elements and not necessarily for describing a sequential or chronological order. Reference herein to "when …" can refer to "if", "under …", "immediately when …", "immediately after …", or "after … for a (tolerable/negligible) length of time". Embodiments of the present application may be combined in various ways without conflict.

In summary, the driving circuit of the present application can automatically switch between the long horizontal scan pause mode and the long vertical scan pause mode according to the period corresponding to the received video packet stream, for example, according to whether the time lengths of the horizontal periods of two consecutive frames are the same, thereby ensuring the display quality. According to the method and the device, the long vertical scanning pause mode can be adopted at a high frame rate, and the long horizontal scanning pause mode is adopted at a low frame rate for saving electricity. The long vertical scanning pause mode at the high frame rate can avoid the unrecoverable display stripes on the touch display panel when the horizontal period is short. The long horizontal scanning pause mode and the extended horizontal scanning pause mode are adopted at the low frame rate, and the vertical blank period is not too long, so that the problems of screen flashing and other abnormal display can be avoided. In the low frame rate, the long horizontal scanning pause mode and the extended horizontal scanning pause mode are adopted, and the voltage can easily reach the predetermined level because the horizontal period is longer. In addition, in the present application, the touch hit rate corresponding to the high frame rate may be equal to the touch hit rate corresponding to the low frame rate.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A timing control circuit, comprising:

a receiving circuit; and

a line memory coupled to the receive circuit, wherein the line memory is configured to:

outputting a first data signal during a first frame period; and

outputting a second data signal during a second frame,

wherein an end time point of the first frame period coincides with a start time point of the second frame period,

one of the first data signal and the second data signal corresponds to a long horizontal scanning pause mode, and the other one of the first data signal and the second data signal corresponds to a long vertical scanning pause mode.

2. The timing control circuit of claim 1, wherein the receive circuit is to:

receiving a first external signal, wherein the first external signal corresponds to a first period; and

receiving a second external signal, wherein the second external signal corresponds to a second period, the first period is not equal to the second period, and the first period and the second period are both a horizontal period, a horizontal synchronization pulse line period, a low-power blank period, a horizontal back porch, or a horizontal front porch.

3. The timing control circuit of claim 1, wherein the receive circuit is to:

receiving a second external signal, wherein the second external signal corresponds to a second period,

wherein the second data signal corresponds to the long vertical scan pause mode or the long horizontal scan pause mode based on the second period.

4. The timing control circuit of claim 1,

based on the first frame period of the first data signal being greater than the second frame period of the second data signal, the first data signal corresponding to the long horizontal scan pause mode,

the first data signal corresponds to the long vertical scan pause mode based on the first frame period of the first data signal being less than the second frame period of the second data signal.

5. The timing control circuit of claim 1, wherein the first frame period of the first data signal is not equal to the second frame period of the second data signal, and a first touch reporting rate corresponding to the first frame period is equal to a second touch reporting rate corresponding to the second frame period.

6. The timing control circuit of claim 1, wherein one of the first data signal and the second data signal corresponds to the long horizontal scan pause mode and an extended horizontal scan pause mode.

7. The timing control circuit of claim 1, wherein the receive circuit is to:

receiving a first external signal, wherein the first external signal corresponds to a first period, and a first delay is provided between the first data signal and the first external signal, and the first delay is proportional to the first period; and

receiving a second external signal, wherein the second external signal corresponds to a second period, a second delay is provided between the first data signal and the second external signal, the second delay is proportional to the second period, and the first delay is not equal to the second delay.

8. The timing control circuit of claim 7, wherein a ratio between the first delay and the second delay is equal to a ratio between the first period and the second period.

9. The timing control circuit of claim 1, wherein the first frame period of the first data signal is equal to the second frame period of the second data signal, and a first touch hit rate for the first data signal is not equal to a second touch hit rate for the second data signal.

10. The timing control circuit of claim 1, wherein a first vertical leading edge time corresponding to the first data signal is not equal to a second vertical leading edge time corresponding to the first data signal.

11. A timing control method, comprising:

outputting a first data signal during a first frame period; and

outputting a second data signal during a second frame,

12. The timing control method of claim 11, further comprising:

receiving a second external signal, wherein the second external signal corresponds to a second period, the first period is not equal to the second period, and the first period and the second period are both a horizontal period, a horizontal synchronization pulse line period, a low-power blank period, a horizontal back porch or a horizontal front porch;

wherein the first and second data signals respectively correspond to different ones of the long horizontal scan pause mode and the long vertical scan pause mode based on a difference in time length between the first and second periods.

13. The timing control method of claim 11, further comprising:

14. The timing control method of claim 11,

15. The timing control method of claim 11, wherein the first frame period of the first data signal is not equal to the second frame period of the second data signal, and a first touch reporting rate corresponding to the first frame period is equal to a second touch reporting rate corresponding to the second frame period.

16. The timing control method of claim 11, wherein one of the first data signal and the second data signal corresponds to the long horizontal scan pause mode and an extended horizontal scan pause mode.

17. The timing control method of claim 11, wherein the receive circuit is configured to:

18. The timing control method of claim 17, wherein a ratio between the first delay and the second delay is equal to a ratio between the first period and the second period.

19. The timing control method of claim 11, wherein the first frame period of the first data signal is equal to the second frame period of the second data signal, and a first touch hit rate corresponding to the first data signal is not equal to a second touch hit rate corresponding to the second data signal.

20. The timing control method of claim 11, wherein a first vertical leading edge time corresponding to the first data signal is not equal to a second vertical leading edge time corresponding to the first data signal.