CN115712420B - Architecture design and architecture conversion method based on complex real-time embedded system - Google Patents
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Abstract
The invention discloses a method for architecture design and architecture conversion based on a complex real-time embedded system, which aims at the architecture design and analysis of the complex real-time embedded system based on a model, wherein the architecture model is used as an authoritative data real-phase source to provide data for developing the work of other visual angles in the whole system, and the functional architecture of the complex real-time embedded system is described through SysML; describing the logic architecture of the complex embedded system through SysML and the extended FACE Profile thereof; the physical architecture of a complex embedded system is described by SysML and its extended MARTE Profile. Based on the established complex real-time embedded system functional architecture, logic architecture and physical architecture model, the method can automatically convert the SysML functional architecture, the SysML and FACE Profile logic architecture and the SysML and MARTE Profile physical architecture model into corresponding AADL architecture models through model conversion, thereby improving the efficiency and accuracy of the subsequent complex real-time embedded system architecture analysis work.
Description
Technical Field
The invention relates to the field of embedded system research and development, in particular to a complex real-time embedded system-based architecture design and architecture conversion method.
Background
The complex real-time embedded system is widely applied to the fields of avionics, spacecrafts, automobile control and the like, has the characteristics of limited resources, real-time response, fault tolerance, special hardware and the like, has higher requirements on performances such as instantaneity, safety and the like, becomes more and more complex due to the requirements of calculation precision and real-time response, and is a difficult problem commonly faced by academia and industry how to design and realize a high-quality complex equipment embedded real-time system and effectively control development time and cost.
In the conventional embedded system development mode, in the sequential development process from demand analysis, design and implementation to testing, because of more development links and more intermediate documents, great uncertainty and potential omission crisis exist in the connection between the development links, once obvious errors or unsatisfied demands appear in the final implementation and testing stage, repeated design of crossing stages cannot be performed, and only design and implementation can be started from the beginning, so that the cost of the development of the embedded system is greatly increased, which is a bottleneck of the design and development of the embedded system. The model driven development method (Model Driven Development, MDD) can carry out architecture design and analysis on the complex real-time embedded system at an early stage, is beneficial to ensuring the quality attribute of the system and effectively controlling the development time and cost. And the quality attributes are determined by the system architecture. Therefore, the design and development method based on architecture Model-driven (Model-based architecture-driver) is an important research content in the field of complex real-time embedded systems. Although developing model-based system architecture design and analysis based on the framework of function (F), logic (L), and physical (P) is becoming a common knowledge, in the field of complex real-time embedded system architecture design and analysis, the following drawbacks still exist: the definition and characteristics of the functional architecture, the logic architecture and the physical architecture are not unified. Meanwhile, in the aspect of architecture conversion, the method is basically manual conversion, and a complete architecture model automatic conversion method is lacked.
Disclosure of Invention
In order to solve the technical problems, the invention provides a complex real-time embedded system-based architecture design and architecture conversion method, such as complex real-time embedded system functional architecture design modeling, logic architecture design modeling, physical architecture design modeling, and architecture model automatic conversion method.
The technical scheme of the invention is as follows: a method for architecture design and architecture conversion based on a complex real-time embedded system comprises the following steps:
step 1, based on low-level requirements and design constraints of a complex real-time embedded system, performing SysML (System Modeling Language ) functional architecture design modeling on the complex real-time embedded system, and then converting a SysML functional architecture model into an AADL functional architecture model through a model automatic conversion method;
step 2, performing logic architecture design based on a functional architecture, performing SysML and FACE Profile logic architecture design modeling on a complex real-time embedded system, and then converting a SysML and FACE Profile logic architecture model into an AADL logic architecture model by a model automatic conversion method;
and 3, performing physical architecture design based on a logic architecture, performing SysML and MARTE Profile physical architecture design modeling on the complex real-time embedded system, and then converting the SysML and MARTE Profile physical architecture model into an AADL physical architecture model through a model automatic conversion method.
Furthermore, step 1 carries out the design modeling of the SysML functional architecture according to the low-level requirements and design constraints of the complex real-time embedded system, and then completes the conversion to the AADL functional architecture model, and specifically comprises the following steps:
based on the low-level requirements and design constraints of the complex real-time embedded system, performing functional architecture design on the complex real-time embedded system, and firstly establishing a functional architecture of the system, including allocation of system functional elements and establishment of functional levels; and then analyzing and defining the system function architecture element interface, identifying the derivative requirement of the system function architecture design, and finally converting the SysML function architecture model into an AADL function architecture model.
Further, the step 2 performs logic architecture design based on the functional architecture, performs logic architecture design modeling of SysML and FACE profiles, and then completes conversion to an AADL logic architecture model, and specifically includes:
the method comprises the steps of carrying out logic architecture design based on a functional architecture, firstly defining logic components, including establishing a logic set, defining logic entities, determining mapping relation between the logic entities and functional elements and distributing performance indexes; and then carrying out interface analysis and definition of a system logic architecture, identifying derivative requirements of the system logic architecture design, and finally converting the SysML and FACE Profile logic architecture model into an AADL logic architecture model.
Further, the step 3 performs physical architecture design based on a logic architecture, performs sysML and MARTE Profile physical architecture design modeling on the complex real-time embedded system, and then completes conversion to an AADL physical architecture model, and specifically includes:
the method comprises the steps of performing physical architecture design based on functions and logic architecture, and firstly defining physical components, including establishing a physical set, defining physical entities, determining mapping relation from the physical entities to the logic entities, converting performance indexes into physical indexes and distributing the physical indexes; and then carrying out interface analysis and definition of a system physical architecture, identifying derivative requirements of the system physical architecture design, and finally converting the SysML and MARTE Profile physical architecture model into an AADL physical architecture model.
Furthermore, the conversion from the complex real-time embedded system architecture model to the AADL model in the steps 1, 2 and 3 adopts the same conversion method, and the specific contents are as follows:
(1) Because the SysML model, the FACE Profile model, the MARTE Profile model and the AADL model are heterogeneous models, the SysML model, the FACE Profile model, the MARTE Profile model and the AADL model are isomorphic under the same meta-model system in order to realize the automatic conversion from the SysML model, the FACE Profile model and the MARTE Profile model to the AADL model, and then semantic mapping and grammar conversion are carried out. The first problem to be solved in the conversion of heterogeneous models is to isomorphism two models under the same meta-model system, namely, define the meta-models of SysML model, FACE Profile model, MARTE Profile model and AADL by the same meta-model. The SysML meta-model, the FACE Profile meta-model, the MARTE Profile meta-model and the AADL meta-model are constructed through MOF, and the models are simultaneously in a MOF meta-model system, so that two languages can be subjected to semantic mapping under the same environment. Then defining semantic mapping rules of SysML subset metamodel and AADL subset metamodel at M2 metamodel layer, constructing specific grammar for AADL subset metamodel, which can be automatically realized by EMF frame.
(2) Developing an ecle meta-model in Eclipse by using EMF technology, and describing a SysML model structure XMI file of a complex real-time embedded system function architecture; the Ecore model generates a parser which reads the SysML model structure representing the functional architecture in the XMI file, thereby creating an EMF model in Eclipse; the mapping from the elements in the EMF model to the elements in the AADL is created by traversing the EMF model corresponding to the function architecture SysML model, the mapping relation between the AADL object corresponding to the component and the EMF to the AADL is created firstly on the basis of the established conversion rule, and then the connection between the components is established by using a model connector, so that the AADL function architecture model is obtained; similarly, the logical architecture model of SysML and FACE Profile and the physical architecture model of SysML and MARTE Profile are converted into an AADL logical architecture model and an AADL physical architecture model, respectively.
The beneficial effects are that:
the method of the invention realizes loading and applying MARTE and FACE Profile based on OMG standard in a developed tool environment, so that based on UML/SysML primitive element and construction type, the meta-model and formal definition of MARTE and FACE Profile are provided by Profile expansion, and support is provided for embedded system architecture design and analysis full modeling. Based on the business process and the conversion method provided by the invention, a conversion tool from a SysML model, a FACE Profile model and a MARTE Profile model to an AADL model is realized, and is integrated into the existing design tool, and an EMF frame technology and an Eclipse plug-in technology are used for realizing the architecture conversion prototype tool plug-in, so that the automatic conversion from the SysML model, the FACE Profile model and the MARTE Profile model to the AADL model is realized, and the efficiency and the accuracy of the model conversion are practically improved.
Drawings
FIG. 1 is a general flow chart of the present invention;
FIG. 2 is a diagram of an example of functional architecture SysML modeling;
FIG. 3FACE Profile implementation;
FIG. 4 is a diagram of an example of logical architecture SysML and FACE Profile modeling;
FIG. 5MARTE Profile implementation;
FIG. 6 is a diagram of an example of modeling of a physical architecture SysML and MARTE Profile;
FIG. 7 is a flow chart of architecture model conversion.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art without the inventive effort based on the embodiments of the present invention are within the scope of protection of the present invention.
According to an embodiment of the present invention, a method for architecture design and architecture conversion based on a complex real-time embedded system is provided, see fig. 1, including the following steps:
step 1, based on low-level requirements and design constraints of a complex real-time embedded system, performing SysML (system modeling language) functional architecture design modeling on the complex real-time embedded system, and then converting a SysML (System Modeling Language ) functional architecture model into an AADL (ArchitectureAnalysis and Design Language ) functional architecture model by a model automatic conversion method;
step 2, performing logic architecture design based on a functional architecture, performing SysML and FACE (FutureAirborne Capability Environment ) Profile logic architecture design modeling on a complex real-time embedded system, and then converting a SysML and FACE Profile logic architecture model into an AADL logic architecture model by a model automatic conversion method;
and 3, performing physical architecture design based on a logic architecture, performing SysML and MARTE (Modeling andAnalysis ofReal Time and Embedded systems, real-time embedded system modeling and analysis) Profile physical architecture design modeling on the complex real-time embedded system, and then converting the SysML and MARTE Profile physical architecture model into an AADL physical architecture model by a model automatic conversion method, wherein a flow chart of architecture model conversion is shown in fig. 7.
Specifically, step 1 carries out the design modeling of the SysML functional architecture according to the low-level requirements and design constraints of the complex real-time embedded system, and then completes the conversion to the AADL functional architecture model, and specifically comprises the following steps:
based on low-level requirements and design constraints of the complex real-time embedded system, a Modsim tool is used for carrying out functional architecture design modeling on the complex real-time embedded system, wherein Modsim is a Jin Hang digital system design modeling and simulation system based on SysML autonomous development. The modeling and simulation system is built based on Eclipse RCP platform architecture, adopts a standard client mode, and provides modeling of UML2.5 and SysML1.6 standard specifications. In the modeling process of functional architecture design, in order to distinguish blocks representing functional groups and functions from blocks representing a system, the functional architecture design is organized by using packets alone. By creating a Block Definition Diagram (BDD) describing a functional group and a decomposition structure of functions, data flow interactions between functions in the functional group are described using an Internal Block Diagram (IBD), functional flows are described using an activity diagram, functional interactions are described using a sequence diagram, and a dynamic behavior model of functional elements is described using a state diagram. Ports representing function blocks represent information flow ports (mainly data flows or event flows), connection is used to represent information flow Connection relationships between functions (in IBD graphs, properties are used to represent properties), modeling example graphs are shown in fig. 2, functionGroupID represents a group of functions, funID represents a specific function, and Port "function ID" on FunID represents an information flow Port. By creating a demand graph to represent and identify derivative demands of system function architecture design, and finally converting a SysML IBD graph representing a function architecture model into a corresponding AADL function architecture model according to conversion rules, the converted model can be directly opened through an OSATE tool, and the conversion rules proposed by the method are shown in the following table 1:
TABLE 1 SysML model and AADL model conversion rules
Further, the step 2 performs logic architecture design based on the functional architecture, performs logic architecture design modeling of SysML and FACE profiles, and then completes conversion to an AADL logic architecture model, and specifically includes:
based on system function architecture design, a Modsim tool is used for carrying out logic architecture design modeling on a complex real-time embedded system, a logic component is used for representing system components, and functions in the function architecture are distributed to the logic components. The BDD diagram is used for describing the decomposition composition relation of the system, the Block at the top layer represents the system, other blocks represent logic components (or subsystems), ports on the blocks are used for representing data exchange ports of the logic components, and the composition connection relation is used for describing the composition structure of the system. The logic component may nest the containing sub-logic components. An Interface packet describing the data exchange port is newly built in the corresponding packet in the logic architecture, and specific data modeling of the data exchange port is carried out by adopting FACE Profile in the BDD diagram. And the association of the FACE data model and the ports is realized by selecting the Port type of the logic component as the data established by the FACE data model element. The interaction relationships between the top-level logical components of the system, as well as the sub-components within each top-level logical component and the data interaction relationships are described using the IBD graph. Connection connectors are used to represent data connections between logical components (denoted by properties). The IBD graph is used to describe the distribution relationship between functions in the functional architecture and logical components in the logical architecture. In the BDD diagram, the blocks representing the functions are dragged into the diagram in the Property form, the blocks of the logic components are dragged in the same way, and the functions are distributed to the logic components by using an allowances. When the model is more complex than the allocation relation, the allocation relation of the functions to the logic components can be described in a form of a traceability matrix. Dynamic behavior verification of a logic architecture is performed by describing dynamic behaviors of the logic entity based on a state diagram model of the logic entity, wherein implementation of a FACE Profile is shown in fig. 3, a modeling example diagram is shown in fig. 4, logiccomponentID represents a logic component, and a port "logic ID" on the logic component represents a corresponding information flow port. By creating a demand graph to represent and identify derivative demands of a system logic architecture design, and finally converting a SysML IBD graph representing a logic architecture model into a corresponding AADL logic architecture model according to conversion rules, the converted model can be directly opened through an OSATE tool, and the conversion rules proposed by the method are shown in the following tables 2 and 3:
TABLE 2 SysML model and AADL model conversion rules
TABLE 3FACE Profile model and AADL model conversion rules
Specifically, step 3, performing physical architecture design according to a logic architecture, performing sysML and MARTE Profile physical architecture design modeling on a complex real-time embedded system, and then converting the sysML and MARTE Profile physical architecture model into an AADL physical architecture model by a model automatic conversion method, wherein the specific steps are as follows:
based on a logic architecture, the Modsim is used for carrying out complex real-time embedded system physical architecture design modeling, MARTE Profile is loaded and applied, and elements in MARTE are adopted to specifically define the software and hardware composition and allocation relation of the embedded system. The BDD diagram is used for describing the decomposition composition relation of the system, the Block at the top layer represents the system, other blocks represent physical components (or subsystems), ports on the Block are used for representing data exchange ports of the physical components, and the composition connection relation is used for describing the composition structure of the system. The system and subsystem are represented using SysMLBlock, and the software and hardware components of the subsystem are defined using MARTE elements. Representing the internal composition relation in an Internal Block Diagram (IBD) of Block, wherein if the Property represents specific software and hardware, the Property is of a type which is defined as MARTE element; if Property indicates a subsystem, the type is a subsystem type defined by Block. The allocation relationship between the MARTE elements is described by using allocation, the allocation relationship between the logic architecture (logic component) and the physical architecture (software and hardware represented by MARTE elements) is described by using a traceback matrix, the implementation of MARTE Profile is shown in FIG. 5, and the modeling example diagram is shown in FIG. 6. By creating a demand graph to represent the derived demand of the physical architecture design of the identification system, and finally converting the SysML IBD graph representing the physical architecture model into a corresponding AADL physical architecture model according to conversion rules, the converted model can be directly opened through an OSATE tool, and the conversion rules proposed by the method are shown in the following tables 4 and 5:
TABLE 4 SysML model and AADL model conversion rules
TABLE 5MARTE Profile model and AADL model conversion rules
While the foregoing has been described in relation to illustrative embodiments thereof, so as to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, but is to be construed as limited to the spirit and scope of the invention as defined and defined by the appended claims, as long as various changes are apparent to those skilled in the art, all within the scope of which the invention is defined by the appended claims.
Claims (4)
1. The architecture design and architecture conversion method based on the complex real-time embedded system is characterized by comprising the following steps:
step 1, based on low-level requirements and design constraints of a complex real-time embedded system, performing SysML (integrated circuit markup language) functional architecture design modeling on the complex real-time embedded system, and then converting a SysML functional architecture model into an AADL functional architecture model through a model automatic conversion method;
step 2, performing logic architecture design based on a functional architecture, performing SysML and FACE Profile logic architecture design modeling on a complex real-time embedded system, and then converting a SysML and FACE Profile logic architecture model into an AADL logic architecture model by a model automatic conversion method;
step 3, performing physical architecture design based on a logic architecture, performing SysML and MARTE Profile physical architecture design modeling on the complex real-time embedded system, and then converting the SysML and MARTE Profile physical architecture model into an AADL physical architecture model by a model automatic conversion method;
step 2 is to perform logic architecture design based on the functional architecture, perform logic architecture design modeling of SysML and FACE profiles, and then complete conversion to an AADL logic architecture model, wherein the specific contents are as follows:
the method comprises the steps of carrying out logic architecture design based on a functional architecture, firstly defining logic components, including establishing a logic set, defining logic entities, determining mapping relation between the logic entities and functional elements and distributing performance indexes; then, interface analysis and definition of a system logic architecture are carried out, derivative requirements of the system logic architecture design are identified, and finally, sysML and FACE Profile logic architecture models are converted into AADL logic architecture models, wherein the method specifically comprises the following steps:
the logic architecture design modeling mainly comprises the steps of modeling and designing logic components of a complex real-time embedded system, representing the system components by using a logic component mode, distributing functions in a functional architecture to the logic components, describing the decomposition composition relation of the system by using a BDD diagram, enabling a Block at the top layer to represent the system, enabling other blocks to represent the logic components or subsystems, enabling ports on the blocks to be used for representing data exchange ports of the logic components, and describing the system composition structure by using composition connection relation; newly building an Interface packet for describing a data exchange Port in a corresponding packet in the logic architecture, wherein specific data modeling of the data exchange Port is performed by adopting an FACE Profile in the BDD graph, and the association between the FACE data model and the Port is realized by selecting the Port type of the logic component as the data established by the FACE data model element; describing interaction relations among top-level logical components of the system and data interaction relations among sub-components inside each top-level logical component by using an IBD graph; connection connectors are used to represent data connections between logical components; performing distribution relation description between functions in a functional architecture and logic components in the logic architecture by using an IBD diagram, dragging blocks representing the functions into the diagram in a Property mode in the BDD diagram, dragging blocks of the logic components in the same mode, distributing the functions to the logic components by using allowances, describing distribution relation from the functions to the logic components by using a trace matrix mode when the complex allowances of the models are more, describing dynamic behaviors of the logic entities by using a state diagram model based on the logic entities, and performing dynamic behavior verification of the logic architecture;
the conversion from the complex real-time embedded system architecture model to the AADL model in the steps 1, 2 and 3 adopts the same conversion method, and the specific contents are as follows:
aiming at the automatic conversion from the SysML model, the FACE Profile model and the MARTE Profile model to the AADL model, the SysML model, the FACE Profile model, the MARTE Profile model and the AADL model are isomorphic under the same meta-model system, so that semantic mapping and grammar conversion are further carried out; namely, defining a SysML model, a FACE Profile model, a MARTE Profile model and an AADL meta model through the same meta model; the method comprises the steps of constructing a SysML meta-model, a FACE Profile meta-model, a MARTE Profile meta-model and an AADL meta-model through MOF, enabling two languages to be subjected to semantic mapping under the same environment at the same time in a MOF meta-model system, defining semantic mapping rules of a SysML subset meta-model and an AADL subset meta-model at an M2 meta-model layer, constructing a specific grammar for the AADL subset meta-model, and automatically realizing the semantic mapping by an EMF framework.
2. The architecture design and architecture conversion method based on the complex real-time embedded system according to claim 1, wherein the step 1 performs the sysML functional architecture design modeling according to the low-level requirements and design constraints of the complex real-time embedded system, and then completes the conversion to the AADL functional architecture model, and the specific contents are as follows:
based on the low-level requirements and design constraints of the complex real-time embedded system, performing functional architecture design on the complex real-time embedded system, and firstly establishing a functional architecture of the system, including allocation of system functional elements and establishment of functional levels; then analyzing and defining element interfaces of the system function architecture, identifying derivative requirements of the system function architecture design, and finally converting the SysML function architecture model into an AADL function architecture model;
the functional architecture design modeling mainly performs functional analysis and design according to use cases of a complex real-time embedded system to generate a functional architecture, the functional architecture abstracts functional groups and functional concepts, the functional groups comprise a plurality of functions, the two concepts are represented by using blocks in SysML or are packaged by using Profile, in order to distinguish blocks representing the functional groups and the functions from blocks representing the system, the blocks are independently organized by using packets, a Block Definition Diagram (BDD) is mainly used for describing the decomposition structure of the functional groups and the functions, data flow interaction between the functions in the functional groups is described by using an Internal Block Diagram (IBD), functional flow is described by using a movable diagram, functional interaction is described by using a sequence diagram, a dynamic behavior model of function elements is described by using a state diagram, a Port representing the functions represents information flow ports of the functions, and Connection interfaces are used for representing information flow Connection relations between the functions.
3. The architecture design and architecture conversion method based on the complex real-time embedded system according to claim 1, wherein the step 3 performs physical architecture design based on a logic architecture, performs the modeling of sysML and MARTE Profile physical architecture design on the complex real-time embedded system, and then completes the conversion to an AADL physical architecture model, and the specific contents are as follows:
the method comprises the steps of performing physical architecture design based on functions and logic architecture, and firstly defining physical components, including establishing a physical set, defining physical entities, determining mapping relation from the physical entities to the logic entities, converting performance indexes into physical indexes and distributing the physical indexes; then, interface analysis and definition of a system physical architecture are carried out, derivative requirements of the system physical architecture design are identified, and finally, sysML and MARTE Profile physical architecture models are converted into AADL physical architecture models, wherein the method specifically comprises the following steps:
the physical architecture design modeling introduces MARTE, adopts elements in MARTE to specifically define the software and hardware composition and distribution relation of an embedded system, uses a BDD diagram to describe the decomposition composition relation of the system, uses the Block at the top layer to represent the system, uses other blocks to represent physical components or subsystems, uses ports on the blocks to represent data exchange ports of the physical components, and uses composition connection relation to describe the composition structure of the system; the system and the subsystem are represented by SysML Block, the software and hardware components of the subsystem are defined by MARTE elements, and the internal composition relation is represented in an Internal Block Diagram (IBD) of the Block, wherein if the Property represents specific software and hardware, the type of the Property is defined MARTE elements; if the Property represents a subsystem, the type of the Property is a subsystem type defined by Block, the allocation is used for describing the software and hardware allocation relation among MARTE elements, and the traceability matrix is used for describing the allocation relation between a logic architecture and a physical architecture.
4. The architecture design and architecture conversion method based on the complex real-time embedded system according to claim 1, wherein the architecture design and architecture conversion method is automatically implemented by an EMF framework, and specifically comprises: developing an Ecore meta-model in Eclipse for describing a SysML model structure XMI file of a complex real-time embedded system function architecture; the Ecore model generates a parser which reads the SysML model structure representing the functional architecture in the XMI file, thereby creating an EMF model in Eclipse; the mapping from the elements in the EMF model to the elements in the AADL is created by traversing the EMF model corresponding to the function architecture SysML model, the mapping relation between the AADL object corresponding to the component and the EMF to the AADL is created firstly on the basis of the established conversion rule, and then the connection between the components is established by using a model connector, so that the AADL function architecture model is obtained; similarly, the logical architecture model of SysML and FACE Profile and the physical architecture model of SysML and MARTE Profile are converted into an AADL logical architecture model and an AADL physical architecture model, respectively.
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| "基于SysML___AAD...刹车控制系统实时性需求验证";邓佳佳等;《计算机与现代化》;第40-49页 * |
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