CN115712420A - Architecture design and architecture conversion method based on complex real-time embedded system - Google Patents
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Abstract
The invention discloses a method for architecture design and architecture conversion based on a complex real-time embedded system, which aims at the architecture design and analysis of the complex real-time embedded system based on a model, wherein the architecture model is taken as an authoritative data true source, provides data for developing the work of other visual angles in the whole system, and describes the functional architecture of the complex real-time embedded system through SysML; describing a logic architecture of the complex embedded system through SysML and an extended FACE Profile thereof; the physical architecture of a complex embedded system is described by SysML and its extended MARTE Profile. Based on the created complex real-time embedded system functional architecture, logic architecture and physical architecture model, the method can automatically convert the SysML functional architecture, the SysML and FACE Profile logic architecture, the SysML and MARTE Profile physical architecture model into the corresponding AADL architecture model through model conversion, thereby improving the efficiency and accuracy of the subsequent analysis work of the complex real-time embedded system architecture.
Description
Technical Field
The invention relates to the field of embedded system research and development, in particular to an architecture design and architecture conversion method based on a complex real-time embedded system.
Background
The complex real-time embedded system is widely applied to the fields of avionics, spacecrafts, automobile control and the like, has the characteristics of resource limitation, real-time response, fault tolerance, special hardware and the like, has higher requirements on the performances of real-time performance, safety and the like, is more and more complex due to the requirements on calculation precision and real-time response, and is a difficult problem facing both academic circles and industrial circles on how to design and realize a high-quality complex equipment embedded real-time system and effectively control development time and cost.
In a traditional embedded system development mode, in a sequential development process from requirement analysis, design and implementation to test, because of more development links and more intermediate documents, the connection between the development links is very uncertain and has potential crisis omission, once obvious errors or unsatisfied requirements occur in the final implementation and test stages, repeated design in a crossing stage cannot be performed, and the design and implementation can only be started from the beginning, so that various cost of the embedded system development is greatly increased, which is a bottleneck of the embedded system design and development. And the Model Driven Development (MDD) method can design and analyze the architecture of the complex real-time embedded system at an early stage, which is helpful to ensure the quality attribute of the system and effectively control the Development time and cost. And the quality attribute is determined by the system architecture. Therefore, a design and development method based on Model-based architecture-drive (Model-based architecture-drive) becomes an important research content in the field of complex real-time embedded systems. Although it is becoming common knowledge to develop model-based system architecture design and analysis based on functional (F), logical (L), and physical (P) frameworks, the following drawbacks still exist in the field of complex real-time embedded system architecture design and analysis: the definitions and features of the functional architecture, the logical architecture, and the physical architecture are not unified yet. Meanwhile, in the aspect of architecture conversion, manual conversion is basically performed, and a complete automatic architecture model conversion method is lacked.
Disclosure of Invention
In order to solve the technical problems, the invention provides an architecture design and architecture conversion method based on a complex real-time embedded system, which integrates the functional architecture design modeling, the logic architecture design modeling, the physical architecture design modeling, the architecture model automatic conversion method and the like of the complex real-time embedded system.
The technical scheme of the invention is as follows: a method for architecture design and architecture conversion based on a complex real-time embedded system comprises the following steps:
and 3, designing a physical architecture based on the logic architecture, designing and modeling SysML and MARTE Profile physical architectures of the complex real-time embedded system, and converting the SysML and MARTE Profile physical architecture models into AADL physical architecture models by using an automatic model conversion method.
Further, the step 1, according to the low-level requirements and design constraints of the complex real-time embedded system, performs the design modeling of the SysML functional architecture, and then completes the conversion to the AADL functional architecture model, specifically including:
based on the low-level requirements and design constraints of the complex real-time embedded system, designing a functional architecture of the complex real-time embedded system, and firstly establishing the functional architecture of the system, including the distribution of system functional elements and the establishment of a functional hierarchy; and then, analyzing and defining the system functional architecture element interface, identifying the derived requirements of the system functional architecture design, and finally converting the SysML functional architecture model into the AADL functional architecture model.
Further, the step 2 is to design a logic architecture based on the functional architecture, to model the logic architecture design of the SysML and FACE Profile, and then to complete the conversion to the AADL logic architecture model, and specifically includes:
designing a logic architecture based on a functional architecture, and firstly defining logic composition, including establishing a logic set, defining a logic entity, determining a mapping relation from the logic entity to a functional element and distributing performance indexes; then, the interface analysis and definition of the system logic architecture are carried out, the derived requirements of the design of the system logic architecture are identified, and finally the SysML and FACE Profile logic architecture model is converted into the AADL logic architecture model.
Further, the step 3 is to design a physical architecture based on a logic architecture, to design and model a SysML and a MARTE Profile physical architecture for the complex real-time embedded system, and then to complete the conversion to the AADL physical architecture model, and specifically includes:
designing a physical architecture based on a function and logic architecture, firstly defining physical composition, including establishing a physical set, defining a physical entity, determining a mapping relation from the physical entity to the logic entity, converting a performance index to a physical index, and distributing the physical index; and then, performing interface analysis and definition of a system physical architecture, identifying derived requirements of system physical architecture design, and finally converting the SysML and MARTE Profile physical architecture model into an AADL physical architecture model.
Further, the conversion from the complex real-time embedded system architecture model to the AADL model in steps 1, 2 and 3 adopts the same conversion method, and the specific contents are as follows:
(1) Because the SysML model, the FACE Profile model, the MARTE Profile model and the AADL model are heterogeneous models, the SysML model, the FACE Profile model, the MARTE Profile model and the AADL model need to be isomorphic under the same element model system in order to realize the automatic conversion from the SysML model, the FACE Profile model and the MARTE Profile model to the AADL model, and then semantic mapping and syntax conversion are carried out. The problem to be solved in the first place for the conversion of heterogeneous models is to isomorphize the two models in the same meta-model system, i.e. define the SysML model, the FACE Profile model, the MARTE Profile model and the AADL meta-model through the same meta-model. The SysML meta-model, the FACE Profile meta-model, the MARTE Profile meta-model and the AADL meta-model are constructed through MOF, and the models are simultaneously in the MOF meta-model system, so that semantic mapping can be performed on two languages in the same environment. Then, semantic mapping rules of the SysML subset meta-model and the AADL subset meta-model are defined at an M2 meta-model layer, and a specific grammar is constructed for the AADL subset meta-model, wherein the specific grammar can be automatically realized by an EMF framework.
(2) Developing an Ecore meta-model in Eclipse by using EMF technology, wherein the Ecore meta-model is used for describing a SysML model structure XMI file of a complex real-time embedded system functional architecture; the Ecore model generates a parser, and the parser reads out a SysML model structure representing a functional architecture in the XMI file, so as to create an EMF model in Eclipse; establishing mapping from elements in the EMF model to elements in AADL by traversing an EMF model corresponding to a SysML model of a functional architecture, establishing an AADL object corresponding to the components and a mapping relation from EMF to AADL on the basis of established conversion rules, and establishing a connection between the components by using a model connector, thereby obtaining an AADL functional architecture model; similarly, the logical architecture models of SysML and FACE Profile and the physical architecture models of SysML and MARTE Profile are converted into AADL logical architecture model and AADL physical architecture model, respectively.
Has the advantages that:
SysML is a standard modeling language of system engineering, but aiming at embedded system architecture design and analysis modeling, the generation of a final embedded system is captured from an early requirement, if an actual complex embedded system in the industry only uses SysML modeling, only the high-level design of the system can be completed, and the requirements of the complex real-time embedded system related to software and hardware cannot be clearly described, so that the embedded system architecture design and analysis are supplemented to the SysML language by MARTE and FACE. Based on the business process and the conversion method provided by the invention, the conversion tool from the SysML model, the FACE Profile model and the MARTE Profile model to the AADL model is realized subsequently and integrated into the existing design tool, the EMF framework technology and the Eclipse plug-in technology are used for realizing the framework conversion prototype tool plug-in, the automatic conversion from the SysML model, the FACE Profile model and the MARTE Profile model to the AADL model is realized, and the efficiency and the accuracy of model conversion are practically improved.
Drawings
FIG. 1 is a general flow diagram of the present invention;
FIG. 2 is an exemplary diagram of the functional architecture SysML modeling;
FIG. 3FACE Profile implementation;
FIG. 4 is an exemplary diagram of the logic architecture SysML and FACE Profile modeling;
FIG. 5MARTE Profile implementation;
FIG. 6 is an exemplary diagram of the physical architecture SysML and MARTE Profile modeling;
FIG. 7 architecture model conversion flow diagram.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by a person skilled in the art based on the embodiments of the present invention belong to the protection scope of the present invention without creative efforts.
According to an embodiment of the present invention, an architecture design and architecture conversion method based on a complex real-time embedded system is provided, referring to fig. 1, including the following steps:
and 3, performing physical architecture design based on the logic architecture, modeling and analyzing the complex real-Time Embedded system by SysML and MARTE (Modeling and simulation of real Time and Embedded systems) Profile physical architecture design, and then converting the SysML and MARTE Profile physical architecture model into an AADL physical architecture model by using an automatic model conversion method, wherein a flow chart of architecture model conversion is shown in FIG. 7.
Specifically, the step 1, according to the low-level requirements and design constraints of the complex real-time embedded system, performs the design modeling of the SysML functional architecture, and then completes the conversion to the AADL functional architecture model, specifically including:
based on the low-level requirements and design constraints of the complex real-time embedded system, a Modsim tool is used for carrying out functional architecture design modeling on the complex real-time embedded system, wherein the Modsim is a system design modeling and simulation system for gold aviation digital code autonomous development based on SysML. The modeling and simulation system is built based on an Eclipse RCP platform architecture, and provides modeling of UML2.5 and SysML1.6 standard specifications by adopting a standard client mode. In the functional architecture design modeling process, in order to distinguish the Block representing the functional group and the function from the Block representing the system, they are organized separately using packages. The method comprises the steps of describing a function group and a decomposition structure of functions by creating a Block Definition Diagram (BDD), describing data flow interaction among the functions in the function group by using an Internal Block Diagram (IBD), describing function flow by using an activity diagram, describing function interaction by using a sequence diagram, and describing a dynamic behavior model of function elements by using a state diagram. The ports representing the function Block represent information flow ports (mainly data flow or event flow) of the function, the Connection is used for representing information flow Connection relation between functions (represented by Property in an IBD chart), the modeling example chart is shown in fig. 2, functional group represents a function group, funID represents a specific function, and the Port "function ID" on FunID represents an information flow Port. The derived requirements of the system functional architecture design are identified by creating a requirement graph, and finally, a SysML IBD graph representing a functional architecture model is converted into a corresponding AADL functional architecture model according to a conversion rule, wherein the converted model can be directly opened through an OSATE tool, and the conversion rule provided by the method is shown in the following table 1:
TABLE 1 SysML model and AADL model conversion rules
Further, the step 2 is to design a logic architecture based on the functional architecture, to model the logic architecture design of the SysML and FACE Profile, and then to complete the conversion to the AADL logic architecture model, and specifically includes:
based on the system functional architecture design, a logic architecture design modeling is carried out on the complex real-time embedded system by using a Modsim tool, the system composition is expressed by using a logic component mode, and the functions in the functional architecture are distributed to the logic components. The BDD graph is used for describing the decomposition composition relationship of the system, the top Block represents the system, other blocks represent logic components (or subsystems), ports on the blocks are used for representing data exchange ports of the logic components, and the composition connection relationship is used for describing the composition structure of the system. Logic components may be nested to include sub-logic components. And newly building an Interface packet describing a data exchange port in a corresponding packet in the logic architecture, wherein specific data modeling of the data exchange port is carried out in a BDD (domain data description) diagram by adopting a FACE Profile. The association of the FACE data model and the Port is achieved by selecting the type of Port of the logical component as the data established by the FACE data model element. IBD graphs are used to describe the interactions between the top-level logical components of the system, as well as the data interactions between sub-components within each top-level logical component. The connection Connector is used to represent the data connections between logical components (denoted by Property). IBD graphs are used to describe the distribution relationship between functions in the functional architecture and logical components in the logical architecture. The Block representing the function is dragged into the graph in Property form in the BDD graph, the Block of the logic component is dragged in the same way, and the function is distributed to the logic component by using allocate. When the model is more complex, the assignment relationship of the function to the logic component can be described by using the form of the traceback matrix. The dynamic behavior verification of the logic architecture is performed by describing the dynamic behavior of the logic entity based on the state diagram model of the logic entity, wherein the implementation of the FACE Profile is shown in fig. 3, the modeling example is shown in fig. 4, the LogicComponentID represents the logic component, and the port "logic ID" on the logic component represents the corresponding information flow port. The derived requirements of the system logic architecture design are identified by creating a requirement graph, and finally, a SysML IBD graph representing a logic architecture model is converted into a corresponding AADL logic architecture model according to a conversion rule, wherein the converted model can be directly opened through an OSATE tool, and the conversion rule provided by the method is shown in the following tables 2 and 3:
TABLE 2 SysML model and AADL model conversion rules
TABLE 3FACE Profile model and AADL model conversion rules
Specifically, step 3, performing physical architecture design modeling on the complex real-time embedded system according to a logic architecture-based physical architecture design, and then converting the SysML and MARTE Profile physical architecture models into AADL physical architecture models by a model automatic conversion method, which is specifically as follows:
based on a logic architecture, the physical architecture design modeling of the complex real-time embedded system is carried out by using Modsim, MARTE Profile is loaded and applied, and the software and hardware composition and distribution relation of the embedded system are specifically defined by adopting elements in MARTE. The BDD graph is used for describing the decomposition composition relationship of the system, the top Block represents the system, other blocks represent physical components (or subsystems), ports on the blocks are used for representing data exchange ports of the physical components, and the composition connection relationship is used for describing the composition structure of the system. SysMLBlock is used to represent the system and subsystems, and MARTE elements are used to define the hardware and software components of the subsystems. Representing the internal composition relationship in an Internal Block Diagram (IBD) of the Block, wherein if Property represents specific software and hardware, the type of Property should be a well-defined MARTE element; if Property represents a subsystem, the type is the subsystem type defined by Block. The allocation relationship between hardware and software of MARTE elements is described by using allocate, and the allocation relationship between a logic architecture (logic component) and a physical architecture (hardware and software represented by MARTE elements) is described by using a traceback matrix, wherein MARTE Profile is implemented as shown in FIG. 5, and a modeling example graph is shown in FIG. 6. The derived requirements of the system physical architecture design are identified by creating a requirement graph representation, and finally, a SysML IBD graph representing a physical architecture model is converted into a corresponding AADL physical architecture model according to a conversion rule, wherein the converted model can be directly opened through an OSATE tool, and the conversion rule provided by the method is shown in the following tables 4 and 5:
TABLE 4 SysML model and AADL model conversion rules
TABLE 5MARTE Profile model and AADL model transformation rules
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, but various changes may be apparent to those skilled in the art, and it is intended that all inventive concepts utilizing the inventive concepts set forth herein be protected without departing from the spirit and scope of the present invention as defined and limited by the appended claims.
Claims (6)
1. A method for architecture design and architecture conversion based on a complex real-time embedded system is characterized by comprising the following steps:
step 1, performing SysML functional architecture design modeling on a complex real-time embedded system based on low-level requirements and design constraints of the complex real-time embedded system, and then converting the SysML functional architecture model into an AADL functional architecture model by using an automatic model conversion method;
step 2, designing a logic architecture based on the functional architecture, designing and modeling SysML and FACE Profile logic architectures of the complex real-time embedded system, and then converting the SysML and FACE Profile logic architecture models into AADL logic architecture models through an automatic model conversion method;
and 3, designing a physical architecture based on the logic architecture, designing and modeling SysML and MARTE Profile physical architectures of the complex real-time embedded system, and converting the SysML and MARTE Profile physical architecture models into AADL physical architecture models by using an automatic model conversion method.
2. The architecture design and architecture conversion method based on the complex real-time embedded system as claimed in claim 1, wherein the step 1 is to model the SysML functional architecture design according to the low-level requirements and design constraints of the complex real-time embedded system, and then to complete the conversion to the AADL functional architecture model, specifically comprising:
based on the low-level requirements and design constraints of the complex real-time embedded system, designing a functional architecture of the complex real-time embedded system, and firstly establishing the functional architecture of the system, including the allocation of system functional elements and the establishment of a functional hierarchy; then, analyzing and defining the interface of the system functional architecture element, then identifying the derived requirement of the system functional architecture design, and finally converting the SysML functional architecture model into an AADL functional architecture model;
the functional architecture design modeling is mainly used for carrying out functional analysis and design according to use cases of a complex real-time embedded system to generate a functional architecture, concepts of a functional group and functions are abstracted from the functional architecture, the functional group comprises a plurality of functions, both the concepts are represented by using blocks in SysML or the concepts are packaged by using profiles, in order to distinguish the blocks representing the functional group and the functions from the blocks representing the system, the functional group and the functions are independently organized by using packets, a Block Definition Diagram (BDD) is mainly used for describing the decomposition structures of the functional group and the functions, data stream interaction among the functions in the functional group is described by using an Internal Block Diagram (IBD), the functional stream is described by using an activity diagram, the functional interaction is described by using a sequence diagram, a dynamic behavior model of a functional element is described by using a state diagram, ports representing the functions represent information stream ports of the functions, and Connection is used for representing information stream Connection relations among the functions.
3. The architecture design and architecture conversion method based on the complex real-time embedded system as claimed in claim 1, wherein the step 2 is to design the logic architecture based on the functional architecture, to model the logic architecture design of SysML and FACE Profile, and then to complete the conversion to the AADL logic architecture model, specifically comprising:
designing a logic architecture based on a functional architecture, and firstly defining logic composition, including establishing a logic set, defining a logic entity, determining a mapping relation from the logic entity to a functional element and distributing performance indexes; then, performing interface analysis and definition of a system logic architecture, then identifying derived requirements of system logic architecture design, and finally converting the SysML and FACE Profile logic architecture model into an AADL logic architecture model, which specifically comprises the following steps:
the logic architecture design modeling mainly comprises the steps of modeling and designing the logic composition of a complex real-time embedded system, representing the system composition in a logic component mode, distributing functions in a functional architecture into the logic components, describing the decomposition composition relationship of the system by using a BDD (building description device) diagram, representing the system by using the topmost Block, representing the logic components or subsystems by using other blocks, representing data exchange ports of the logic components by using ports on the Block, and describing the system composition structure by using a composition connection relationship. Establishing an Interface packet describing a data exchange Port in a corresponding packet in a logic architecture, wherein specific data modeling of the data exchange Port is carried out in a BDD (domain data description) diagram by adopting FACE Profile, and association of a FACE data model and the Port is realized by selecting the type of the Port of a logic assembly as data established by a FACE data model element; describing the interaction relationship between the top-level logic components of the system and the data interaction relationship between sub-components inside each top-level logic component by using an IBD graph; connection Connector is used to represent data connections between logical components (represented by Property); the method comprises the steps that an IBD graph is used for describing distribution relations between functions in a functional architecture and logic components in a logic architecture, a Block representing the functions is dragged into the BDD graph in a Property form, the Block of the logic components is dragged in the same way, the functions are distributed to the logic components by using allocate, when a model is more complex allocate relations, the distribution relations between the functions and the logic components are described in a tracing matrix form, and dynamic behavior verification of the logic architecture is performed by describing dynamic behaviors of logic entities based on a state graph model of the logic entities.
4. The architecture design and architecture conversion method according to claim 1, wherein the step 3 is to design the physical architecture based on the logic architecture, to model the physical architecture design of the complex real-time embedded system by SysML and MARTE Profile, and then to complete the conversion to the AADL physical architecture model, and the specific content is:
designing a physical architecture based on a function and logic architecture, firstly defining physical composition, including establishing a physical set, defining a physical entity, determining a mapping relation from the physical entity to the logic entity, converting a performance index to a physical index, and distributing the physical index; then, performing interface analysis and definition of a system physical architecture, then identifying derived requirements of system physical architecture design, and finally converting the SysML and MARTE Profile physical architecture model into an AADL physical architecture model, which specifically comprises the following steps:
the physical architecture design modeling is introduced into MARTE, the software and hardware composition and distribution relationship of an embedded system are specifically defined by adopting elements in MARTE, a BDD graph is used for describing the decomposition composition relationship of the system, the Block at the top represents the system, other blocks represent physical components or subsystems, ports on the blocks are used for representing data exchange ports of the physical components, and the composition connection relationship is used for describing the composition structure of the system; using SysMLBlock to represent a system and a subsystem, using MARTE elements to define the software and hardware composition of the subsystem, and representing the internal composition relationship in an Internal Block Diagram (IBD) of the Block, wherein if Property represents specific software and hardware, the type of the Property should be defined MARTE elements; if Property represents a subsystem, the type of the Property is a subsystem type defined by Block, allocate is used for describing software and hardware allocation relations among MARTE elements, and a traceback matrix is used for describing allocation relations between a logic architecture and a physical architecture.
5. The architecture design and architecture conversion method based on the complex real-time embedded system according to claim 1, wherein the same conversion method is adopted for the conversion from the complex real-time embedded system architecture model to the AADL model in steps 1, 2 and 3, and the specific contents are as follows:
aiming at the automatic conversion from a SysML model, a FACE Profile model and an MARTE Profile model to an AADL model, the SysML model, the FACE Profile model, the MARTE Profile model and the AADL model need to be isomorphic under the same meta model system, and then semantic mapping and syntax conversion are carried out; defining SysML model, FACE Profile model, MARTE Profile model and AADL meta model through the same meta model; the SysML meta-model, the FACE Profile meta-model, the MARTE Profile meta-model and the AADL meta-model are constructed through MOF, the models are simultaneously in an MOF meta-model system, so that semantic mapping can be performed on two languages in the same environment, then semantic mapping rules of the SysML subset meta-model and the AADL subset meta-model are defined in an M2 meta-model layer, specific grammars are constructed for the AADL subset meta-model, and the EMF framework is used for automatically realizing the semantic mapping.
6. The architecture design and architecture conversion method based on the complex real-time embedded system according to claim 1, wherein the method is automatically implemented by an EMF framework, and specifically comprises: developing an Ecore meta-model in Eclipse, wherein the Ecore meta-model is used for describing a SysML model structure XMI file of a complex real-time embedded system functional architecture; the Ecore model generates a parser, and the parser reads out a SysML model structure representing a functional architecture in the XMI file, so as to create an EMF model in Eclipse; establishing mapping from elements in the EMF model to elements in the AADL by traversing the EMF model corresponding to the SysML model of the functional architecture, establishing an AADL object corresponding to the components and a mapping relation from EMF to AADL on the basis of established conversion rules, and establishing the relation among the components by using a model connector so as to obtain the AADL functional architecture model; similarly, the logical architecture models of SysML and FACE Profile and the physical architecture models of SysML and MARTE Profile are converted into AADL logical architecture model and AADL physical architecture model, respectively.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106096126A (en) * | 2016-06-08 | 2016-11-09 | 华东师范大学 | A kind of modeling method of information physical emerging system based on SysML/MARTE |
| US10181059B1 (en) * | 2007-06-19 | 2019-01-15 | The Mathworks, Inc. | Modeling a physical component interface in a unified modeling language model |
| CN110286902A (en) * | 2019-05-31 | 2019-09-27 | 南京航空航天大学 | SysML safety extension and its automatic switching method to AADL fault model |
| CN112764724A (en) * | 2021-01-21 | 2021-05-07 | 北京航空航天大学 | Model-based avionics system software component generation method and device |
| CN114036769A (en) * | 2021-11-18 | 2022-02-11 | 中国航空无线电电子研究所 | Avionics system physical architecture-oriented function deployment scheme generation method and device |
-
2022
- 2022-11-17 CN CN202211458349.0A patent/CN115712420B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10181059B1 (en) * | 2007-06-19 | 2019-01-15 | The Mathworks, Inc. | Modeling a physical component interface in a unified modeling language model |
| CN106096126A (en) * | 2016-06-08 | 2016-11-09 | 华东师范大学 | A kind of modeling method of information physical emerging system based on SysML/MARTE |
| CN110286902A (en) * | 2019-05-31 | 2019-09-27 | 南京航空航天大学 | SysML safety extension and its automatic switching method to AADL fault model |
| CN112764724A (en) * | 2021-01-21 | 2021-05-07 | 北京航空航天大学 | Model-based avionics system software component generation method and device |
| CN114036769A (en) * | 2021-11-18 | 2022-02-11 | 中国航空无线电电子研究所 | Avionics system physical architecture-oriented function deployment scheme generation method and device |
Non-Patent Citations (1)
| Title |
|---|
| 邓佳佳等: ""基于SysML___AAD...刹车控制系统实时性需求验证"", 《计算机与现代化》, pages 40 - 49 * |
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