CN115706613A

CN115706613A - DCI receiving method, DCI transmitting method, terminal, network device and storage medium

Info

Publication number: CN115706613A
Application number: CN202110898590.4A
Authority: CN
Inventors: 汤文
Original assignee: Datang Mobile Communications Equipment Co Ltd
Current assignee: Datang Mobile Communications Equipment Co Ltd
Priority date: 2021-08-05
Filing date: 2021-08-05
Publication date: 2023-02-17

Abstract

The application provides a DCI receiving method, a DCI sending method, a terminal, network equipment and a storage medium, wherein the method comprises the following steps: the terminal receives DCI, wherein the DCI comprises at least one of a HARQ process identification field and a feedback timing indication field, and the terminal further comprises: at least one of an FDRA field and a PUCCH resource indication field: the terminal determines target content, wherein the determined target content comprises at least one of the following items: determining an HARQ process identifier according to the bit and the first bit of the HARQ process identifier field; and determining a feedback timing indication according to the bit and the second bit of the feedback timing indication field, or determining the feedback timing indication according to the HARQ process identifier and the bit of the feedback timing indication field. The application can improve the indication effect of the DCI.

Description

DCI receiving method, DCI transmitting method, terminal, network device and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to a receiving method, a sending method, a terminal, a network device, and a storage medium for Downlink Control Information (DCI).

Background

The DCI may include a Hybrid Automatic Repeat Request (HARQ) process identifier field and a feedback timing indicator field, and the number of bits of the HARQ process identifier field and the number of bits of the feedback timing indicator field are often fixed in some communication systems, which results in less content that can be indicated by the HARQ process identifier field and the feedback timing indicator field, and thus results in a poor DCI indication effect.

Disclosure of Invention

The embodiment of the application provides a DCI receiving method, a DCI sending method, a terminal, network equipment and a storage medium, so as to solve the problem that the DCI indication effect is poor.

The embodiment of the application provides a DCI receiving method, which comprises the following steps:

the terminal receives DCI, wherein the DCI comprises at least one of a hybrid automatic repeat request (HARQ) process identification field and a feedback timing indication field, and the terminal further comprises: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) Resource indication field:

the terminal determines target content, wherein the determined target content comprises at least one of the following items:

determining an HARQ process identifier according to the bit and the first bit of the HARQ process identifier field;

determining a feedback timing indication according to the bit of the feedback timing indication field and the second bit, or determining the feedback timing indication according to the HARQ process identifier and the bit of the feedback timing indication field;

wherein the first bit comprises a first bit of the FDRA field or the PUCCH resource indication field;

the second bit comprises a second bit of the FDRA field or the PUCCH resource indication field.

Optionally, the first bit of the FDRA field includes:

the lowest bit in the FDRA information carried by the FDRA field;

determining the HARQ process identifier according to the bit and the first bit of the HARQ process identifier field, including:

and determining the HARQ process identifier according to the bit of the HARQ process identifier field and the lowest bit in the FDRA information carried by the FDRA field.

Optionally, the least significant bit in the FDRA information is used as the most significant bit of the HARQ process identifier; or

And the lowest bit in the FDRA information is used as the lowest bit of the HARQ process identifier.

Optionally, the first bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The lowest order bits of the PUCCH resource indication field;

determining the HARQ process identification according to the bit of the HARQ process identification field and the highest bit of the PUCCH resource indication field; or

And determining the HARQ process identifier according to the bits of the HARQ process identifier field and the least significant bits of the PUCCH resource indicator field.

Optionally, the most significant bit of the PUCCH resource indication field is used as the most significant bit of the HARQ process identifier; or

The most significant bit of the PUCCH resource indication field is used as the least significant bit of the HARQ process identifier; or alternatively

The lowest order bit of the PUCCH resource indication field is used as the highest order bit of the HARQ process identification; or

And the least significant bit of the PUCCH resource indication field is used as the least significant bit of the HARQ process identification.

Optionally, when the DCI is DCI format 0_0 or DCI format 0 _u1, the HARQ process identifier includes a bit of a HARQ process identifier field in the DCI, and further includes: a first bit of an FDRA field in the DCI; or alternatively

When the DCI is DCI format 1_0 or the DCI is DCI format 1 _u1, the HARQ process identifier includes a bit of a HARQ process identifier field in the DCI, and further includes: a first bit of an FDRA field in the DCI; or

When the DCI is DCI format 1_0 or the DCI is DCI format 1 _u1, the HARQ process identifier includes a bit of a HARQ process identifier field in the DCI, and further includes: a first bit of a PUCCH resource indication field in the DCI.

Optionally, the second bit of the FDRA field includes:

the lowest bit in the FDRA information carried by the FDRA field;

the determining a feedback timing indication according to the bit and the second bit of the feedback timing indication field includes:

and determining the feedback timing indication according to the bit of the feedback timing indication field and the lowest bit in the FDRA information carried by the FDRA field.

Optionally, the least significant bit in the FDRA information is used as the most significant bit of the feedback timing indication; or alternatively

The least significant bit in the FDRA information is used as the least significant bit of the feedback timing indication.

Optionally, the second bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or alternatively

The lowest order bits of the PUCCH resource indication field;

determining a feedback timing indication according to the bit of the feedback timing indication field and the most significant bit of the PUCCH resource indication field; or

And determining feedback timing indication according to the bit of the feedback timing indication field and the lowest bit of the PUCCH resource indication field.

Optionally, the most significant bit of the PUCCH resource indication field is used as the most significant bit of the feedback timing indication; or alternatively

The most significant bit of the PUCCH resource indication field is used as the least significant bit of the feedback timing indication; or

The lowest order bit of the PUCCH resource indication field is used as the highest order bit of the feedback timing indication; or alternatively

The lowest order bits of the PUCCH resource indication field are used as the lowest order bits of the feedback timing indication.

Optionally, when the DCI is DCI format 0_0 or DCI format 0_1, the feedback timing indication includes a bit of a feedback timing indication field in the DCI, and further includes: a second bit of an FDRA field in the DCI; or

In a case that the DCI is DCI format 1_0 or the DCI is DCI format 1 _u1, the feedback timing indication includes bits of a feedback timing indication field in the DCI, and further includes: a second bit of an FDRA field in the DCI; or

In a case that the DCI is DCI format 1_0 or the DCI is DCI format 1_1, the feedback timing indication includes a bit of a feedback timing indication field in the DCI, and further includes: a second bit of a PUCCH resource indication field in the DCI.

Optionally, the determining the feedback timing indication according to the HARQ process identifier and the bit of the feedback timing indication field includes:

under the condition that the HARQ process identifier is in the first identifier range, determining feedback timing indication in a first timing set according to bits of the feedback timing indication field; or alternatively

And under the condition that the HARQ process identifier is in a second identifier range, determining a feedback timing indication in a second timing set according to the bits of the feedback timing indication field.

Optionally, the HARQ process identifier number included in the first identifier range is equal to the HARQ process identifier number included in the second identifier range;

the first timing set includes a number of timings equal to a number of timings included in the second timing set.

An embodiment of the present application provides a DCI sending method, including:

the network equipment transmits DCI, wherein the DCI comprises at least one of a hybrid automatic repeat request (HARQ) process identification field and a feedback timing indication field, and further comprises: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field;

wherein, the bit and the first bit of the HARQ process identification field are used for determining the HARQ process identification; and/or a bit and a second bit of the feedback timing indication field are used for determining a feedback timing indication, or the feedback timing indication corresponding to the DCI is determined by a HARQ process identifier and the bit of the feedback timing indication field;

the first bit comprises a first bit of the FDRA field or the PUCCH resource indication field;

the second bit includes: a second bit of the FDRA field or the PUCCH resource indication field.

An embodiment of the present application provides a terminal, including: a memory, a transceiver, and a processor, wherein:

the memory for storing a computer program; the transceiver is used for transceiving data under the control of the processor; the processor is used for reading the computer program in the memory and executing the following operations:

receiving DCI, the DCI including at least one of a hybrid automatic repeat request (HARQ) process identification field and a feedback timing indication field, and further comprising: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field:

determining targeted content, the determining targeted content comprising at least one of:

Optionally, the first bit of the FDRA field includes:

the lowest bit in the FDRA information carried by the FDRA field;

the determining the HARQ process identifier according to the bit of the HARQ process identifier field and the first bit includes:

Optionally, the first bit of the PUCCH resource indication field includes:

The lowest order bits of the PUCCH resource indication field;

Optionally, the second bit of the FDRA field includes:

the least significant bit in the FDRA information carried by the FDRA field;

and determining feedback timing indication according to the bit of the feedback timing indication field and the lowest bit in the FDRA information carried by the FDRA field.

Optionally, the second bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field;

under the condition that the HARQ process identifier is in the first identifier range, determining feedback timing indication in a first timing set according to bits of the feedback timing indication field; or

And under the condition that the HARQ process identifier is in a second identifier range, determining feedback timing indication in a second timing set according to bits of the feedback timing indication field.

An embodiment of the present application provides a network device, including: a memory, a transceiver, and a processor, wherein:

a memory for storing a computer program; a transceiver for transceiving data under the control of the processor; a processor for reading the computer program in the memory and performing the following operations:

sending Downlink Control Information (DCI), wherein the DCI comprises at least one of a hybrid automatic repeat request (HARQ) process identification field and a feedback timing indication field, and further comprises: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field;

wherein, the bit and the first bit of the HARQ process identification field are used for determining the HARQ process identification; and/or bits and second bits of the feedback timing indication field are used for determining feedback timing indication, or feedback timing indication corresponding to the DCI is determined by HARQ process identification and bits of the feedback timing indication field;

An embodiment of the present application provides a terminal, including:

a receiving unit, configured to receive DCI, where the DCI includes at least one of a hybrid automatic repeat request HARQ process identification field and a feedback timing indication field, and further includes: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field:

a determining unit configured to determine target content, wherein the target content includes at least one of:

An embodiment of the present application provides a network device, including:

a sending unit, configured to send DCI, where the DCI includes an HARQ process identifier and a feedback timing indication;

wherein the HARQ process identifier includes bits of a HARQ process identifier field in the DCI, and a first bit of a frequency domain resource allocation FDRA field or a physical uplink control channel PUCCH resource indication field in the DCI; and/or the feedback timing indication comprises bits of a feedback timing indication field in the DCI and second bits of a Frequency Domain Resource Allocation (FDRA) field or a Physical Uplink Control Channel (PUCCH) resource indication field in the DCI; and/or, the HARQ process identification and the bits of the feedback timing indication field are used for determining the feedback timing indication.

A processor-readable storage medium according to an embodiment of the present application is characterized in that the processor-readable storage medium stores a computer program, where the computer program is configured to enable the processor to execute the DCI receiving method according to the embodiment of the present application, or the computer program is configured to enable the processor to execute the DCI transmitting method according to the embodiment of the present application.

In this embodiment, a terminal receives DCI, where the DCI includes at least one of a HARQ process identifier field and a feedback timing indication field, and further includes: at least one of an FDRA field and a PUCCH resource indication field: the terminal determines target content, wherein the determined target content comprises at least one of the following items: determining an HARQ process identifier according to the bit of the HARQ process identifier field and the first bit; determining a feedback timing indication according to the bit of the feedback timing indication field and the second bit, or determining the feedback timing indication according to the HARQ process identifier and the bit of the feedback timing indication field; wherein the first bit comprises a first bit of the FDRA field or the PUCCH resource indication field; the second bit comprises a second bit of the FDRA field or the PUCCH resource indication field. By the method, more HARQ processes can be indicated by the DCI, and/or more feedback timings can be indicated by the DCI, so that the indication effect of the DCI can be improved.

Drawings

FIG. 1 is a block diagram of a network architecture in which the present application may be implemented;

fig. 2 is a flowchart of a DCI receiving method according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of an FDRA field according to an embodiment of the present application;

fig. 4 is a flowchart of a DCI sending method according to an embodiment of the present application;

fig. 5 is a block diagram of a terminal according to an embodiment of the present disclosure;

fig. 6 is a block diagram of a network device according to an embodiment of the present application;

fig. 7 is a block diagram of another terminal provided in an embodiment of the present application;

fig. 8 is a block diagram of another network device according to an embodiment of the present application.

Detailed Description

To make the technical problems, technical solutions and advantages to be solved by the present application clearer, the following detailed description is made with reference to the accompanying drawings and specific embodiments.

In the embodiment of the present application, the term "and/or" describes an association relationship of associated objects, and means that there may be three relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

In the embodiments of the present application, the term "plurality" means two or more, and other terms are similar thereto.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The embodiment of the application provides an information sending method, an information receiving method, a terminal, network equipment and a storage medium, so as to solve the problem that the interaction performance between the terminal and a network side is poor.

The method and the device are based on the same application concept, and because the principles of solving the problems of the method and the device are similar, the implementation of the device and the method can be mutually referred, and repeated parts are not repeated.

The technical scheme provided by the embodiment of the application can be suitable for various systems, especially 6G systems. For example, the applicable system may be a global system for mobile communication (GSM) system, a Code Division Multiple Access (CDMA) system, a Wideband Code Division Multiple Access (WCDMA) General Packet Radio Service (GPRS) system, a long term evolution (long term evolution, LTE) system, an LTE Frequency Division Duplex (FDD) system, an LTE Time Division Duplex (TDD) system, an LTE-a (long term evolution) system, a universal mobile system (universal mobile telecommunications system, UMTS), a universal internet Access (WiMAX) system, a New Radio Access (WiMAX) system, a Radio Access (NR 5, new NR 6, etc. These various systems include terminal devices and network devices. The System may further include a core network portion, such as an Evolved Packet System (EPS), a 5G System (5 GS), and the like.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a network architecture to which the present application is applicable, and as shown in fig. 1, includes a terminal 11 and a network device 12.

The terminal according to the embodiments of the present application may be a device providing voice and/or data connectivity to a user, a handheld device having a wireless connection function, or another processing device connected to a wireless modem. In different systems, the names of the terminal devices may be different, for example, in a 5G system, the terminal device may be called a User Equipment (UE). A wireless terminal device, which may be a mobile terminal device such as a mobile phone (or called a "cellular" phone) and a computer having a mobile terminal device, for example, a portable, pocket, hand-held, computer-included or vehicle-mounted mobile device, may communicate with one or more Core Networks (CNs) via a Radio Access Network (RAN), and may exchange languages and/or data with the RAN. For example, devices such as Personal Communication Service (PCS) phones, cordless phones, session Initiation Protocol (SIP) phones, wireless Local Loop (WLL) stations, personal Digital Assistants (PDAs), redcap terminals, and Low Power Wide Area (LPWA) terminals. The wireless terminal device may also be referred to as a system, a subscriber unit (subscriber unit), a subscriber station (subscriber station), a mobile station (mobile station), a remote station (remote station), an access point (access point), a remote terminal (remote terminal), an access terminal (access terminal), a user terminal (user terminal), a user agent (user agent), and a user device (user device), which is not limited in this embodiment.

The network device according to the embodiment of the present application may be a base station, and the base station may include a plurality of cells for serving a terminal. A base station may also be called an access point, or may be a device in an access network that communicates over the air-interface, through one or more sectors, with wireless terminal devices, or by other names, depending on the particular application. The network device may be configured to exchange received air frames and Internet Protocol (IP) packets with one another as a router between the wireless terminal device and the rest of the access network, which may include an Internet Protocol (IP) communications network. The network device may also coordinate attribute management for the air interface. For example, the network device according to the embodiment of the present application may be a Base Transceiver Station (BTS) in a Global System for Mobile communications (GSM) or a Code Division Multiple Access (CDMA), may be a network device (NodeB) in a Wideband Code Division Multiple Access (WCDMA), may be an evolved Node B (eNB) or an e-NodeB) in a Long Term Evolution (LTE) System, may be a Base Station in a 5G Base Station (gNB) or a 6G Base Station in a 5G network architecture (next generation System), may be a Home evolved Node B (Home evolved Node B, heNB), a relay Node (relay Node), a Home Base Station (pico) or a pico Base Station (pico) in the present application, and the present application is not limited thereto. In some network configurations, a network device may include Centralized Unit (CU) nodes and Distributed Unit (DU) nodes, which may also be geographically separated.

The network device and the terminal may each use one or more antennas for Multiple Input Multiple Output (MIMO) transmission, and the MIMO transmission may be Single User MIMO (SU-MIMO) or Multi-User MIMO (MU-MIMO). According to the form and the number of the root antenna combination, the MIMO transmission can be 2D-MIMO, 3D-MIMO, FD-MIMO or massive-MIMO, and can also be diversity transmission, precoding transmission, beamforming transmission, etc.

Referring to fig. 2, fig. 2 is a flowchart of a DCI receiving method according to an embodiment of the present disclosure, and as shown in fig. 2, the DCI receiving method includes the following steps:

step 201, the terminal receives DCI, where the DCI includes at least one of a HARQ process identifier field and a feedback timing indication field, and further includes: at least one of a Frequency Domain Resource Allocation (FDRA) field and a PUCCH resource indication field (PUCCH resource indicator):

determining HARQ process identification (HARQ process number) according to the bit and the first bit of the HARQ process identification field;

determining a feedback timing indication according to the bit of the feedback timing indication field and the second bit, or determining the feedback timing indication according to the HARQ process identification and the bit of the feedback timing indication field;

The DCI is DCI transmitted by a network device received by a terminal, and may include DCI format 0/u 0/1.

The number of bits of the HARQ process number field may be protocol-defined or configured by higher layer parameters, such as: the bits of the higher layer parameter configuration DCI formats 0-2 and 1-2 are any one of 1,2, 3, and 4.

The feedback timing indication may be a K1 indication, and specifically may be a feedback timing indication (PDSCH-to-HARQ _ feedback indicator) from a Physical Downlink Shared Channel (PDSCH) to a HARQ. In addition, the bit number of the feedback timing indication field may be defined by a protocol or configured by a higher layer parameter, for example: the high-level parameter configures any one of

bit numbers

1,2, and 3 of the feedback timing indication field.

The bit number of the FDRA field may be determined according to a resource allocation type, for example: 8 bits or 9 bits or the like

The number of bits of the PUCCH resource indication field may be defined by a protocol, for example: 3 bits.

The first bit of the FDRA field may be 1 bit in the FDRA field, and the first bit of the PUCCH resource indication field may be 1 bit of the PUCCH resource indication field, and may also be 2 bits or more in some scenarios or embodiments.

The determining of the HARQ process identifier according to the bit of the HARQ process identifier field and the first bit may be that the HARQ process identifier is indicated according to the bit of the HARQ process identifier field and the first bit, so as to determine the HARQ process indicated by the DCI.

In the embodiment of the application, the indication of the HARQ process identifier can be realized by using the first bit of the FDRA field or the PUCCH resource indication field and the bit of the HARQ process identifier field, so that the bit number of the HARQ process identifier can be increased, and further, the HARQ process identifier included in DCI can indicate more HARQ processes, so as to improve the indication effect of DCI.

The determining of the feedback timing indication according to the bit of the feedback timing indication field and the second bit may be that the feedback timing indication is indicated according to the bit of the feedback timing indication field and the second bit to determine the feedback timing.

The determining of the feedback timing indication according to the HARQ process identifier and the bit of the feedback timing indication field may be determining the feedback timing indication according to a third bit corresponding to the HARQ process identifier and the bit of the feedback timing indication field. The third bit may be an extra bit added to the HARQ process identifier, for example: the first bit or the second bit. The HARQ process identifier may be an HARQ process identifier indicated by bits in the HARQ process identifier field of the DCI, or an HARQ process identifier indicated by the HARQ process identifier field of the DCI and bits additionally added to the HARQ process identifier, or the HARQ process identifier may be an HARQ process identifier indicated by other signaling, which is not limited.

In this way, the feedback timing indication is determined according to the HARQ process identifier and the bits of the feedback timing indication field, so that the DCI can indicate more feedback timings.

In the embodiment of the application, the feedback timing indication can be realized by using the first bit of the FDRA field or the PUCCH resource indication field and the bit of the feedback timing indication, so that the bit number of the feedback timing indication can be increased, and further, the feedback timing indication included in the DCI can indicate more feedback timings, so as to improve the DCI indication effect. In addition, by improving the indication effect of the DCI, the information transmission rate and reliability can be ensured.

It should be noted that the DCI provided in the embodiment of the present application may be applied to a Non-Terrestrial network (NTN) system, and certainly, may also be applied to a Terrestrial Network (TN) system, which is not limited in the embodiment of the present application.

In the embodiment of the present application, the FDRA field is mainly used for frequency domain Resource allocation, and the bit number of the FDRA field is related to the number of Resource blocks RB (Resource Block) of a corresponding uplink or downlink Bandwidth Part (BWP);

for example: if the number of bits of the resource allocation type 1,FDRA field is used is

Wherein the content of the first and second substances,

the number of RBs of uplink or downlink BWP;

for the Resource allocation type 0, the Resource allocation type is a non-continuous Resource allocation type at this time, the Resource allocation Resource is allocated according to Resource Block Groups (RBGs), one RBG is a Virtual Resource Block Group (VRB Group), and is composed of P continuous VRBs, the specific number is determined by the size of a high-level parameter RBG and the BWP bandwidth, and the size of the RBG determines whether the Resource allocation type is Resource allocation type 1 or Resource allocation type 2, as shown in the following table 1:

table 1:

BWP bandwidth	Resource allocation type 1	Resource allocation type 2
			1–36	2	4
37–72	4	8
			73–144	8	16
145–275	16	16

If the resource allocation type 0 is used, the number of bits of the FDRA field is N _RBG Wherein, in the process,

wherein the content of the first and second substances,

a BWP size corresponding to the BWP bandwidth in the table, wherein

Represents the starting RB number of BWP in the above table, and P is the RBG size for different resource allocation types and different BWP bandwidths in the above table.

For the simultaneous configuration of resource allocation type 1 and resource allocation type 0, the bit number of the FDRA field is then

As an optional implementation manner, the first bit of the FDRA field includes:

the lowest bit in the FDRA information carried by the FDRA field;

In this embodiment, the lowest order bit in the FDRA information can be used as both the bit in the FDRA information and the bit of the HARQ process identifier, that is, the lowest order bit in the FDRA information is used as an implicit indication of the extra bit of the HARQ process identifier field. That is, the least significant bit is used to indicate both contents at the same time.

Therefore, the indication effect of the HARQ process identification in the DCI is improved, and the indication of the FDRA information is not influenced.

For example: in some communication systems, the HARQ process id field and the FDRA field are configured in the same DCI format, and it is considered that the FDRA field needs to be configured for each process, that is, each process has a certain probability of corresponding HARQ process id range being (0, 15) or (16, 31). Assuming that there are 32 processes in a slot, in this embodiment, considering the randomness of the FDRA field configuration, the worst case of the configuration of the HARQ process identifier is one of (0, 15) or (16, 31), and the best case is the process ID configuration (0, 31).

In one embodiment, the least significant bit in the FDRA information is the most significant bit of the HARQ process identity.

Taking the comparison of the HARQ process identification fields as ABCD and the lowest bit in the FDRA information as X, the HARQ process identification is XABCD, so that the HARQ process identification can indicate more HARQ processes.

This embodiment is illustrated below by way of an example:

for resource allocation type 1, the allocated frequency domain resources are continuous resource allocation. Wherein, the bit corresponding to the FDRA field is used to indicate a Resource Indication Value (RIV), which includes a starting RB (RB _ start) allocated to a UE RB and a continuously allocated RB length L _ RBs, and the RIV calculation formula may be as follows:

if it is used

Then

Otherwise

Wherein L is _RBs Not less than 1 and not more than

Suppose that

In order to guarantee the transmission coding rate, the required frequency domain resource is 3RB, corresponding to 18 allocation modes, namely optional RB _start The first 3 consecutive RBs for (0,1,2, \ 8230;, 19), as shown in FIG. 3. The bit number of the FDRA field is

The network equipment can flexibly configure the frequency domain resources of the terminal according to the frequency domain multiplexing condition and the frequency domain interference condition, when the FDRA field is selected (00101000, 00101010, 00101100, 00101110, 00110000, 00110010, 00110100, 00110110, 00111000), the corresponding HARQ process identification range is (0, 15), namely X =0 in 'XABCD'; when the FDRA field is selectable (00101001, 00101011, 00101101, 00101111, 00110001, 00110011, 00110101, 00110111, 00111001), the corresponding HARQ process identification range is (16, 31), i.e., X =1 in "XABCD".

For resource allocation type 0, at this time, the resource allocation type is discontinuous, the resource allocation is allocated according to RBGs, one RBG is a VRB group, and is composed of P consecutive VRBs, the specific number is determined by the high-level parameters RBG size and BWP bandwidth, and the RBG size determines resource allocation type 1 or resource allocation type 2. Specific examples thereof are shown in Table 1 above.

The FDRA field contains N _ RBG bits, where 1 bit corresponds to 1 RBG, the highest bit represents RBG 0, the lowest bit represents RBG N _ RBG-1, and so on. If a certain RBG is allocated to a certain terminal, the corresponding bit in the bitmap is set to be 1; otherwise it is 0. Then the number of RBGs in a BWP is:

the network equipment can flexibly configure the frequency domain resources of the terminal according to the frequency domain multiplexing condition and the frequency domain interference condition, when the last bit of the FDRA field is 0, the corresponding HARQ process ID range is (0, 15), namely X =0 in 'XABCD'; when the last bit of the FDRA field is 1 and the corresponding HARQ process ID range is (16,31), i.e. X =1 in "XABCD".

For simultaneous configuration of resource allocation type 1 and resource allocation type0, when the FDRA field corresponds to

A bit. At this time, the most significant bit of the FDRA field is used to indicate a resource allocation type 0 or a resource allocation type 1, where a bit value of 0 indicates that the resource allocation type is 0, and a bit value of 1 indicates that the resource allocation type is 1. Refer to the above embodiments of resource allocation type 0 or resource allocation type 1, depending on the configuration of the most significant bits of the FDRA field.

In another embodiment, the least significant bits in the FDRA information are the least significant bits of the HARQ process identity.

Taking the comparison of the HARQ process identification fields as ABCD, the least significant bit in the FDRA information as X, and the HARQ process identification as ABCDX, so that the HARQ process identification can indicate more HARQ processes.

This embodiment is illustrated below by way of an example:

for resource allocation type 1, assume

In order to ensure the transmission coding rate, the required frequency domain resource is 3RB, which corresponds to 18 allocation modes, namely, the optional RB _start The first 3 consecutive RBs for (0,1,2, \ 8230;, 19), as shown in FIG. 3. When the FDRA field corresponds to

The number of bits is one,

the network device can flexibly configure the frequency domain resources of the UE according to the frequency domain multiplexing condition and the frequency domain interference condition, when the FDRA field is selected (00101000, 00101010, 00101100, 00101110, 00110000, 00110010, 00110100, 00110110, 00111000), that is, X =0 in "ABCDX", the corresponding HARQ process ID is (0, 2,4,6,8,10,12,14,16,18,20,22,24,26,28, 30); when the FDRA field is selected (00101001, 00101011, 00101101, 00101111, 00110001, 00110011, 00110101, 00110111, 00111001), that is, X =1 in "ABCDX", the corresponding HARQ process ID is (1, 3,5,7,9,11,13,15,17,19,21,23,25,27,29, 31).

For the resource allocation type 0, the network device may flexibly configure the frequency domain resource of the UE according to the frequency domain multiplexing condition and the frequency domain interference condition, when the last bit of the FDRA field is 0, the corresponding HARQ process ID is (0, 2,4,6,8,10,12,14,16,18,20,22,24,26,28, 30), i.e. X =0 in "ABCDX"; when the last bit of the Frequency domain resource assignment field is 1, the corresponding HARQ process ID is (1, 3,5,7,9,11,13,15,17,19,21,23,25,27,29, 31), i.e., X =1 in "ABCDX".

For the simultaneous configuration of resource allocation type 1 and resource allocation type 0, the FDRA field corresponds to the resource allocation type 1

It should be noted that, in the embodiment of the present application, the first bit of the FDRA field is not limited to be the lowest bit in the FDRA information carried by the FDRA field, for example: in some scenarios or embodiments, the first bit of the FDRA field is a second last bit and a third last bit in FDRA information carried by the FDRA field.

As an optional implementation manner, the first bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The lowest order bits of the PUCCH resource indication field;

determining HARQ process identification according to the bits of the HARQ process identification field and the most significant bits of the PUCCH resource indication field; or alternatively

In this embodiment, the most significant bit/the least significant bit in the PUCCH resource indication field may be used as both the bits in the PUCCH resource indication field and the bits of the HARQ process identifier, that is, the most significant bit/the least significant bit in the PUCCH resource indication field may be used as an implicit indication of the extra bits of the HARQ process identifier field. That is, the most significant bit/the least significant bit described above are used to indicate two contents at the same time.

Therefore, the indication effect of the DCIHARQ process identification is improved, and the indication of the PUCCH resource indication field is not influenced.

For example: the PUCCH resource indication field may be present in DCI format 1/0, 1, and is a field mainly used for resource allocation of PUCCH, and the field is defined to be 3 bits in the protocol. For DCI format 1/0/1, it is considered that the PUCCH resource indicator field needs to be configured for each process, that is, there is a certain probability for each process to take the corresponding HARQ process identifier range to be (0, 15) or (16, 31). Assuming that there are 32 processes in one slot, this embodiment considers the randomness of the PUCCH resource indication field configuration, where the worst case of the process ID configuration is one of (0, 15) or (16, 31), and the best case is the process ID configuration (0, 31), and the PUCCH resource indication field has higher flexibility and can avoid the influence on other fields in DCI.

In one embodiment, the most significant bit of the PUCCH resource indication field is used as the most significant bit of the HARQ process identifier; or

And the lowest order bits of the PUCCH resource indication field are used as the highest order bits of the HARQ process identification.

Taking the comparison of the HARQ process identifier field as ABCD, and the most significant bit/the least significant bit of the PUCCH resource indicator field as X, the HARQ process identifier is XABCD, so that the HARQ process identifier may indicate more HARQ processes.

This embodiment is illustrated below by way of an example:

for the least significant bit/the most significant bit of the PUCCH resource indication field as the most significant bit of the HARQ process identifier, the high layer RRC signaling configures 1 or more PUCCH resource sets, each resource set includes multiple PUCCH resources, and after the terminal receives the downlink scheduling information, a determined PUCCH resource is found in 1 PUCCH resource set according to the PUCCH resource indication field in the DCI, as shown in table 2 below.

Table 2:

the network device can utilize the high-layer RRC signaling to dynamically configure the PUCCH resource indication field, so as to flexibly configure the PUCCH resource indication field, when the lowest bit/highest bit of the PUCCH resource indication field is 0 and the corresponding HARQ process identification range is (0, 15), namely X =0 in XABCD; when the least significant bit/most significant bit of the PUCCH resource indication field is 1, the corresponding HARQ process identification range is (16,31), i.e., X =1 in "XABCD".

In another embodiment, the most significant bit of the PUCCH resource indication field is the least significant bit of the HARQ process identity; or

The lowest order bits of the PUCCH resource indication field are used as the lowest order bits of the HARQ process identification.

Taking the comparison of the HARQ process identifier field as ABCD, the most significant bit/the least significant bit in the PUCCH resource indication field as X, and the HARQ process identifier as ABCDX, so that the HARQ process identifier may indicate more HARQ processes.

This embodiment is illustrated below by way of an example:

for the least significant bit/the most significant bit of the indicator field of the PUCCH resource used as the least significant bit of the HARQ process identifier, the higher layer RRC signaling configures 1 or more PUCCH resource sets, each resource set includes multiple PUCCH resources, and after receiving the downlink scheduling information, the UE finds a certain PUCCH resource in the 1 PUCCH resource set according to the indicator field of the PUCCH resource in the DCI, as shown in table 4.

The network device can utilize the high layer RRC signaling to dynamically configure the PUCCH resource, so as to flexibly configure the PUCCH resource indication field, when the least significant bit/most significant bit of the PUCCH resource indication field is 0, corresponding to the HARQ process ID (0, 2,4,6,8,10,12,14,16,18,20,22,24,26,28, 30), i.e., X =0 in "ABCDX"; when the least significant bit/most significant bit of the PUCCH resource indication field is 1, the corresponding HARQ process ID (1, 3,5,7,9,11,13,15,17,19,21,23,25,27,29, 31), i.e., X =1 in "ABCDX".

As an optional implementation manner, in a case that the DCI is DCI format 0_0 or the DCI is DCI format 0 _u1, the HARQ process identifier includes bits of a HARQ process identifier field in the DCI, and further includes: a first bit of an FDRA field in the DCI; or

When the DCI is DCI format 1_0 or the DCI is DCI format 1_1, the HARQ process identifier includes a bit of a HARQ process identifier field in the DCI, and further includes: a first bit of an FDRA field in the DCI; or

In this embodiment, it is possible to realize that for DCI format 0/1, DCI format 1/1 uses the least significant bit of FDRA or the least significant/most significant bit of PUCCH resource indication field as an implicit indication of 1 additional bit of HARQ process identifier, the impact on the information indicated by the FDRA field or the PUCCH resource indication field in the DCI can be avoided on the premise that flexibility on DCI format 0/1/0/1 \/1 and scheduling is not changed.

For example: DCI format 0/1 uses the least significant bit of FDRA as the least significant bit of HARQ process identification, and DCI1_0/1 uses the least significant bit/most significant bit of PUCCH resource indication field or the least significant bit of FDRA as the least significant bit of HARQ process identification

Another example is: DCI format 0/1 uses the lowest order bit of FDRA as the highest order bit of the HARQ process ID, and DCI format 1/1 uses the lowest order/highest order bit of the PUCCH resource indication field or the lowest order bit of FDRA as the highest order bit of the HARQ process ID.

As an optional implementation, the second bit of the FDRA field includes:

the least significant bit in the FDRA information carried by the FDRA field;

The least significant bit of the FDRA information may refer to the description of the above embodiments, and is not limited herein.

In this embodiment, the lowest order bit in the FDRA information can be used as both the bit in the FDRA information and the bit of the feedback timing indication, that is, the lowest order bit in the FDRA information is used as an implicit indication of the extra bit of the feedback timing indication. That is, the least significant bit is used to indicate both contents at the same time. Therefore, the premise of not changing the DCI format and the scheduling flexibility can be ensured, and the influence on the FDRA field is avoided.

In addition, since the second bit of the FDRA field and the first bit of the FDRA field may be the same, bits added by the multiplexing HARQ process identifier may be used as bits additionally added for the feedback timing indication, and on the premise of ensuring scheduling flexibility, the increase of the interval corresponding to the feedback timing indication value does not additionally change the DCI format and is low in complexity.

It should be noted that, in some embodiments, the second bit of the FDRA field and the first bit of the FDRA field may be different, for example: the first bit of the FDRA field is the lowest bit of the FDRA information, and the second bit of the FDRA field may be the second last and third bits of the FDRA information.

In one embodiment, the least significant bit of the FDRA information is the most significant bit of the feedback timing indication.

Taking ABC as a bit of the feedback timing indication field and X as a least significant bit of the FDRA information, XABC is used as the feedback timing indication, so that more feedback timings can be indicated by the feedback timing indication.

This embodiment is illustrated below by way of an example:

for resource allocation type 1, the network device configures the HARQ process identity field and the FDRA field in the same DCI format, and when the FDRA field is selected (00101000, 00101010, 00101100, 00101110, 00110000, 00110010, 00110100, 00110110, 00111000), at this time, the corresponding feedback timing indication field range is (0, 7), that is, X =0 in XABC. The network equipment can flexibly configure the frequency domain resources of the terminal according to the frequency domain multiplexing condition and the frequency domain interference condition; when the FDRA field is selected (00101001, 00101011, 00101101, 00101111, 00110001, 00110011, 00110101, 00110111, 00111001), at this time, the corresponding FDRA field range is (8, 15), that is, X =1 in XABC, and the network device may flexibly configure the frequency domain resource of the terminal according to the frequency domain multiplexing condition and the frequency domain interference condition.

For the resource allocation type 0, when the last bit of the FDRA field is 0, at this time, the corresponding range of the feedback timing indication field is (0, 7), that is, X =0 in XABC, and the network device can flexibly configure the remaining bit frequency domain resources of the terminal according to the frequency domain multiplexing condition and the frequency domain interference condition; when the last bit of the FDRA field is 1, at this time, the corresponding range of the feedback timing indication field is (8, 15), that is, X =1 in XABC, and the network device may flexibly configure the remaining bit frequency-domain resources of the terminal according to the frequency-domain multiplexing condition and the frequency-domain interference condition.

In another embodiment, the least significant bit of the FDRA information is used as the least significant bit of the feedback timing indication.

Taking the comparison of the feedback timing indication field as ABC, the least significant bit in the FDRA information as X, and the feedback timing indication as ABCX, the feedback timing indication can indicate more feedback timings.

This embodiment is illustrated below by way of an example:

for resource allocation type 1, when the FDRA segment is selected (00101000, 00101010, 00101100, 00101110, 00110000, 00110010, 00110100, 00110110, 00111000), that is, X =0 in the ABCX, the corresponding feedback timing indication field is (0, 2,4,6,8,10,12, 14); when the FDRA field is selected (00101001, 00101011, 00101101, 00101111, 00110001, 00110011, 00110101, 00110111, 00111001), that is, X =1 in the ABCX, the corresponding feedback timing indication field is (1, 3,5,7,9,11,13, 15). The network device can flexibly configure the FDRA field and the feedback timing indication field of the terminal based on the frequency domain multiplexing situation and the frequency domain interference situation and the feedback timing indication required to be used.

For the resource allocation type 0, when the FDRA field only needs to ensure that the last bit is 0, at this time, the corresponding feedback timing indication field is (0, 2,4,6,8,10,12, 14), that is, X =0 in "ABCX", and the network device can flexibly configure the remaining bit frequency domain resources of the terminal according to the frequency domain multiplexing condition and the frequency domain interference condition; when the last bit of the FDRA field is 1, at this time, the corresponding feedback timing indication field is (1, 3,5,7,9,11,13, 15), that is, X =1 in the ABCX, and the network device may flexibly configure the remaining bit frequency domain resources of the terminal according to the frequency domain multiplexing condition and the frequency domain interference condition.

As an optional implementation manner, the second bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field;

For the most significant bit/the least significant bit of the PUCCH resource indication field, reference may be made to the description of the above embodiments, which is not limited herein.

In this embodiment, the most significant bit/the least significant bit of the PUCCH resource indication field can be used as both the bits in the PUCCH resource indication field and the bits of the feedback timing indication, that is, the most significant bit/the least significant bit of the PUCCH resource indication field is used as an implicit indication of the extra bits of the feedback timing indication. That is, the most significant bit/the least significant bit described above are used to indicate two contents at the same time. Therefore, the premise of not changing the DCI format and the scheduling flexibility can be ensured, and the influence on the PUCCH resource indication field is avoided.

In addition, since the second bit of the PUCCH resource indication field and the first bit of the PUCCH resource indication field may be the same, bits added by the multiplexing HARQ process identifier may be used as bits additionally added for feedback timing indication, and on the premise of ensuring scheduling flexibility, an increase in the interval corresponding to the feedback timing indication value does not additionally change the DCI format and is low in complexity.

It should be noted that, in some embodiments, the second bit of the PUCCH resource indication field and the first bit of the PUCCH resource indication field may be different, for example: the first bit of the PUCCH resource indication field is the lowest order bit in the PUCCH resource indication field, and the second bit of the PUCCH resource indication field may be the second to last, and third bits of the PUCCH resource indication field.

In one embodiment, the most significant bit of the PUCCH resource indication field is used as the most significant bit of the feedback timing indication; or

And the lowest bit of the PUCCH resource indication field is used as the highest bit of the feedback timing indication.

Taking the comparison of the feedback timing indication field as ABC, the most significant bit/the least significant bit of the PUCCH resource indication field as X, and the feedback timing indication as XABC, the feedback timing indication may indicate more feedback timings.

This embodiment is illustrated below by way of an example:

and for the highest bit using the lowest bit/highest bit of the PUCCH resource indication field as the highest bit of the feedback timing indication, configuring 1 or more PUCCH resource sets by high-level RRC signaling, wherein each resource set comprises a plurality of PUCCH resources, and after receiving downlink scheduling information, the terminal finds a determined PUCCH resource in the 1 PUCCH resource sets according to the PUCCH resource indication field in the DCI.

When the lowest bit/highest bit of the PUCCH resource indication field is 0, and at this time, the corresponding feedback timing indication field range is (0, 7), that is, X =0 in "XABC", the network device may utilize high layer RRC signaling to dynamically configure the PUCCH resource, thereby flexibly configuring the PUCCH resource indication field; when the PUCCH resource indication field only needs to ensure that the least significant bit/most significant bit is 1, at this time, the corresponding feedback timing indication field range is (8, 15), that is, X =1 in "XABC", and the network device may use higher layer RRC signaling to dynamically configure the PUCCH resource, thereby flexibly configuring the PUCCH resource indication field.

In another embodiment, the most significant bits of the PUCCH resource indication field are the least significant bits of the feedback timing indication; or alternatively

Taking the comparison of the feedback timing indication fields as ABC and the most significant bit/the least significant bit of the PUCCH resource indication fields as X, the feedback timing indication is ABCX, so that the feedback timing indication may indicate more feedback timings.

This embodiment is illustrated below by way of an example:

and using the lowest bit/highest bit of the PUCCH resource indication field as the lowest bit of the feedback timing indication, configuring 1 or more PUCCH resource sets by high-level RRC signaling, wherein each resource set comprises a plurality of PUCCH resources, and after receiving downlink scheduling information, the terminal finds a determined PUCCH resource in the 1 PUCCH resource sets according to the PUCCH resource indication field in the DCI.

When the least significant bit/most significant bit of the PUCCH resource indication field is 0, at this time, the corresponding feedback timing indication field is (0, 2,4,6,8,10,12, 14), that is, X =0 in ABCX, the network device may utilize higher layer RRC signaling to dynamically configure the PUCCH resource, thereby flexibly configuring the PUCCH resource indication field; when the least significant bit/most significant bit of the PUCCH resource indication field is 1, at this time, the corresponding feedback timing indication field is (1,3,5,7,9,11,13,15), that is, X =1 in the ABCX, the network device may use higher layer RRC signaling to dynamically configure the PUCCH resource, thereby flexibly configuring the PUCCH resource indication field.

As an optional implementation, in a case that the DCI is DCI format 0_0 or the DCI is DCI format 0 _u1, the feedback timing indication includes bits of a feedback timing indication field in the DCI, and further includes: a second bit of an FDRA field in the DCI; or alternatively

In a case that the DCI is DCI format 1_0 or the DCI is DCI format 1_1, the feedback timing indication includes a bit of a feedback timing indication field in the DCI, and further includes: a second bit of an FDRA field in the DCI; or alternatively

In a case that the DCI is DCI format 1_0 or the DCI is DCI format 1 _u1, the feedback timing indication includes bits of a feedback timing indication field in the DCI, and further includes: a second bit of a PUCCH resource indication field in the DCI.

In this embodiment, it is possible to realize that for DCI format 0/1, DCI format 1/1 uses the least significant bit of FDRA or the least significant/most significant bit of PUCCH resource indication field as an implicit indication of 1 additional bit of the feedback timing indication field, the impact on the information indicated by the FDRA field or the PUCCH resource indication field in the DCI can be avoided on the premise that flexibility on DCI format 0/1/0/1 \/1 and scheduling is not changed.

As an optional implementation manner, the determining a feedback timing indication according to the HARQ process identifier and the bit of the feedback timing indication field includes:

The first identification range and the second identification range may be predefined, for example: the first identification range and the second identification range correspond to a HARQ process identification (0, 15) and a HARQ process identification (16, 31), respectively. The first timing set and the second timing set may be predefined, for example: the first and second timing sets correspond to two timing sets, respectively, each timing set including 8 timing values.

And the feedback timing number included in each of the first timing set and the second timing set is an indicatable timing number of a bit of a feedback timing indication field in the DCI. For example: the feedback timing indication field is 3 bits, and the first timing set and the second timing set are two different timing sets including 8 timing values, respectively, so that the set that the feedback timing indication of the DCI can indicate is 16 timing values.

In this embodiment, since the feedback timing indications may indicate the feedback timings in the two timing sets respectively, the feedback timing indications included in the DCI may indicate more feedback timings, so as to improve the indication effect of the DCI.

As an optional implementation manner, the number of HARQ process identifiers included in the first identifier range is equal to the number of HARQ process identifiers included in the second identifier range;

This embodiment may be to bind both the additional 1 bit of HARQ process identification and the additional 1 bit of feedback timing indication. I.e. 1 bit increased by the HARQ process is used as 1 bit increased by the feedback timing indication.

The 32 HARQ processes considered in the NTN are divided into two groups, where the HARQ process range (0, 15) corresponds to one K1 set (8 values), and the HARQ process range (16, 31) corresponds to another K1 set (8 values), and on the premise of ensuring scheduling flexibility, the increase of the interval corresponding to the K1 value has no additional change to the DCI format and is low in complexity.

For example: dividing 32 HARQ processes considered in NTN into two groups, wherein the HARQ process range (0, 15) corresponds to one K1 set (8 values) and corresponds to (0, 7) of the feedback timing indication field range; the HARQ process range (16, 31) corresponds to another K1 set (8 values), corresponding to (8, 15) of the feedback timing indication field range.

In the embodiment of the present application, a terminal receives DCI, where the DCI includes at least one of a HARQ process identifier field and a feedback timing indication field, and further includes: at least one of an FDRA field and a PUCCH resource indication field: the terminal determines target content, wherein the determined target content comprises at least one of the following items: determining an HARQ process identifier according to the bit and the first bit of the HARQ process identifier field; determining a feedback timing indication according to the bit of the feedback timing indication field and the second bit, or determining the feedback timing indication according to the HARQ process identification and the bit of the feedback timing indication field; wherein the first bit comprises a first bit of the FDRA field or the PUCCH resource indication field; the second bit comprises a second bit of the FDRA field or the PUCCH resource indication field. By the method, more HARQ processes can be indicated by the DCI, and/or more feedback timings can be indicated by the DCI, so that the indication effect of the DCI can be improved.

Referring to fig. 4, fig. 4 is a flowchart of a DCI sending method according to an embodiment of the present application, and as shown in fig. 4, the method includes the following steps:

step 401, the network device sends DCI, where the DCI includes at least one of an HARQ process identifier field and a feedback timing indication field, and further includes: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field;

Optionally, the first bit of the FDRA field includes:

the FDRA field carries the least significant bits of FDRA information.

Optionally, the first bit of the PUCCH resource indication field includes:

The least significant bit of the PUCCH resource indication field.

Optionally, when the DCI is DCI format 0_0 or DCI format 0 _u1, the HARQ process identifier includes a bit of a HARQ process identifier field in the DCI, and further includes: a first bit of an FDRA field in the DCI; or

When the DCI is DCI format 1_0 or the DCI is DCI format 1 _u1, the HARQ process identifier includes a bit of a HARQ process identifier field in the DCI, and further includes: a first bit of an FDRA field in the DCI; or alternatively

Optionally, the second bit of the FDRA field includes:

the FDRA field carries the least significant bits of FDRA information.

Optionally, the least significant bit in the FDRA information is used as the most significant bit of the feedback timing indication; or

Optionally, the second bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field.

Optionally, the most significant bit of the PUCCH resource indication field is used as the most significant bit of the feedback timing indication; or

Optionally, when the DCI is DCI format 0_0 or DCI format 0_1, the feedback timing indication includes a bit of a feedback timing indication field in the DCI, and further includes: a second bit of an FDRA field in the DCI; or alternatively

In a case that the DCI is DCI format 1_0 or the DCI is DCI format 1 _u1, the feedback timing indication includes bits of a feedback timing indication field in the DCI, and further includes: a second bit of an FDRA field in the DCI; or alternatively

Optionally, in a case that the HARQ process identifier is in the first identifier range, the feedback timing indication is used to indicate timing in the first timing set; the feedback timing indication is used to indicate timing in a second set of timings in case the HARQ process identity is in a second identity range.

It should be noted that, this embodiment is used as an implementation of a network device corresponding to the embodiment shown in fig. 2, and specific implementations thereof may refer to relevant descriptions of the embodiment shown in fig. 2, so that, in order to avoid repeated descriptions, this embodiment is not described again, and the same beneficial effects may also be achieved.

Referring to fig. 5, fig. 5 is a block diagram of a terminal according to an embodiment of the present disclosure, as shown in fig. 5, including a memory 520, a transceiver 500, and a processor 510:

a memory 520 for storing a computer program; a transceiver 500 for transceiving data under the control of the processor 510; a processor 510 for reading the computer program in the memory 520 and performing the following operations:

receiving DCI, wherein the DCI comprises at least one of a hybrid automatic repeat request (HARQ) process identification field and a feedback timing indication field, and further comprises: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field:

Wherein in fig. 5 the bus architecture may comprise any number of interconnected buses and bridges, with one or more processors, represented by processor 510, and various circuits, represented by memory 520, being linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The transceiver 500 may be a number of elements including a transmitter and a receiver that provide a means for communicating with various other apparatus over transmission media including wireless channels, wired channels, fiber optic cables, and the like. For different user devices, the user interface 530 may also be an interface capable of interfacing externally to a desired device, including but not limited to a keypad, display, speaker, microphone, joystick, etc.

The processor 510 is responsible for managing the bus architecture and general processing, and the memory 520 may store data used by the processor 500 in performing operations.

Alternatively, the processor 510 may be a CPU (central processing unit), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a CPLD (Complex Programmable Logic Device), and the processor may also have a multi-core architecture.

The processor is used for executing any method provided by the embodiment of the application according to the obtained executable instructions by calling the computer program stored in the memory. The processor and memory may also be physically separated.

Optionally, the first bit of the FDRA field includes:

the least significant bit in the FDRA information carried by the FDRA field;

And the lowest bit in the FDRA information is used as the lowest bit of the HARQ process identification.

Optionally, the first bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field;

determining HARQ process identification according to the bits of the HARQ process identification field and the most significant bits of the PUCCH resource indication field; or

The lowest order bit of the PUCCH resource indication field is used as the highest order bit of the HARQ process identification; or alternatively

Optionally, the second bit of the FDRA field includes:

the lowest bit in the FDRA information carried by the FDRA field;

Optionally, the second bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field;

determining a feedback timing indication according to the bit of the feedback timing indication field and the highest bit of the PUCCH resource indication field; or alternatively

And determining feedback timing indication according to the bits of the feedback timing indication field and the least significant bits of the PUCCH resource indication field.

Optionally, a most significant bit of the PUCCH resource indication field is used as a most significant bit of the feedback timing indication; or

The lowest order bit of the PUCCH resource indication field is used as the highest order bit of the feedback timing indication; or

Optionally, the number of HARQ process identifiers included in the first identifier range is equal to the number of HARQ process identifiers included in the second identifier range;

It should be noted that, the terminal provided in the embodiment of the present application can implement all the method steps implemented by the method embodiment and achieve the same technical effect, and detailed descriptions of the same parts and beneficial effects as the method embodiment in this embodiment are omitted here.

Referring to fig. 6, fig. 6 is a block diagram of a network device according to an embodiment of the present application, and as shown in fig. 6, the network device includes a memory 620, a transceiver 600, and a processor 610:

a memory 620 for storing a computer program; a transceiver 600 for transceiving data under the control of the processor 610; a processor 610 for reading the computer program in the memory 620 and performing the following operations:

transmitting DCI, wherein the DCI comprises at least one of a hybrid automatic repeat request (HARQ) process identification field and a feedback timing indication field, and further comprises: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field;

Wherein in fig. 6, the bus architecture may include any number of interconnected buses and bridges, with one or more processors, represented by processor 610, and various circuits, represented by memory 620, being linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The transceiver 600 may be a number of elements including a transmitter and a receiver that provide a means for communicating with various other apparatus over transmission media including wireless channels, wired channels, fiber optic cables, and the like. For different user devices, the user interface 630 may also be an interface capable of interfacing with a desired device externally, including but not limited to a keypad, display, speaker, microphone, joystick, etc.

The processor 610 is responsible for managing the bus architecture and general processing, and the memory 620 may store data used by the processor 600 in performing operations.

Alternatively, the processor 610 may be a CPU (central processing unit), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a CPLD (Complex Programmable Logic Device), and the processor may also adopt a multi-core architecture.

The processor is used for executing any one of the methods provided by the embodiment of the application according to the obtained executable instructions by calling the computer program stored in the memory. The processor and memory may also be physically separated.

Optionally, the first bit of the FDRA field includes:

the FDRA field carries the least significant bits of FDRA information.

Optionally, the first bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field.

The most significant bit of the PUCCH resource indication field is used as the least significant bit of the HARQ process identifier; or

Optionally, when the DCI is DCI format 0_0 or DCI format 0_1, the HARQ process identifier includes a bit of a HARQ process identifier field in the DCI, and further includes: a first bit of an FDRA field in the DCI; or

When the DCI is DCI format 1_0 or the DCI is DCI format 1_1, the HARQ process identifier includes a bit of a HARQ process identifier field in the DCI, and further includes: a first bit of a PUCCH resource indication field in the DCI.

Optionally, the second bit of the FDRA field includes:

the FDRA field carries the least significant bits of FDRA information.

Optionally, the second bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field.

It should be noted that, the network device provided in the embodiment of the present application can implement all the method steps implemented by the method embodiment and achieve the same technical effect, and detailed descriptions of the same parts and beneficial effects as those of the method embodiment in this embodiment are not repeated herein.

Referring to fig. 7, fig. 7 is a structural diagram of another terminal according to an embodiment of the present application, and as shown in fig. 7, a terminal 700 includes:

a receiving unit 701, configured to receive DCI, where the DCI includes at least one of a hybrid automatic repeat request HARQ process identification field and a feedback timing indication field, and further includes: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field:

a determining unit 702 configured to determine target content, where the target content includes at least one of:

Optionally, the first bit of the FDRA field includes:

the least significant bit in the FDRA information carried by the FDRA field;

Optionally, the first bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field;

Optionally, the second bit of the FDRA field includes:

the lowest bit in the FDRA information carried by the FDRA field;

Optionally, the second bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The lowest order bits of the PUCCH resource indication field;

The most significant bit of the PUCCH resource indication field is used as the least significant bit of the feedback timing indication; or alternatively

And the lowest bit of the PUCCH resource indication field is used as the lowest bit of the feedback timing indication.

It should be noted that, the terminal provided in the embodiment of the present application can implement all the method steps implemented by the method embodiment and can achieve the same technical effects, and detailed descriptions of the same parts and beneficial effects as those of the method embodiment in this embodiment are omitted here.

Referring to fig. 8, fig. 8 is a structural diagram of another network device according to an embodiment of the present application, and as shown in fig. 8, a network device 800 includes:

a sending unit 801, configured to send DCI, where the DCI includes at least one of a hybrid automatic repeat request HARQ process identification field and a feedback timing indication field, and further includes: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field;

Optionally, the first bit of the FDRA field includes:

the FDRA field carries the least significant bits of FDRA information.

Optionally, the first bit of the PUCCH resource indication field includes:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field.

Optionally, when the DCI is DCI format 0_0 or DCI format 0_1, the HARQ process identifier includes a bit of a HARQ process identifier field in the DCI, and further includes: a first bit of an FDRA field in the DCI; or alternatively

Optionally, the second bit of the FDRA field includes:

the FDRA field carries the least significant bits of FDRA information.

Optionally, the second bit of the PUCCH resource indication field includes:

The least significant bit of the PUCCH resource indication field.

It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation. In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented as a software functional unit and sold or used as a stand-alone product, may be stored in a processor readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.

An embodiment of the present application further provides a processor-readable storage medium, where the processor-readable storage medium stores a computer program, where the computer program is configured to enable the processor to execute the information sending method provided in the embodiment of the present application, or the computer program is configured to enable the processor to execute the information receiving method provided in the embodiment of the present application.

The processor-readable storage medium may be any available medium or data storage device that can be accessed by a processor, including, but not limited to, magnetic memory (e.g., floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc.), optical memory (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor memory (e.g., ROMs, EPROMs, EEPROMs, non-volatile memories (NAND FLASH), solid State Disks (SSDs)), etc.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These processor-executable instructions may also be stored in a processor-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These processor-executable instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A method for receiving Downlink Control Information (DCI), comprising:

2. The method of claim 1, wherein the first bit of the FDRA field comprises:

the lowest bit in the FDRA information carried by the FDRA field;

3. The method of claim 2, wherein the least significant bits in the FDRA information are the most significant bits of the HARQ process identification; or

4. The method of claim 1, wherein the first bit of the PUCCH resource indication field comprises:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field;

5. The method of claim 4, wherein the most significant bit of the PUCCH resource indication field is the most significant bit of the HARQ process identification; or

6. The method of any of claims 1-5, wherein in the case that the DCI is DCI Format 0, or the DCI is DCI Format 0, the HARQ process identification comprises bits of a HARQ process identification field in the DCI, and further comprising: a first bit of an FDRA field in the DCI; or alternatively

7. The method of claim 1, wherein the second bit of the FDRA field comprises:

the lowest bit in the FDRA information carried by the FDRA field;

8. The method of claim 7, wherein a least significant bit in the FDRA information is a most significant bit of the feedback timing indication; or

9. The method of claim 1, wherein the second bit of the PUCCH resource indication field comprises:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field;

determining a feedback timing indication according to the bit of the feedback timing indication field and the most significant bit of the PUCCH resource indication field; or alternatively

10. The method of claim 9, wherein a most significant bit of the PUCCH resource indication field is a most significant bit of the feedback timing indication; or

11. The method of claim 1, 7, 8, 9, or 10, wherein in the case that the DCI is DCI format 0_0 or the DCI is DCI format 0_1, the feedback timing indication comprises bits of a feedback timing indication field in the DCI, and further comprising: a second bit of an FDRA field in the DCI; or

In a case that the DCI is DCI format 1_0 or the DCI is DCI format 1_1, the feedback timing indication includes a bit of a feedback timing indication field in the DCI, and further includes: a second bit of an FDRA field in the DCI; or

12. The method of claim 1,2, 3, 4, 5,7, 8, 9 or 10, wherein the determining a feedback timing indication according to HARQ process identification and bits of the feedback timing indication field comprises:

13. The method of claim 12, wherein a number of HARQ process identifiers included within the first range of identifiers is equal to a number of HARQ process identifiers included within the second range of identifiers;

14. A method for sending Downlink Control Information (DCI), comprising:

15. A terminal, comprising: a memory, a transceiver, and a processor, wherein:

16. The terminal of claim 15, wherein the first bit of the FDRA field comprises:

the least significant bit in the FDRA information carried by the FDRA field;

17. The terminal of claim 15, wherein the first bit of the PUCCH resource indication field comprises:

the most significant bit of the PUCCH resource indication field; or

The least significant bit of the PUCCH resource indication field;

18. The terminal of claim 15, wherein the second bit of the FDRA field comprises:

the least significant bit in the FDRA information carried by the FDRA field;

19. The terminal of claim 15, wherein the second bit of the PUCCH resource indication field comprises:

The least significant bit of the PUCCH resource indication field;

20. The terminal of claim 15, wherein the determining a feedback timing indication according to the HARQ process identity and the bits of the feedback timing indication field comprises:

21. A network device, comprising: a memory, a transceiver, and a processor, wherein:

a memory for storing a computer program; a transceiver for transceiving data under the control of the processor; a processor for reading the computer program in the memory and performing the following:

sending downlink control information DCI, wherein the DCI comprises at least one of a hybrid automatic repeat request (HARQ) process identification field and a feedback timing indication field, and further comprises: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field;

22. A terminal, comprising:

a determining unit, configured to determine target content, where the target content includes at least one of:

determining an HARQ process identifier according to the bit of the HARQ process identifier field and the first bit;

23. A network device, comprising:

a sending unit, configured to send downlink control information DCI, where the DCI includes at least one of a hybrid automatic repeat request HARQ process identifier field and a feedback timing indication field, and further includes: at least one of a Frequency Domain Resource Allocation (FDRA) field and a Physical Uplink Control Channel (PUCCH) resource indication field;

24. A processor-readable storage medium, characterized in that the processor-readable storage medium stores a computer program for causing the processor to execute the DCI receiving method of any one of claims 1 to 13 or the DCI transmitting method of claim 14.