CN115174016B

CN115174016B - Information transmission method, device, equipment and storage medium

Info

Publication number: CN115174016B
Application number: CN202110363800.XA
Authority: CN
Inventors: 司倩倩; 高雪娟
Original assignee: Datang Mobile Communications Equipment Co Ltd
Current assignee: Datang Mobile Communications Equipment Co Ltd
Priority date: 2021-04-02
Filing date: 2021-04-02
Publication date: 2023-12-26
Anticipated expiration: 2041-04-02
Also published as: CN115174016A; WO2022206457A1

Abstract

The embodiment of the application discloses an information transmission method, an information transmission device, information transmission equipment and a storage medium. The method comprises the following steps: determining a first code rate offset value when first uplink control information UCI of a first physical uplink control channel PUCCH is multiplexed to a physical uplink shared channel PUSCH and a second code rate offset value when second UCI of a second PUCCH is multiplexed to the PUSCH based on first code rate offset configuration information and second code rate offset configuration information, wherein the first code rate offset configuration information is code rate offset configuration information corresponding to the first UCI, the second code rate offset configuration information is code rate offset configuration information corresponding to the second UCI, priorities of the first PUCCH and the second PUCCH are different, and priorities of the PUSCH are the same as priorities of the second PUCCH; and multiplexing the first UCI and the second UCI to the PUSCH for transmission based on the first code rate offset value and the second code rate offset value. By adopting the embodiment of the application, the code rate offset value corresponding to the UCI of each PUCCH can be determined when the PUCCH and the PUSCH with different priorities are multiplexed, and the accuracy of information transmission is improved.

Description

Information transmission method, device, equipment and storage medium

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to an information transmission method, apparatus, device, and storage medium.

Background

At present, a communication system supports multiplexing transmission of uplink channels with different priorities, and for multiplexing between physical uplink control channels (Physical Uplink Control Channel, PUCCH) and physical uplink shared channels (Physical Uplink Shared Channel, PUSCH) with different priorities, an independent code rate offset (beta-offset) configuration is supported, but how to determine beta-offset values used by PUCCHs with different priorities in multiplexing based on PUSCH scheduling information has no clear scheme.

For example, when the communication system supports multiplexing transmission of uplink control information (Uplink Control Information, UCI) of a low-priority PUCCH on a high-priority PUSCH, since the transmission reliability requirement of UCI of the low-priority PUCCH is lower than that of the high-priority PUSCH, the network side may configure different values for the code rate offset value between UCI of the low-priority PUCCH and the high-priority PUSCH and the code rate offset value between UCI of the high-priority PUCCH and the high-priority PUSCH. However, based on the existing multiplexing method, only the code rate offset value when UCI of a PUCCH with a high priority is multiplexed on a PUSCH with a high priority can be determined based on the PUSCH scheduling information, and the code rate offset value when UCI of a PUCCH with a low priority is multiplexed on a PUSCH with a high priority cannot be determined.

Disclosure of Invention

The embodiment of the application provides an information transmission method, an information transmission device, information transmission equipment and a storage medium, which can determine code rate offset values corresponding to UCI of each PUCCH when PUCCH and PUSCH with different priorities are multiplexed, and improve information transmission accuracy.

In a first aspect, an embodiment of the present application provides an information transmission method, applied to a terminal device, where the method includes:

determining a first code rate offset value when first uplink control information UCI of a first physical uplink control channel PUCCH is multiplexed to a physical uplink shared channel PUSCH and a second code rate offset value when second UCI of a second PUCCH is multiplexed to the PUSCH based on first code rate offset configuration information and second code rate offset configuration information, wherein the first code rate offset configuration information is code rate offset configuration information corresponding to the first UCI, the second code rate offset configuration information is code rate offset configuration information corresponding to the second UCI, priorities of the first PUCCH and the second PUCCH are different, and priorities of the PUSCH are the same as priorities of the second PUCCH;

and multiplexing the first UCI and the second UCI to the PUSCH for transmission based on the first code rate offset value and the second code rate offset value.

In a second aspect, an embodiment of the present application provides an information transmission method, applied to a network device, where the method includes:

determining a first code rate offset value when a first UCI of a first PUCCH is multiplexed to a PUSCH and a second code rate offset value when a second UCI of a second PUCCH is multiplexed to the PUSCH based on first code rate offset configuration information and second code rate offset configuration information, wherein the first code rate offset configuration information is code rate offset configuration information corresponding to the first UCI, the second code rate offset configuration information is code rate offset configuration information corresponding to the second UCI, priorities of the first PUCCH and the second PUCCH are different, and priorities of the PUSCH are the same as priorities of the second PUCCH;

and receiving the first UCI and the second UCI multiplexed and transmitted on the PUSCH based on the first code rate offset value and the second code rate offset value.

In a third aspect, embodiments of the present application provide a terminal device, including a memory, a transceiver, and a processor:

a memory for storing a computer program; a transceiver for receiving and transmitting data under the control of the processor; a processor for reading the computer program in the memory and performing the method provided in the first aspect.

In a fourth aspect, embodiments of the present application provide a network device, including a memory, a transceiver, and a processor:

a memory for storing a computer program; a transceiver for receiving and transmitting data under the control of the processor; a processor for reading the computer program in the memory and executing the method provided in the second aspect

In a fifth aspect, an embodiment of the present application provides an information transmission apparatus, including:

a first determining unit, configured to determine, based on first code rate offset configuration information and second code rate offset configuration information, a first code rate offset value when first uplink control information UCI of a first physical uplink control channel PUCCH is multiplexed to a physical uplink shared channel PUSCH, and a second code rate offset value when second UCI of a second PUCCH is multiplexed to the PUSCH, where the first code rate offset configuration information is code rate offset configuration information corresponding to the first UCI, the second code rate offset configuration information is code rate offset configuration information corresponding to the second UCI, priorities of the first PUCCH and the second PUCCH are different, and priorities of the PUSCH are the same as priorities of the second PUCCH;

And a transmitting unit, configured to multiplex the first UCI and the second UCI to the PUSCH for transmission based on the first code rate offset value and the second code rate offset value.

In a sixth aspect, an embodiment of the present application provides an information transmission apparatus, including:

a second determining unit, configured to determine, based on first code rate offset configuration information and second code rate offset configuration information, a first code rate offset value when a first UCI of a first PUCCH is multiplexed to a PUSCH and a second code rate offset value when a second UCI of a second PUCCH is multiplexed to the PUSCH, where the first code rate offset configuration information is code rate offset configuration information corresponding to the first UCI, the second code rate offset configuration information is code rate offset configuration information corresponding to the second UCI, priorities of the first PUCCH and the second PUCCH are different, and priorities of the PUSCH are the same as priorities of the second PUCCH;

and a receiving unit, configured to receive the first UCI and the second UCI multiplexed and transmitted on the PUSCH based on the first code rate offset value and the second code rate offset value.

In a seventh aspect, embodiments of the present application provide a processor-readable storage medium storing a computer program for causing the processor to perform the method provided in the first and/or second aspects.

In the embodiment of the application, based on the code rate offset configuration information corresponding to the UCI of the PUUCH with different priorities, the code rate offset value corresponding to the UCI of each PUCCH is determined when the PUCCH and PUSCH with different priorities are multiplexed, so that the resources occupied by the UCI of the PUCCH with different priorities on the PUSCH are determined, and the accuracy of information transmission is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow chart of an information transmission method according to an embodiment of the present application;

fig. 2 is another flow chart of the information transmission method provided in the embodiment of the present application;

fig. 3 is a schematic structural diagram of a terminal device provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of a network device according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of an information transmission device according to an embodiment of the present disclosure;

Fig. 6 is another schematic structural diagram of an information transmission device according to an embodiment of the present application;

Detailed Description

In the embodiment of the application, the term "and/or" describes the association relationship of the association objects, which means that three relationships may exist, for example, a and/or B may be represented: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The term "plurality" in the embodiments of the present application means two or more, and other adjectives are similar thereto.

The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The method and the device are based on the same application, and because the principles of solving the problems by the method and the device are similar, the implementation of the device and the method can be referred to each other, and the repetition is not repeated.

The technical scheme provided by the embodiment of the application can be suitable for various systems, in particular to a 5G system. For example, suitable systems may be global system for mobile communications (global system of mobile communication, GSM), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (Wideband Code Division Multiple Access, WCDMA) universal packet Radio service (general packet Radio service, GPRS), long term evolution (long term evolution, LTE), LTE frequency division duplex (frequency division duplex, FDD), LTE time division duplex (time division duplex, TDD), long term evolution-advanced (long term evolution advanced, LTE-a), universal mobile system (universal mobile telecommunication system, UMTS), worldwide interoperability for microwave access (worldwide interoperability for microwave access, wiMAX), 5G New air interface (New Radio, NR), and the like. Terminal devices and network devices are included in these various systems. Core network parts such as evolved packet system (Evolved Packet System, EPS), 5G system (5 GS) etc. may also be included in the system.

The terminal device according to the embodiments of the present application may be a device that provides voice and/or data connectivity to a user, a handheld device with a wireless connection function, or other processing device connected to a wireless modem, etc. The names of the terminal devices may also be different in different systems, for example in a 5G system, the terminal devices may be referred to as User Equipment (UE). The wireless terminal device may communicate with one or more Core Networks (CNs) via a radio access Network (Radio Access Network, RAN), which may be mobile terminal devices such as mobile phones (or "cellular" phones) and computers with mobile terminal devices, e.g., portable, pocket, hand-held, computer-built-in or vehicle-mounted mobile devices that exchange voice and/or data with the radio access Network. Such as personal communication services (Personal Communication Service, PCS) phones, cordless phones, session initiation protocol (Session Initiated Protocol, SIP) phones, wireless local loop (Wireless Local Loop, WLL) stations, personal digital assistants (Personal Digital Assistant, PDAs), and the like. The wireless terminal device may also be referred to as a system, subscriber unit (subscriber unit), subscriber station (subscriber station), mobile station (mobile), remote station (remote station), access point (access point), remote terminal device (remote terminal), access terminal device (access terminal), user terminal device (user terminal), user agent (user agent), user equipment (user device), and the embodiments of the present application are not limited.

The network device according to the embodiment of the present application may be a base station, where the base station may include a plurality of cells for providing services for terminal devices. A base station may also be called an access point or may be a device in an access network that communicates over the air-interface, through one or more sectors, with wireless terminal devices, or other names, depending on the particular application. The network device may be operable to exchange received air frames with internet protocol (Internet Protocol, IP) packets as a router between the wireless terminal device and the rest of the access network, which may include an Internet Protocol (IP) communication network. The network device may also coordinate attribute management for the air interface. For example, the network device according to the embodiments of the present application may be a network device (Base Transceiver Station, BTS) in GSM or CDMA, a network device (NodeB) in WCDMA, an evolved network device (evolutional Node B, eNB or e-NodeB) in LTE system, a 5G base station (gNB) in a 5G network architecture (next generation system), a home evolved base station (Home evolved Node B, heNB), a relay node (relay node), a home base station (femto), a pico base station (pico), and the like. In some network structures, the network device may include a Centralized Unit (CU) node and a Distributed Unit (DU) node, which may also be geographically separated.

Multiple-input Multiple-output (Multi Input Multi Output, MIMO) transmissions may each be made between a network device and a terminal device using one or more antennas, and the MIMO transmissions may be Single User MIMO (SU-MIMO) or Multiple User MIMO (MU-MIMO). The MIMO transmission may be 2D-MIMO, 3D-MIMO, FD-MIMO, or massive-MIMO, or may be diversity transmission, precoding transmission, beamforming transmission, or the like, depending on the form and number of the root antenna combinations.

Referring to fig. 1, fig. 1 is a flow chart of an information transmission method according to an embodiment of the present application. As shown in fig. 1, the information transmission method provided in the embodiment of the present application may be used in a terminal device, and specifically may include the following steps:

step S11, determining a first code rate offset value when the first UCI of the first PUCCH is multiplexed to the PUSCH and a second code rate offset value when the second UCI of the second PUCCH is multiplexed to the PUSCH based on the first code rate offset configuration information and the second code rate offset configuration information.

Specifically, the priorities of the first PUCCH and the second PUCCH are different, and the priority of the PUSCH is the same as the priority of the second PUCCH. The priorities of the first PUCCH and the second PUCCH may be specifically determined based on the actual application scenario requirement, which is not limited herein.

As an example, the priority of the first PUCCH is high, the priority of the second PUCCH is low, and the priority of the PUSCH is low.

As an example, the priority of the first PUCCH is a low priority, the priority of the second PUCCH is a high priority, and the priority of the PUSCH is a high priority.

Specifically, the first code rate offset configuration information is corresponding code rate offset configuration information when a first UCI of a first PUCCH is multiplexed to a PUSCH, and the second code rate offset configuration information is corresponding code rate offset configuration information when a second UCI of a second PUCCH is multiplexed to a PUSCH.

Wherein, the UCI includes channel state information (Channel State Information, CSI) and hybrid automatic repeat request acknowledgement (HARQ-ACK).

Wherein, the CSI comprises CSI-Part 1 and CSI-Part 2.

Alternatively, the first code rate offset configuration information and the second code rate offset configuration information may be configured by higher layer signaling.

The code rate offset configuration information corresponding to the UCI of each PUCCH includes one or more groups of code rate offset values, each group includes a plurality of code rate offset values, and the plurality of code rate offset values in each group correspond to different UCI types or bit numbers.

As an example, UCI of the first PUCCH is HARQ-ACK, and when multiplexed to PUSCH, it uses a code rate offset value corresponding to HARQ-ACK in a certain group to transmit HARQ-ACK through PUSCH.

As an example, the number of bits of UCI of the first PUCCH is 20 bits, and when multiplexed to PUSCH, it uses a code rate offset value corresponding to 20 bits in a certain group to transmit UCI through PUSCH.

Specifically, when the first UCI of the first PUCCH and the second UCI of the second PUCCH are multiplexed to the PUSCH, the first code rate offset value when the first UCI of the first PUCCH is multiplexed to the PUSCH and the second code rate offset value when the second UCI of the second PUCCH is multiplexed to the PUSCH may be determined based on the first code rate offset configuration information and the second code rate offset configuration information. The first code rate offset value is a code rate offset (beta-offset) value used when the first UCI is multiplexed to the PUSCH, and the second code rate offset value is a code rate offset (beta-offset) value used when the second UCI is multiplexed to the PUSCH.

For any UCI of the first UCI and the second UCI, a Resource Element (RE) occupied by the UCI transmitted on the PUSCH is controlled by a corresponding code rate offset (beta-offset) value, where the code rate offset value indicates a code rate offset of the UCI and data transmission. For REs occupied by UCI mapping on a PUSCH, when the data transmission of the UL-SCH exists in the PUSCH, determining the UCI code rate according to the data transmission code rate and a code rate offset (beta-offset) value, and further determining the number of REs occupied by the UCI according to the UCI code rate.

When the UL-SCH data transmission does not exist in the PUSCH, the number of REs occupied by the HARQ-ACK and the CSI Part 1 is respectively determined according to the data transmission code rate and the code rate offset value indicated by the downlink control information (DownlinkControlInformation, DCI) of the PUSCH, and the rest REs in the RE resources available for UCI transmission on the PUSCH are used for the CSI Part 2 transmission.

In some possible embodiments, determining, based on the first code rate offset configuration information and the second code rate offset configuration information, a first code rate offset value when a first UCI of a first PUCCH is multiplexed to PUSCH and a second code rate offset value when a second UCI of a second PUCCH is multiplexed to PUSCH includes:

determining the bit number of code rate offset indication information in DCI of the PUSCH based on the first code rate offset configuration information and/or the second code rate offset configuration information, wherein the bit in the code rate offset indication information is used for indicating the first code rate offset configuration information and/or the second code rate offset configuration information;

and determining a first code rate offset value when the first UCI of the first PUCCH is multiplexed to the PUSCH and a second code rate offset value when the second UCI of the second PUCCH is multiplexed to the PUSCH based on code rate offset configuration information indicated by bits in the code rate offset indication information.

Wherein, the code rate offset indication information of the DCI of the PUSCH includes a certain number of bits, and at least one of the first code rate offset configuration information or the second code rate offset configuration information may be indicated by the certain number of bits. For example, 2 or 4 sets of code rate offset values corresponding to the first code rate offset configuration information are indicated by 1 bit or 2 bits.

In other words, the number of bits of the code rate offset indication information to be included in the DCI of the PUSCH may be determined based on the first code rate offset configuration information and/or the second code rate offset configuration information, the first code rate offset configuration information and/or the second code rate offset configuration information being indicated by a certain number of bits.

In some possible implementations, the code rate offset indication information may be determined based on at least one of the first code rate offset configuration information or the second code rate offset configuration information.

Specifically, based on the first code rate offset configuration information and the second code rate offset configuration information, the bit number of the code rate offset indication information in the DCI of the PUSCH may be determined.

Wherein the code rate offset indication information bit number in the DCI of the PUSCH is determined based on a first set of code rate offset values included in the first code rate offset configuration information and a second set of code rate offset values included in the second code rate offset configuration information.

Wherein if the first group number of the code rate offset values included in the first code rate offset configuration information is a, the second group number of the code rate offset values included in the second code rate offset configuration information is B, and a and B are positive integers, the code rate offset indication information in the DCI of the PUSCH includes log ₂ (max (A, B)) this feature.

If A is greater than or equal to B, log ₂ Front log in (max (A, B)) bits ₂ (B) Or last log ₂ (B) Bits are used to indicate second code rate offset configuration information, log ₂ The (max (a, B)) bit is used to indicate the first code rate offset configuration information; log if A is less than B ₂ Front log in (max (A, B)) bits ₂ (A) Or last log ₂ (A) Bits are used to indicate first code rate offset configuration information, log ₂ The (max (a, B)) bit is used to indicate the second code rate offset configuration information.

Or if the first group number of the code rate offset values included in the first code rate offset configuration information is a, the second group number of the code rate offset values included in the second code rate offset configuration information is B, and a and B are positive integers, the code rate offset indication information in the DCI of the PUSCH includes log ₂ (A)+log ₂ (B) Bits. log of ₂ (A)+log ₂ (B) Log in this specification ₂ (A) Bits are used to indicate first code rate offset configuration information, log ₂ (B) The bit is used to indicate the second code rate offset configuration information.

As an example, the priority of the first PUCCH is low, the priority of the second PUCCH is low, and the priority of the PUSCH is high.

If 4 sets of values are included in the code rate offset configuration information (beta-offset configuration) transmitted on the PUSCH of the low priority PUCCH, the code rate offset configuration information beta-offset configuration transmitted on the PUSCH of the high priority PUCCH, the code rate offset indication information is included in the DCI corresponding to the PUSCH of the high priority, wherein 2 bits are used for indicating the code rate offset configuration information transmitted on the PUSCH of the high priority PUCCH for the UCI multiplexing of the low priority PUCCH, and the code rate offset configuration information transmitted on the PUSCH of the high priority for the UCI multiplexing of the high priority PUCCH for the other 2 bits.

If the UCI multiplexing of the PUCCH of low priority contains 1 set of values in the code rate offset configuration information (beta-offset configuration) transmitted on the PUSCH of high priority and the UCI multiplexing of the PUCCH of high priority contains 4 sets of values in the code rate offset configuration information beta-offset configuration transmitted on the PUSCH of high priority, it is determined that the DCI corresponding to the PUSCH of high priority contains 2-bit code rate offset indication information for indicating the code rate offset configuration information transmitted on the PUSCH of high priority.

If 4 sets of values are included in the code rate offset configuration information (beta-offset configuration) transmitted on the high-priority PUSCH by UCI multiplexing of the low-priority PUCCH, and 4 sets of values are included in the code rate offset configuration information beta-offset configuration transmitted on the high-priority PUSCH by UCI multiplexing of the high-priority PUCCH, it is determined that 2-bit code rate offset indication information is included in DCI corresponding to the high-priority PUSCH while code rate offset configuration information transmitted on the high-priority PUSCH is multiplexed by UCI for indicating the high-priority PUSCH and code rate offset configuration information transmitted on the high-priority PUSCH by UCI multiplexing of the low-priority UCI.

If the UCI multiplexing of the PUCCH of low priority contains 2 sets of values in the code rate offset configuration information (beta-offset configuration) transmitted on the PUSCH of high priority and the UCI multiplexing of the PUCCH of high priority contains 4 sets of values in the code rate offset configuration information beta-offset configuration transmitted on the PUSCH of high priority, it is determined that the DCI corresponding to the PUSCH of high priority contains 2 bits of this code rate offset indication information, the 2 bits of which are used to indicate the code rate offset configuration information transmitted on the PUSCH of high priority and the 1 st bit of which is also used to indicate the code rate offset configuration information transmitted on the PUSCH of low priority.

Alternatively, the number of bits of the code rate offset indication information in the DCI of the PUSCH may be determined based on the second code rate offset configuration information.

Wherein the bit number of the code rate offset indication information in the DCI of the PUSCH is determined based on the second set of code rate offset values included in the second code rate offset configuration information.

If the number of groups of code rate offset values included in the second code rate offset configuration information is B, and B is a positive integer, the code rate offset indication information in the DCI of the PUSCH includes log ₂ (B) Bits, log ₂ (B) This is used to indicate the second code rate offset configuration information.

As an example, the priority of the first PUCCH is low, the priority of the second PUCCH is low, and the priority of the PUSCH is high. If the UCI multiplexing of the PUCCH of low priority contains 1 set of values in the code rate offset configuration information beta-offset configuration transmitted on the PUSCH of high priority and the UCI multiplexing of the PUCCH of high priority contains 4 sets of values in the code rate offset configuration information (beta-offset configuration) transmitted on the PUSCH of high priority, it is determined that the DCI corresponding to the PUSCH of high priority contains 2-bit code rate offset indication information for indicating the code rate offset configuration information transmitted on the PUSCH of high priority.

In some possible embodiments, when determining the first code rate offset value when the first UCI of the first PUCCH is multiplexed to the PUSCH based on the code rate offset configuration information indicated by the bits in the code rate offset indication information in the DCI of the PUSCH and the second code rate offset value when the second UCI of the second PUCCH is multiplexed to the PUSCH, the first code rate offset value when the first UCI of the first PUCCH is multiplexed to the PUSCH may be determined based on the code rate offset configuration information indicated by the bits in the code rate offset indication information and the first code rate offset configuration information, and the second code rate offset value when the second UCI of the second PUCCH is multiplexed to the PUSCH may be determined based on the code rate offset indication information and the second code rate offset configuration information.

Specifically, for the first code rate offset value, if the first code rate offset configuration information includes a set of code rate offset values, determining a code rate offset value for the first UCI of the first PUCCH from the set of code rate offset values based on the type of the first UCI of the first PUCCH and the number of bits, and determining the code rate offset value as the first code rate offset value when the first UCI is multiplexed to the PUSCH.

As an example, the priority of the first PUCCH is a first priority, the priority of the second PUCCH is a second priority, and the priority of the PUSCH is a second priority. If UCI corresponding to the PUCCH of the first priority is multiplexed on the PUSCH of the second priority only including a set of values, whether or not there are bits in the code rate offset indication information in the DCI of the PUSCH of the second priority indicating the first code rate offset configuration information of the PUCCH of the first priority, a first code rate offset (beta-offset) value used by UCI corresponding to the PUCCH of the first priority on the PUSCH of the second priority is multiplexed in the set of values may be determined based on the type and the number of bits of UCI carried by the PUCCH of the first priority.

Optionally, if the first code rate offset configuration information includes multiple groups of code rate offset values, a group of code rate offset values among the multiple groups of code rate offset values included in the first code rate offset configuration information may be determined based on the related indication of the DCI of the PUSCH, and the first code rate offset value may be determined from the group of code rate offset values based on the type and the number of bits of the first UCI of the first PUCCH, where bits of the code rate offset indication information are used to indicate the first code rate offset configuration information, that is, at least one bit exists in the code rate offset information to indicate the first code rate offset configuration information.

As an example, the priority of the first PUCCH is a first priority, the priority of the second PUCCH is a second priority, and the priority of the PUSCH is a second priority. If there is at least one bit in the DCI corresponding to the PUSCH of the second priority to indicate the first code rate offset configuration information corresponding to when UCI of the first priority PUCCH is multiplexed on the PUSCH of the second priority, and UCI of the PUCCH of the first priority contains multiple sets of values in the first code rate offset configuration information corresponding to the PUSCH of the second priority, it is determined to use one of the sets of values based on the related indication of the DCI of the PDSCH. Further based on the type and number of bits of UCI carried by the PUCCH of the first priority, a first code rate offset (beta-offset) value used by UCI multiplexing of the PUCCH of the first priority on the PUSCH of the second priority is determined in the set of values.

Optionally, if the first code rate offset configuration information includes multiple groups of code rate offset values, determining, based on the pre-configuration information or the higher layer configuration information, a group of code rate offset values among the multiple groups of code rate offset values included in the first code rate offset configuration information, and determining, based on a type and a number of bits of the first UCI of the first PUCCH, the first code rate offset value from the group of code rate offset values, wherein the code rate offset indication information is not used for indicating the first code rate offset configuration information, that is, there are no bits in the code rate offset information for indicating the first code rate offset configuration information.

As an example, the priority of the first PUCCH is a first priority, the priority of the second PUCCH is a second priority, and the priority of the PUSCH is a second priority. If there is no bit in the DCI corresponding to the second priority PUSCH to indicate that UCI of the first priority PUCCH is multiplexed in the first code rate offset configuration information corresponding to the second priority PUSCH and UCI of the first priority PUCCH contains multiple sets of values in the first code rate offset configuration information corresponding to the second priority PUSCH, determining to use one of the sets of values based on the pre-configuration information or the higher layer configuration information, and determining a first code rate offset (beta-offset) value used by UCI of the first priority PUCCH on the second priority PUSCH based on the type of UCI carried by the first priority PUCCH and the number of bits in the set of values.

The pre-configuration information is used for indicating to select a first group of code rate offset values from a plurality of groups of code rate offset values or indicating to select a last group of code rate offset values from a plurality of groups of code rate offset values.

Specifically, for the second code rate offset value, the second code rate offset value when the second UCI of the second PUCCH is multiplexed to PUSCH may be determined based on the code rate offset indication information and the second code rate offset configuration information.

As an example, the priority of the first PUCCH is a first priority, the priority of the second PUCCH is a second priority, and the priority of the PUSCH is a second priority. A set of code rate offset values may be determined from second code rate offset configuration information corresponding to UCI multiplexing of the second priority PUCCH on the second priority PUSCH based on the code rate offset indication information, and a second code rate offset (beta-offset) value used by UCI multiplexing of the second priority PUCCH on the second priority PUSCH may be determined from the set of values based further on the type and number of bits of UCI carried by the second priority PUCCH.

The determination of the first code rate offset value is described below by way of specific examples. The priority of the first PUCCH is low, the priority of the second PUCCH is low, and the priority of the PUSCH is high.

If the terminal device supports PUCCH and PUSCH multiplexing transmission of different priorities, the network device configures code rate offset configuration information (beta-offset configuration) for UCI of a high priority PUCCH multiplexed and transmitted on a high priority PUSCH and UCI of a low priority PUCCH multiplexed and transmitted on the high priority PUSCH, respectively, and determines a code rate offset (beta-offset) value used for UCI multiplexing of a low priority PUCCH multiplexed and transmitted on the high priority PUSCH based on the following manner:

if the UCI multiplexing of the low-priority PUCCH includes 1 set of values in the code rate offset configuration information (beta-offset configuration) transmitted on the high-priority PUSCH, the code rate offset (beta-offset) value used by the UCI multiplexing of the low-priority PUCCH on the high-priority PUSCH is determined among the set of values based on the type and the number of bits of the UCI of the low-priority PUCCH.

If 4 sets of values are included in code rate offset configuration information (beta-offset configuration) transmitted on the high-priority PUSCH for UCI multiplexing of the low-priority PUCCH, code rate offset indication information of 2 bits in DCI corresponding to the high-priority PUSCH may be used to indicate code rate offset configuration information transmitted on the high-priority PUSCH for UCI multiplexing of the low-priority PUCCH, 1 set of values of 4 sets is determined based on the 2 bits indicated by the DCI, and a code rate offset (beta-offset) value used for UCI multiplexing of the low-priority PUCCH on the high-priority PUSCH is determined in the sets of values based on the type and number of bits of UCI of the low-priority PUCCH.

If the UCI multiplexing of the PUCCH of low priority contains 2 sets of values in the code rate offset configuration information (beta-offset configuration) transmitted on the PUSCH of high priority, the code rate offset indication information of 2 bits is contained in the DCI corresponding to the PUSCH of high priority, wherein the first bit may be used to indicate the code rate offset configuration information that the UCI multiplexing of the PUCCH of low priority transmits on the PUSCH of high priority, 1 set of values of 2 sets is determined based on the 1 bit indicated by the DCI, and the code rate offset (beta-offset) value used by the UCI multiplexing of the PUCCH of low priority on the PUSCH of high priority is determined in this set of values based on the type and number of bits of the UCI of the PUCCH of low priority.

If 4 sets of values are included in the code rate offset configuration information (beta-offset configuration) transmitted on the high-priority PUSCH for UCI multiplexing of the low-priority PUCCH, 2 bits of code rate offset indication information are included in the DCI corresponding to the high-priority PUSCH, but no bit therein may be used to indicate that the code rate offset configuration information transmitted on the high-priority PUSCH is multiplexed by UCI of the low-priority PUCCH, or no code rate offset indication information is included in the DCI corresponding to the high-priority PUSCH, 1 set of values is determined, such as a first set of values is fixedly selected, based on the pre-configuration information or the high-layer configuration information, and the code rate offset (beta-offset) value used by the UCI multiplexing of the low-priority PUCCH on the high-priority PUSCH is determined in the set of values based on the type and the number of bits of UCI of the low-priority PUCCH.

In some possible embodiments, when determining the first code rate offset value when the first UCI of the first PUCCH is multiplexed to the PUSCH based on the code rate offset configuration information indicated by the bits in the code rate offset indication information in the DCI of the PUSCH and the second code rate offset value when the second UCI of the second PUCCH is multiplexed to the PUSCH, the second code rate offset value when the second UCI of the second PUCCH is multiplexed to the PUSCH may be determined based on the code rate offset configuration information indicated by the bits in the code rate offset indication information and the second code rate offset configuration information based on the first code rate offset configuration information or the first offset value.

The first offset value is an offset value between code rate offset values when UCI of PUCCHs of different priorities is multiplexed to the same PUSCH, that is, an offset value between a first code rate offset value used when the first UCI of the first PUCCH is multiplexed to the PUSCH and a second code rate offset value used when the second UCI of the second PUCCH is multiplexed to the PUSCH.

The offset value is predefined based on a protocol or determined based on a higher layer signaling configuration, and may specifically be determined based on actual application scene requirements, which is not limited herein.

Specifically, for the second code rate offset value, if the second code rate offset configuration information includes a set of code rate offset values, the second code rate offset value is determined from the set of code rate offset values based on the type and the number of bits of the first UCI.

As an example, the priority of the first PUCCH is a first priority, the priority of the second PUCCH is a second priority, and the priority of the PUSCH is a second priority. If UCI corresponding to the PUCCH of the second priority is multiplexed on the PUSCH of the second priority only including a set of values, whether there are bits in the code rate offset indication information in the DCI of the PUSCH of the second priority indicates the second code rate offset configuration information of the PUCCH of the second priority, a second code rate offset (beta-offset) value used by UCI corresponding to the PUCCH of the second priority is multiplexed on the PUSCH of the second priority may be determined among the set of values based on the type and the number of bits of UCI carried by the PUCCH of the first priority.

Optionally, if the second code rate offset configuration information includes multiple groups of code rate offset values, determining, based on DCI, a group of code rate offset values among the multiple groups of code rate offset values included in the second code rate offset configuration information, and determining, based on a type and a number of bits of a first UCI of the first PUCCH, a second code rate offset value when the second UCI is multiplexed to PUSCH from the group of code rate offset values, where the code rate offset indication information is used to indicate the second code rate offset configuration information, that is, at least one bit exists in the code rate offset indication information to indicate the second code rate offset configuration information.

As an example, the priority of the first PUCCH is a first priority, the priority of the second PUCCH is a second priority, and the priority of the PUSCH is a second priority. If there is at least one bit in the DCI corresponding to the PUSCH of the second priority to indicate the second code rate offset configuration information corresponding to when UCI of the PUCCH of the second priority is multiplexed in the PUSCH of the second priority, and UCI of the PUCCH of the second priority is multiplexed in the second code rate offset configuration information corresponding to the PUSCH of the second priority to include a plurality of sets of values, it is determined to use one of the sets of values based on the related indication of the DCI of the PDSCH. Further based on the type and number of bits of UCI carried by the PUCCH of the first priority, a second code rate offset (beta-offset) value used by UCI multiplexing of the PUCCH of the second priority on PUSCH of the second priority is determined in the set of values.

Optionally, if the second code rate offset configuration information includes multiple sets of code rate offset values, determining, based on the pre-configuration information or the higher layer configuration information, one set of code rate offset values of the multiple sets of code rate offset values included in the second code rate offset configuration information, and determining, based on the type and the number of bits of the first UCI, the second code rate offset value from the set of code rate offset values, where the code rate offset indication information is not used to indicate the second code rate offset configuration information, i.e., no bits in the code rate offset indication information are used to indicate the second code rate offset configuration information.

As an example, the priority of the first PUCCH is a first priority, the priority of the second PUCCH is a second priority, and the priority of the PUSCH is a second priority. If there is no bit in the DCI corresponding to the second priority PUSCH to indicate the second code rate offset configuration information corresponding to the second priority PUSCH, and the UCI multiplexing of the second priority PUCCH includes a plurality of sets of values in the second code rate offset configuration information corresponding to the second priority PUSCH, determining to use one of the sets of values based on the pre-configuration information or the higher layer configuration information, and determining a second code rate offset (beta-offset) value used by the UCI multiplexing of the second priority PUCCH on the second priority PUSCH in the set of values based on the type and the number of bits of UCI carried by the first priority PUCCH.

Specifically, for the first code rate offset value, the first code rate offset value may be determined from a set of code rate offset values in the first code rate offset configuration information. That is, if the first code rate offset configuration information includes a set of code rate offset values, the first code rate offset value when the first UCI of the first PUCCH is multiplexed to the PUSCH is determined from the set of code rate offset values. If the first code rate offset configuration information includes multiple groups of code rate offset values, determining a group of code rate offset values from the multiple groups of code rate offset values based on pre-configuration information or higher layer configuration information, and further determining a first code rate offset value when the first UCI of the first PUCCH is multiplexed to PUSCH from the group of code rate offset values.

As an example, the priority of the first PUCCH is a first priority, the priority of the second PUCCH is a second priority, and the priority of the PUSCH is a second priority. If the first code rate offset configuration information corresponding to the PUCCH of the first priority includes only one set of code rate offset values, determining a first code rate offset (beta-offset) value when UCI of the PUCCH of the first priority is multiplexed to PUSCH of the second priority from the set of code rate offset values.

And determining a fixed group of code rate offset values (such as a first group or a last group) from the plurality of groups of code rate offset values when the first code rate offset configuration information corresponding to the PUCCH of the first priority comprises the plurality of groups of code rate offset values, and further determining a first code rate offset (beta-offset) value when UCI of the PUCCH of the first priority is multiplexed to the PUSCH of the second priority from the group of code rate offset values.

Optionally, for the first code rate offset value, after determining the second code rate offset value when the second UCI of the second PUCCH is multiplexed to PUSCH, the first code rate offset value when the first UCI of the first PUCCH is multiplexed to PUSCH may be determined based on the second code rate offset value and the first offset value.

As an example, the priority of the first PUCCH is a first priority, the priority of the second PUCCH is a second priority, and the priority of the PUSCH is a second priority. After determining the second code rate offset value when UCI of the PUCCH of the second priority is multiplexed to the PUSCH of the second priority based on the code rate offset configuration information corresponding to the PUCCH of the second priority and the code rate offset instruction information of the DCI of the PUSCH, a first offset value between the second code rate offset value when UCI of the PUCCH of the second priority is multiplexed to the PUSCH of the second priority and the first code rate offset value when UCI of the PUCCH of the first priority is multiplexed to the PUSCH of the second priority may be determined, and further, the first code rate offset value when UCI of the PUCCH of the first priority is multiplexed to the PUSCH of the second priority may be determined based on the first offset value and the second code rate offset value.

The determination of the first code rate offset value and the second code rate offset value will be described by way of specific examples. The priority of the first PUCCH is low, the priority of the second PUCCH is low, and the priority of the PUSCH is high.

If the terminal device supports PUCCH and PUSCH multiplexing transmission of different priorities, the network device configures code rate offset configuration information (beta-offset configuration) for UCI of a high priority PUCCH multiplexed and UCI of a low priority PUCCH multiplexed on a high priority PUSCH, respectively, the code rate offset (beta-offset) value used when UCI of a low priority PUCCH and UCI of a high priority PUCCH are multiplexed may be determined based on the following manner:

if the UCI multiplexing of the high-priority PUCCH includes 1 set of values in the code rate offset configuration information (beta-offset configuration) transmitted on the high-priority PUSCH, a code rate offset (beta-offset) value used by the UCI multiplexing of the high-priority PUCCH on the high-priority PUSCH is determined in the set of values based on the type and the number of bits of the UCI of the low-priority PUCCH, and a code rate offset (beta-offset) value used by the UCI multiplexing of the low-priority PUCCH on the high-priority PUSCH is determined based on a first offset value between code rate offset (beta-offset) values of UCI multiplexing of different-priority PUCCHs on the same PUSCH.

If 4 sets of values are included in code rate offset configuration information (beta-offset configuration) transmitted on the high-priority PUSCH for UCI multiplexing of the high-priority PUCCH, and 2 bits of code rate offset indication information are included in DCI corresponding to the high-priority PUSCH, 1 set of the 4 sets of values is determined based on the 2 bits indicated by the DCI, and code rate offset (beta-offset) values used for UCI multiplexing of the high-priority PUCCH on the high-priority PUSCH are determined from among the sets of values based on the type and number of bits of UCI of the low-priority PUCCH, and then code rate offset (beta-offset) values used for UCI multiplexing of the low-priority PUCCH on the high-priority PUSCH are determined based on first offset values between beta-offset values for UCI multiplexing of different-priority PUCCHs on the same PUSCH.

If 4 sets of values are included in the code rate offset configuration information (beta-offset configuration) transmitted on the high-priority PUSCH by UCI multiplexing of the high-priority PUCCH, 2 bits of code rate offset indication information are included in the DCI corresponding to the high-priority PUSCH, but no bit therein may be used to indicate that the code rate offset configuration information transmitted on the high-priority PUSCH by UCI multiplexing of the low-priority PUCCH is not included in the DCI corresponding to the high-priority PUSCH, 1 set of values is determined, such as a first set of values is fixedly selected, based on the pre-configuration information or the high-layer configuration information, and the code rate offset (beta-offset) value used by the UCI multiplexing of the high-priority PUCCH on the high-priority PUSCH is determined in the set of values based on the type and the number of bits of UCI of the low-priority PUCCH.

And step S12, multiplexing the first UCI and the second UCI to the PUSCH for transmission based on the first code rate offset value and the second code rate offset value.

In some possible embodiments, after determining the first code rate offset value when the first UCI of the first PUCCH is multiplexed to PUSCH and the second code rate offset value when the second UCI of the second PUCCH is multiplexed to PUSCH, the terminal device may determine RE resources occupied by the first UCI on PUSCH based on the first code rate offset value, determine RE resources occupied by the second UCI on PUSCH based on the second code rate offset value, and further multiplex the first UCI and the second UCI to PUSCH based on the RE resources occupied by the first UCI and the second UCI, and transmit to the network device through PUSCH.

Referring to fig. 2, fig. 2 is another flow chart of the information transmission method provided in the embodiment of the present application. As shown in fig. 2, the information transmission method provided in the embodiment of the present application may be applicable to a network device, and specifically may include the following steps:

step S21, determining a first code rate offset value when the first UCI of the first PUCCH is multiplexed to the PUSCH and a second code rate offset value when the second UCI of the second PUCCH is multiplexed to the PUSCH based on the first code rate offset configuration information and the second code rate offset configuration information.

Wherein determining, based on the first code rate offset configuration information and the second code rate offset configuration information, a first code rate offset value when a first UCI of a first PUCCH is multiplexed to PUSCH and a second code rate offset value when a second UCI of a second PUCCH is multiplexed to PUSCH includes:

determining the bit number of code rate offset indication information in DCI of the PUSCH based on the first code rate offset configuration information and/or the second code rate offset configuration information, wherein the bit number of the code rate offset indication information is used for indicating the first code rate offset configuration information and/or the second code rate offset configuration information;

based on the code rate offset configuration information indicated by the bit in the code rate offset indication information, a first code rate offset value when a first UCI of a first PUCCH is multiplexed to PUSCH and a second code rate offset value when a second UCI of a second PUCCH is multiplexed to PUSCH are determined.

Wherein determining the bit number of the code rate offset indication information in the DCI of the PUSCH based on the first code rate offset configuration information and the second code rate offset configuration information includes:

the bit number of the code rate offset indication information in the DCI of the PUSCH is determined based on the first group number of the code rate offset values included in the first code rate offset configuration information and the second group number of the code rate offset values included in the second code rate offset configuration information.

If the first group number is A, the second group number is B, and A and B are positive integers; the code rate offset indication information includes log ₂ (max (A, B)) bits, log if A is greater than or equal to B ₂ Front log in (max (A, B)) bits ₂ (B) Or last log ₂ (B) Bits are used to indicate second code rate offset configuration information, log ₂ (max (A, B)) this is used to indicate the first code rate offset configuration information, log if A is less than B ₂ (max (A, B)) front log in this specification ₂ (A) Or last log ₂ (A) Bits are used to indicate first code rate offset configuration information, log ₂ The (max (a, B)) bit is used to indicate second code rate offset configuration information; or,

the code rate offset indication information includes log ₂ (A)+log ₂ (B) This feature, log ₂ (A)+log ₂ (B) Log in this specification ₂ (A) Bits are used to indicate first code rate offset configuration information, log ₂ (B) The bit is used to indicate the second code rate offset configuration information.

Wherein determining the bit number of the code rate offset indication information in the DCI of the PUSCH based on the second code rate offset configuration information includes:

the number of bits of the code rate offset indication information in the DCI of the PUSCH is determined based on a second set of code rate offset values included in the second code rate offset configuration information.

If the second group number is B, B is a positive integer;

the code rate offset indication information includes log ₂ (B) This feature, log ₂ (B) This is used to indicate the second code rate offset configuration information.

Wherein determining, based on code rate offset configuration information indicated by bits in the code rate offset indication information, a first code rate offset value when a first UCI of a first PUCCH is multiplexed to PUSCH and a second code rate offset value when a second UCI of a second PUCCH is multiplexed to PUSCH, comprises:

determining a first code rate offset value when a first UCI of a first PUCCH is multiplexed to a PUSCH based on code rate offset configuration information and first code rate offset configuration information indicated by bits in the code rate offset indication information, and determining a second code rate offset value when a second UCI of a second PUCCH is multiplexed to the PUSCH based on the code rate offset indication information and the second code rate offset configuration information; or,

determining a second code rate offset value based on code rate offset configuration information and second code rate offset configuration information indicated by bits in the code rate offset indication information, and determining a first code rate offset value based on the first code rate offset configuration information or the first offset value;

the first offset value is an offset value between the first code rate offset value and the second code rate offset value.

Wherein determining a first code rate offset value when the first UCI of the first PUCCH is multiplexed to PUSCH based on the code rate offset configuration information indicated by the bit in the code rate offset indication information and the first code rate offset configuration information includes:

If the first code rate offset configuration information comprises a group of code rate offset values, determining the first code rate offset value when the first UCI is multiplexed to the PUSCH from the group of code rate offset values based on the type and the bit number of the first UCI of the first PUCCH;

if the first code rate offset configuration information comprises a plurality of groups of code rate offset values, determining a group of code rate offset values in the plurality of groups of code rate offset values included in the first code rate offset configuration information based on DCI, and determining the first code rate offset value from the group of code rate offset values based on the type and the bit number of the first UCI, wherein the bits in the code rate offset indication information are used for indicating the first code rate offset configuration information;

if the first code rate offset configuration information includes multiple groups of code rate offset values, determining one group of code rate offset values in the multiple groups of code rate offset values included in the first code rate offset configuration information based on pre-configuration information or higher layer configuration information, and determining the first code rate offset value from the group of code rate offset values based on the type and the bit number of the first UCI, wherein the bits in the code rate offset indication information are not used for indicating the first code rate offset configuration information.

Wherein determining the second code rate offset value based on the code rate offset configuration information and the second code rate offset configuration information indicated by the bits in the code rate offset indication information comprises:

If the second code rate offset configuration information includes a set of code rate offset values, determining the second code rate offset value from the set of code rate offset values based on the type and the number of bits of the first UCI;

if the second code rate offset configuration information comprises a plurality of groups of code rate offset values, determining a group of code rate offset values in the plurality of groups of code rate offset values included in the second code rate offset configuration information based on DCI, and determining a second code rate offset value when the second UCI is multiplexed to the PUSCH from the group of code rate offset values based on the type and the bit number of the first UCI of the first PUCCH, wherein the bits in the code rate offset indication information are used for indicating the second code rate offset configuration information;

if the second code rate offset configuration information includes multiple groups of code rate offset values, determining one group of code rate offset values in the multiple groups of code rate offset values included in the second code rate offset configuration information based on pre-configuration information or higher layer configuration information, and determining the second code rate offset value from the group of code rate offset values based on the type and the bit number of the first UCI, wherein the bits in the code rate offset indication information are not used for indicating the second code rate offset configuration information.

Wherein determining the first code rate offset value based on the first code rate offset configuration information comprises:

A first code rate offset value is determined from a set of code rate offset values in the first code rate offset configuration information.

Wherein determining the first code rate offset value based on the first offset value comprises:

a first code rate offset value is determined based on the second code rate offset value and the first offset value.

The pre-configuration information is used for indicating that the first group of code rate offset values or the last group of code rate offset values are selected from a plurality of groups of code rate offset values.

In some possible embodiments, the specific implementation manner of determining, by the network device, the first code rate offset value when the first UCI of the first PUCCH is multiplexed to the PUSCH and the second code rate offset value when the second UCI of the second PUCCH is multiplexed to the PUSCH based on the first code rate offset configuration information and the second code rate offset configuration information may refer to the implementation manner shown in step S11 in fig. 1 on the terminal device side, which is not described herein again.

Step S22, based on the first code rate offset value and the second code rate offset value, the first UCI and the second UCI which are multiplexed and transmitted on the PUSCH are received.

In some possible embodiments, after determining the first code rate offset value when the first UCI of the first PUCCH is multiplexed to PUSCH and the second code rate offset value when the second UCI of the second PUCCH is multiplexed to PUSCH, the network device may determine RE resources occupied by the first UCI on the PUSCH based on the first code rate offset value, determine RE resources occupied by the second UCI on the PUSCH based on the second code rate offset value, and further receive the first UCI of the first PUCCH and the second UCI of the second PUCCH transmitted by the terminal device through the PUSCH based on the RE resources occupied by the first UCI and the second UCI.

In the embodiment of the application, when multiplexing between PUCCHs and PUSCHs of different priorities indicates independent code rate offset configuration information, code rate offset (beta-offset) values corresponding to UCI of each PUCCH can be determined when PUCCHs and PUSCHs of different priorities are multiplexed based on code rate offset configuration information corresponding to UCI of PUCCHs of different priorities, priorities of PUCCHs, DCI of PUSCH and the like, so that resources occupied by UCI of PUCCHs of different priorities on PUSCH are determined, and information transmission accuracy is improved.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a terminal device provided in an embodiment of the present application. The terminal device provided in the embodiment of the present application includes a user interface 1230, a memory 1220, a transceiver 1200, and a processor 1210.

Transceiver 1200 for receiving and transmitting data under the control of processor 1210, memory 1220 for storing computer programs, processor 1210 for reading the computer programs in memory 1220 to implement:

In some possible embodiments, the processor 1210 is configured to:

determining the bit number of code rate offset indication information in DCI of a PUSCH based on first code rate offset configuration information and/or second code rate offset configuration information, wherein the bit in the code rate offset indication information is used for indicating the first code rate offset configuration information and/or the second code rate offset configuration information;

In some possible embodiments, the processor 1210 is configured to:

and determining the bit number of the code rate offset indication information in the DCI of the PUSCH based on the first group number of the code rate offset values included in the first code rate offset configuration information and the second group number of the code rate offset values included in the second code rate offset configuration information.

In some possible embodiments, the first set of numbers is a, the second set of numbers is B, and a and B are positive integers;

the code rate offset indication information includes log ₂ (max (A, B)) bits, log if A is greater than or equal to B ₂ Front log in (max (A, B)) bits ₂ (B) Or last log ₂ (B) Bits are used to indicate the second rate offset configuration information, log ₂ The (max (A, B)) bit is used to indicate the first code rate offset configuration information, and if A is smaller than B, log ₂ Front log in (max (A, B)) bits ₂ (A) Or last log ₂ (A) Bits are used to indicate the first code rate offset configuration information, log ₂ A (max (a, B)) bit for indicating the second code rate offset configuration information; or,

the code rate offset indication information includes log ₂ (A)+log ₂ (B) Bits, log ₂ (A)+log ₂ (B) Log in bits ₂ (A) Bits are used to indicate the first code rate offset configuration information, log ₂ (B) Bits are used to indicate the second code rate offset configuration information.

In some possible embodiments, the processor 1210 is configured to:

and determining the bit number of the code rate offset indication information in the DCI of the PUSCH based on the second group number of the code rate offset values included in the second code rate offset configuration information.

In some possible embodiments, the second group number is B, and B is a positive integer;

The code rate offset indication information includes log ₂ (B) Bits, log ₂ (B) Bits are used to indicate the second code rate offset configuration information.

In some possible embodiments, the processor 1210 is configured to:

determining a first code rate offset value when a first UCI of a first PUCCH is multiplexed to a PUSCH based on code rate offset configuration information indicated by bits in the code rate offset indication information and the first code rate offset configuration information, and determining a second code rate offset value when a second UCI of a second PUCCH is multiplexed to the PUSCH based on the code rate offset indication information and the second code rate offset configuration information; or,

determining the second code rate offset value based on code rate offset configuration information indicated by bits in the code rate offset indication information and the second code rate offset configuration information, and determining the first code rate offset value based on the first code rate offset configuration information or the first offset value;

wherein the first offset value is an offset value between the first code rate offset value and the second code rate offset value.

In some possible embodiments, the processor 1210 is configured to:

if the first code rate offset configuration information includes a set of code rate offset values, determining a first code rate offset value when the first UCI is multiplexed to PUSCH from the set of code rate offset values based on a type and a bit number of the first UCI of the first PUCCH;

If the first code rate offset configuration information includes multiple groups of code rate offset values, determining a group of code rate offset values in the multiple groups of code rate offset values included in the first code rate offset configuration information based on the DCI, and determining the first code rate offset value from the group of code rate offset values based on the type and the number of bits of the first UCI, wherein the bits in the code rate offset indication information are used for indicating the first code rate offset configuration information;

if the first code rate offset configuration information includes multiple groups of code rate offset values, determining one group of code rate offset values from multiple groups of code rate offset values included in the first code rate offset configuration information based on pre-configuration information or higher layer configuration information, and determining the first code rate offset value from the group of code rate offset values based on the type and the bit number of the first UCI, wherein the bits in the code rate offset indication information are not used for indicating the first code rate offset configuration information.

In some possible embodiments, the processor 1210 is configured to:

If the second code rate offset configuration information includes multiple groups of code rate offset values, determining, based on the DCI, one group of code rate offset values among the multiple groups of code rate offset values included in the second code rate offset configuration information, and determining, based on a type and a number of bits of a first UCI of a first PUCCH, a second code rate offset value when the second UCI is multiplexed to the PUSCH from the group of code rate offset values, where bits in the code rate offset indication information are used to indicate the second code rate offset configuration information;

if the second code rate offset configuration information includes multiple groups of code rate offset values, determining one group of code rate offset values from multiple groups of code rate offset values included in the second code rate offset configuration information based on pre-configuration information or higher layer configuration information, and determining the second code rate offset value from the group of code rate offset values based on the type and the bit number of the first UCI, wherein the bits in the code rate offset indication information are not used for indicating the second code rate offset configuration information.

In some possible embodiments, the processor 1210 is configured to:

the first code rate offset value is determined from a set of code rate offset values in the first code rate offset configuration information.

In some possible embodiments, the processor 1210 is configured to:

the first code rate offset value is determined based on the second code rate offset value and the first offset value.

In some possible embodiments, the pre-configuration information is used to indicate that the first set of code rate offset values or the last set of code rate offset values are selected from the plurality of sets of code rate offset values.

In some possible embodiments, the first code rate offset configuration information and the second code rate offset configuration information are configured by higher layer signaling.

Wherein in fig. 3, a bus architecture may comprise any number of interconnected buses and bridges, and in particular one or more processors represented by processor 1210 and various circuits of memory represented by memory 1220, linked together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, power management circuits, etc., which are well known in the art and, therefore, will not be described further herein. The bus interface provides an interface. Transceiver 1200 may be a number of elements, including a transmitter and a receiver, providing a means for communicating with various other apparatus over transmission media, including wireless channels, wired channels, optical cables, etc. The user interface 1230 may also be an interface capable of interfacing with an inscribed desired device for a different terminal device, including but not limited to a keypad, display, speaker, microphone, joystick, etc.

The processor 1210 is responsible for managing the bus architecture and general processing, and the memory 1220 may store data used by the processor 1210 in performing operations.

Alternatively, the processor 1210 may be a CPU (central processing unit), ASIC (Application Specific Integrated Circuit ), FPGA (Field-Programmable Gate Array, field programmable gate array) or CPLD (Complex Programmable Logic Device ), and the processor may also employ a multi-core architecture.

The processor is configured to execute any of the methods provided in the embodiments of the present application by invoking a computer program stored in a memory according to the obtained executable instructions. The processor and the memory may also be physically separate.

It should be noted that, the terminal device provided in this embodiment of the present application can implement all the method steps implemented in the method embodiment and achieve the same technical effects, and specific details of the same parts and beneficial effects as those of the method embodiment in this embodiment are not described herein.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a network device according to an embodiment of the present application. The network device provided in the embodiments of the present application includes a memory 1320, a transceiver 1300, and a processor 1310.

A transceiver 1300 for receiving and transmitting data under the control of a processor 1310, a memory 1320 for storing a computer program, and the processor 1310 for reading the computer program in the memory 1320 to realize:

In some possible embodiments, the processor 1310 is configured to:

And determining a first code rate offset value when the first UCI of the first PUCCH is multiplexed to the PUSCH and a second code rate offset value when the second UCI of the second PUCCH is multiplexed to the PUSCH based on the code rate offset configuration information indicated by the bit in the code rate offset indication information.

In some possible embodiments, the processor 1310 is configured to:

the bit number of the code rate offset indication information in the DCI of the PUSCH is determined based on the first set of code rate offset values included in the first code rate offset configuration information and the second set of code rate offset values included in the second code rate offset configuration information.

the code rate offset indication information includes log ₂ (max (A, B)) this feature, if A is greater than or equal to B, log ₂ Front log in (max (A, B)) bits ₂ (B) Or last log ₂ (B) Bits are used to indicate the second rate offset configuration information, log ₂ (max (A, B)) is used to indicate the first code rate offset configuration information, log if A is smaller than B ₂ Front log in (max (A, B)) bits ₂ (A) Or last log ₂ (A) Bits are used to indicate the first code rate offset configuration information, log ₂ A (max (a, B)) bit for indicating the second code rate offset configuration information; or,

the code rate offset indication information includes log ₂ (A)+log ₂ (B) This feature, log ₂ (A)+log ₂ (B) Log in bits ₂ (A) Bits are used to indicate the first code rate offset configuration information, log ₂ (B) Bits are used to indicate the second code rate offset configuration information.

In some possible embodiments, the processor 1310 is configured to:

Where in FIG. 4, a bus architecture may comprise any number of interconnected buses and bridges, with various circuits of the one or more processors, represented by processor 1310, and the memory, represented by memory 1320, being chained together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, power management circuits, etc., which are well known in the art and, therefore, will not be described further herein. The bus interface provides an interface. Transceiver 1300 may be a number of elements, including a transmitter and a receiver, providing a means for communicating with various other apparatus over a transmission medium, including wireless channels, wired channels, optical cables, etc. The processor 1310 is responsible for managing the bus architecture and general processing, and the memory 1320 may store data used by the processor 1310 in performing operations.

The processor 1310 may be a Central Processing Unit (CPU), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a Field-programmable gate array (Field-Programmable Gate Array, FPGA), or a complex programmable logic device (complex 13 Programmable Logic Device, CPLD), or the processor may employ a multi-core architecture.

It should be noted that, the network device provided in the embodiment of the present application can implement all the method steps implemented in the embodiment of the method and achieve the same technical effects, and the details of the same parts and the advantages as those of the embodiment of the method in the embodiment are not described in detail herein.

Referring to fig. 5, fig. 5 is a schematic structural diagram of an information transmission device according to an embodiment of the present application. The information transmission device 5 provided in the embodiment of the present application includes:

a first determining unit 51, configured to determine, based on first code rate offset configuration information and second code rate offset configuration information, a first code rate offset value when a first uplink control information UCI of a first physical uplink control channel PUCCH is multiplexed to a physical uplink shared channel PUSCH, and a second code rate offset value when a second UCI of a second PUCCH is multiplexed to the PUSCH, where the first code rate offset configuration information is code rate offset configuration information corresponding to the first UCI, the second code rate offset configuration information is code rate offset configuration information corresponding to the second UCI, priorities of the first PUCCH and the second PUCCH are different, and priorities of the PUSCH are the same as priorities of the second PUCCH;

A transmitting unit 52, configured to multiplex the first UCI and the second UCI to the PUSCH for transmission based on the first code rate offset value and the second code rate offset value.

In some possible embodiments, the first determining unit 51 is configured to:

It should be noted that, the information transmission device 5 provided in this embodiment of the present application can implement all the method steps implemented in the method embodiment and achieve the same technical effects, and specific details of the same parts and beneficial effects as those of the method embodiment in this embodiment are not described herein.

Referring to fig. 6, fig. 6 is another schematic structural diagram of an information transmission device according to an embodiment of the present application. The information transmission device 6 provided in the embodiment of the present application includes:

a second determining unit 61, configured to determine, based on first code rate offset configuration information and second code rate offset configuration information, a first code rate offset value when a first UCI of a first PUCCH is multiplexed to a PUSCH, and a second code rate offset value when a second UCI of a second PUCCH is multiplexed to the PUSCH, where the first code rate offset configuration information is code rate offset configuration information corresponding to the first UCI, the second code rate offset configuration information is code rate offset configuration information corresponding to the second UCI, priorities of the first PUCCH and the second PUCCH are different, and priorities of the PUSCH are the same as priorities of the second PUCCH;

A receiving unit 62, configured to receive the first UCI and the second UCI multiplexed and transmitted on the PUSCH based on the first code rate offset value and the second code rate offset value.

In some possible embodiments, the second determining unit 61 is configured to:

the code rate offset indication information includes log ₂ (A)+log ₂ (B) This feature, log ₂ (A)+log ₂ (B) Log in this specification ₂ (A) Bits are used to indicate the first code rate offset configuration information, log ₂ (B) This is used to indicate the second code rate offset configuration information.

In some possible embodiments, the second determining unit 61 is configured to:

It should be noted that, the information transmission device 6 provided in this embodiment of the present application can implement all the method steps implemented in the method embodiment and achieve the same technical effects, and the same parts and beneficial effects as those of the method embodiment in this embodiment are not described in detail herein.

It should be noted that, in the embodiment of the present application, the division of the units is schematic, which is merely a logic function division, and other division manners may be implemented in actual practice. In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a processor-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the above-described method of the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

In some possible implementations, the processor-readable storage medium may be any available medium or data storage device that can be accessed by a processor, including, but not limited to, magnetic storage (e.g., floppy disks, hard disks, tapes, magneto-optical disks (MOs), etc.), optical storage (e.g., CD, DVD, BD, HVD, etc.), and semiconductor storage (e.g., ROM, EPROM, EEPROM, nonvolatile storage (NAND FLASH), solid State Disk (SSD)), etc.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These processor-executable instructions may also be stored in a processor-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These processor-executable instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. An information transmission method, applied to a terminal device, comprising:

determining the bit number of code rate offset indication information in Downlink Control Information (DCI) of a Physical Uplink Shared Channel (PUSCH) based on first code rate offset configuration information and/or second code rate offset configuration information, wherein the bits in the code rate offset indication information are used for indicating the first code rate offset configuration information and/or the second code rate offset configuration information;

determining a first code rate offset value when first uplink control information UCI of a first Physical Uplink Control Channel (PUCCH) is multiplexed to a PUSCH based on code rate offset configuration information indicated by bits in the code rate offset indication information and the first code rate offset configuration information, and determining a second code rate offset value when second UCI of a second PUCCH is multiplexed to the PUSCH based on the code rate offset indication information and the second code rate offset configuration information; or,

The first offset value is an offset value between the first code rate offset value and the second code rate offset value, the first code rate offset configuration information is code rate offset configuration information corresponding to the first UCI, the second code rate offset configuration information is code rate offset configuration information corresponding to the second UCI, priorities of the first PUCCH and the second PUCCH are different, and priorities of the PUSCH are the same as priorities of the second PUCCH;

2. The method of claim 1, wherein determining the number of bits of code rate offset indication information in DCI for PUSCH based on the first code rate offset configuration information and the second code rate offset configuration information comprises:

3. The method of claim 2, wherein the first set of numbers is a, the second set of numbers is B, and a and B are positive integers;

The code rate offset indication information includes log ₂ (max (A, B)) bits, log if A is greater than or equal to B ₂ Front log in (max (A, B)) bits ₂ (B) Or last log ₂ (B) Bits are used to indicate the second code rate offset configuration information, log ₂ A (max (A, B)) bit for indicating the first code rate offset configuration information, log if A is less than B ₂ Front log in (max (A, B)) bits ₂ (A) Or last log ₂ (A) Bits are used to indicate the first code rate offset configuration information, log ₂ A (max (a, B)) bit for indicating the second code rate offset configuration information; or,

4. The method of claim 1, wherein determining the number of bits of the code rate offset indication information in the DCI of the PUSCH based on the second code rate offset configuration information comprises:

and determining the bit number of code rate offset indication information in the DCI of the PUSCH based on the second group number of code rate offset values included in the second code rate offset configuration information.

5. The method of claim 4, wherein the second set of numbers is B, B being a positive integer;

6. The method of claim 1, wherein the determining a first code rate offset value for a first UCI of a first PUCCH when multiplexed to PUSCH based on code rate offset configuration information indicated by bits in the code rate offset indication information and the first code rate offset configuration information comprises:

if the first code rate offset configuration information comprises a group of code rate offset values, determining a first code rate offset value when the first UCI is multiplexed to the PUSCH from the group of code rate offset values based on the type and the bit number of the first UCI of the first PUCCH;

if the first code rate offset configuration information includes multiple groups of code rate offset values, determining a group of code rate offset values in the multiple groups of code rate offset values included in the first code rate offset configuration information based on the DCI, and determining the first code rate offset value from the group of code rate offset values based on the type and the bit number of the first UCI, wherein the bits in the code rate offset indication information are used for indicating the first code rate offset configuration information;

7. The method of claim 1, wherein the determining the second code rate offset value based on the code rate offset configuration information indicated by the bits in the code rate offset indication information and the second code rate offset configuration information comprises:

if the second code rate offset configuration information includes multiple groups of code rate offset values, determining a group of code rate offset values in the multiple groups of code rate offset values included in the second code rate offset configuration information based on the DCI, and determining a second code rate offset value when the second UCI is multiplexed to the PUSCH from the group of code rate offset values based on the type and the bit number of the first UCI of the first PUCCH, wherein the bits in the code rate offset indication information are used for indicating the second code rate offset configuration information;

8. The method of claim 1, wherein determining the first code rate offset value based on the first code rate offset configuration information comprises:

9. The method of claim 1, wherein the determining the first code rate offset value based on the first offset value comprises:

10. The method according to claim 6 or 7, wherein the pre-configuration information is used to indicate that the first or last set of code rate offset values is selected from a plurality of sets of code rate offset values.

11. The method of claim 1, wherein the first code rate offset configuration information and the second code rate offset configuration information are configured by higher layer signaling.

12. An information transmission method, applied to a network device, comprising:

And receiving the first UCI and the second UCI multiplexed on the PUSCH based on the first code rate offset value and the second code rate offset value.

13. The method of claim 12, wherein determining the number of bits of code rate offset indication information in the DCI of the PUSCH based on the first code rate offset configuration information and the second code rate offset configuration information comprises:

14. The method of claim 13, wherein the first set of numbers is a, the second set of numbers is B, and a and B are positive integers;

15. The method of claim 12, wherein determining code rate offset indication information in DCI for PUSCH based on the second code rate offset configuration information comprises:

16. The method of claim 15, wherein the second set of numbers is B, B being a positive integer;

17. The method of claim 12, wherein the determining a first code rate offset value for a first UCI of a first PUCCH when multiplexed to PUSCH based on code rate offset configuration information indicated by bits in the code rate offset indication information and the first code rate offset configuration information comprises:

18. The method of claim 12, wherein the determining the second code rate offset value based on the code rate offset configuration information indicated by the bits in the code rate offset indication information and the second code rate offset configuration information comprises:

19. The method of claim 12, wherein determining the first code rate offset value based on the first code rate offset configuration information comprises:

20. The method of claim 12, wherein the determining the first code rate offset value based on the first offset value comprises:

21. The method according to claim 17 or 18, wherein the pre-configuration information is used to indicate that either the first or the last set of code rate offset values is selected from a plurality of sets of code rate offset values.

22. A terminal device comprising a memory, a transceiver, and a processor:

a memory for storing a computer program; a transceiver for transceiving data under control of the processor; a processor for reading the computer program in the memory and performing the method of any of claims 1 to 11.

23. A network device comprising a memory, a transceiver, and a processor:

A memory for storing a computer program; a transceiver for transceiving data under control of the processor; a processor for reading the computer program in the memory and performing the method of any of claims 12 to 21.

24. An information transmission apparatus, characterized in that the apparatus comprises:

a first determining unit, configured to determine, based on first code rate offset configuration information and/or second code rate offset configuration information, a bit number of code rate offset indication information in DCI of PUSCH, where bits in the code rate offset indication information are used to indicate the first code rate offset configuration information and/or the second code rate offset configuration information;

and the sending unit is used for multiplexing the first UCI and the second UCI to the PUSCH for transmission based on the first code rate offset value and the second code rate offset value.

25. An information transmission apparatus, characterized in that the apparatus comprises:

a second determining unit, configured to determine, based on first code rate offset configuration information and/or second code rate offset configuration information, a bit number of code rate offset indication information in DCI of PUSCH, where bits in the code rate offset indication information are used to indicate the first code rate offset configuration information and/or the second code rate offset configuration information;

and a receiving unit, configured to receive the first UCI and the second UCI multiplexed on the PUSCH based on the first code rate offset value and the second code rate offset value.

26. A processor-readable storage medium, characterized in that the processor-readable storage medium stores a computer program for causing the processor to perform the method of any one of claims 1 to 11 or to perform the method of claims 12 to 21.