CN115706582A

CN115706582A - High-speed level shifter

Info

Publication number: CN115706582A
Application number: CN202110892289.2A
Authority: CN
Inventors: 邹臣
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2021-08-04
Filing date: 2021-08-04
Publication date: 2023-02-17

Abstract

A high speed level shifter, characterized by: the latch unit is respectively connected with the series unit, the first latch unit and the second latch unit to realize level conversion from low to high; the serial unit controls the on or off states of a first branch and a second branch in the latch unit based on the output of the first latch unit and the second latch unit; the first latch unit is used for realizing latch output based on the voltage state of the first branch of the latch unit and controlling the on or off of the first branch in the series unit based on the first latch output; the second latch unit is used for realizing latch output based on the voltage state of the second branch of the latch unit and controlling the on or off of the second branch in the series unit based on the second latch output; and the output unit is connected with the second latch unit and is used for realizing level conversion output based on the output of the second latch unit. The circuit of the invention has simple structure, low cost, high level conversion speed and good effect.

Description

High-speed level shifter

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a high speed level shifter.

Background

Level shifters are widely used in various integrated circuits to provide proper operating voltages for various circuit modules. A level shifter commonly used in the prior art is shown in fig. 1, and the main operation principle is that low power voltage signals which are opposite to each other are input to gate terminals of two mirrored NMOS transistors in a symmetric latch structure, so as to flip the operating states of two PMOS transistors in the latch structure, and thus, two PMOS transistors of which the operating levels are high power voltage in the latch structure are switched to on or off states. The circuit may then output a high supply voltage signal corresponding to the low supply voltage signal after passing through an inverter.

However, there are still problems with such conventional level shifters in the prior art. First, when the voltage signal has a fast inversion speed, the level shifter generates a certain delay when the PMOS transistor is controlled to be turned on or off by switching the state of the NMOS transistor, which results in a limited conversion speed of the level shifter, and thus, the level shifter cannot perform accurate level shifting on a signal with a high inversion frequency of an input level. In order to ensure accurate level conversion of high-frequency signals, the sizes of the PMOS transistor and the NMOS transistor in the selected level converter need to be large enough, which results in that the manufacturing area of the chip is difficult to reduce, and the power loss of the level conversion is relatively large.

Secondly, in the level shifter in the prior art, during the level shifting process, one branch formed by the NMOS transistor Mn1 and the PMOS transistor Mp2 or one branch formed between the NMOS transistor Mn2 and the PMOS transistor Mp1 is always in a conducting state and forms a through current, thereby causing a large power loss in the working process, consuming a large amount of electric energy from a power supply, generating a large amount of heat, affecting the performance of other temperature sensitive circuits, and further posing a certain threat to the safety of a chip.

Finally, when the input ends of the two NMOS transistors in such a level shifter do not monitor the input voltage, the two NMOS transistors will both be in the off state, and with the turn-on of the high power voltage V _ hi, the potentials of the input ends of the two PMOS transistors in the latch structure are not constant, which may cause the oscillation of the output end of the circuit. This results in the subsequent circuits connected to their outputs not being able to maintain a safe and normal operating state.

In view of the above, a need exists for a new high speed level shifter.

Disclosure of Invention

In order to solve the disadvantages of the prior art, an object of the present invention is to provide a high-speed level shifter, in which a series unit and first and second latch units with smaller PMOS transistor sizes are added to a level shifter commonly used in the prior art, so as to realize high-speed level shifting.

The invention adopts the following technical scheme. A high-speed level shifter, wherein the shifter includes a latch unit, a series unit, a first latch unit, a second latch unit, and an output unit; the latch unit is respectively connected with the series unit, the first latch unit and the second latch unit and is used for realizing level conversion from low to high; the series unit is respectively connected with the latch unit, the first latch unit and the second latch unit and is used for controlling the on or off states of a first branch and a second branch in the latch unit based on the output of the first latch unit and the output of the second latch unit; the first latch unit is connected with the latch unit and the series unit and used for realizing latch output based on the voltage state of the first branch of the latch unit and controlling the on or off of the first branch in the series unit based on the first latch output; the second latch unit is connected with the latch unit, the series unit and the output unit, and is used for realizing latch output based on the voltage state of a second branch of the latch unit and controlling the on or off of the second branch in the series unit based on the second latch output; and the output unit is connected with the second latch unit and is used for realizing level conversion output based on the output of the second latch unit.

Preferably, the size of the PMOS tube in the first latch unit and the second latch unit is smaller than that of the PMOS tube in the latch unit.

Preferably, the latch unit comprises NMOS tubes Mn1 and Mn2, PMOS tubes Mp1 and Mp2; the drain electrodes of Mn1 and Mp1 form a first branch, the drain electrodes are connected with each other, the source electrodes are respectively grounded and the drain electrode of a PMOS tube Mp3 In the series unit, the grid electrode of Mp1 is connected with the drain electrode of Mp2, and the grid electrode of Mn1 is connected with an input level In; mn2 and Mp2 constitute a second branch, the drains of which are connected to each other, the sources of which are respectively grounded and the drain of a PMOS tube Mp4 in the series unit, the gate of Mp2 is connected to the drain of Mp1, and the gate of Mn2 is connected to the inverted level Inn of the input level.

Preferably, the series unit comprises PMOS transistors Mp3 and Mp4; the source electrode of the PMOS tube Mp3 is connected with a power supply voltage V _ hi, the drain electrode of the PMOS tube Mp3 is connected with the source electrode of the PMOS tube Mp1 in the latch unit to form a part of a first branch circuit, and the grid electrode of the PMOS tube Mp3 is connected with the first latch output of the first latch unit; the source of the PMOS transistor Mp4 is connected to the power supply voltage V _ hi, the drain is connected to the source of the PMOS transistor Mp2 in the latch unit to form a part of the second branch, and the gate is connected to the second latch output of the second latch unit.

Preferably, the first latch unit and the second latch unit have the same structure and respectively comprise a latch, an NMOS transistor and an inverter; the latch and the inverter are sequentially connected in series, the input end of the latch is connected with the drain voltage of the NMOS tube in the first or second branch, and the output end of the inverter is connected with the gate of the PMOS tube in the series unit in the first or second branch; and the grid electrode and the drain electrode of the NMOS tube are respectively connected with the latch.

Preferably, the latch in the first latch unit comprises PMOS tubes Mp6 and Mp9, and the latch in the second latch unit comprises PMOS tubes Mp5 and Mp7; the grid electrode of one of the two PMOS tubes in the latch is connected with the drain electrode of the other tube to form a latch structure.

Preferably, the NMOS transistor in the first latch unit is Mn5, and the NMOS transistor in the second latch unit is Mn3; the source electrode of an NMOS tube in the first latch unit is grounded, and the grid electrode and the drain electrode are respectively connected with the latch in the first latch unit; the source electrode of the NMOS tube in the second latch unit is grounded, and the grid electrode and the drain electrode are respectively connected with the latch in the second latch unit.

Preferably, the inverter in the first latch unit comprises a PMOS transistor Mp10 and an NMOS transistor Mn6; the phase inverter in the second latch unit comprises a PMOS tube Mp8 and an NMOS tube Mn4; the drain electrodes of the NMOS tube and the PMOS tube are connected with each other, the grid electrodes of the NMOS tube and the PMOS tube are connected with each other, and the source electrodes of the NMOS tube and the PMOS tube are respectively connected to the ground potential and the power voltage V _ hi.

Preferably, the output unit comprises an inverter composed of a PMOS transistor Mp11 and an NMOS transistor Mn7, an input end of the inverter is connected to an output end of the second latch unit, and an output end of the inverter is used as a level conversion output.

Preferably, when the input of the input level In is a high level, under the action of the first latch unit, the first branch In the latch unit is turned on, and the level conversion output is a low level; when the input of the input level In is low level, the second branch In the latch unit is conducted under the action of the second latch unit, and the level conversion output is high level.

Compared with the prior art, the high-speed level shifter has the advantages that the first latch unit and the second latch unit with smaller sizes of the series unit and the PMOS tube are added in the common level shifter, so that the high-speed level shifting is realized. The circuit of the invention has simple structure, low cost, high level conversion speed and good effect.

The beneficial effects of the invention also include:

1. because the MOS transistor with a smaller size has a poorer control capability for the output power and the current, the size of the PMOS transistor and the size of the NMOS transistor in the level shifter unit in the prior art both need to be larger to ensure the conversion of the level shifter for the high-frequency voltage signal. In the invention, the first latch unit and the second latch unit are added, the PMOS tube with very small size for realizing the latch function is provided in the latch unit, and the control capability of the drain voltage of the NMOS tube on or off states of the Mp2 tube and the Mp1 tube is enhanced, so that the requirement on the size of the MOS tube in the latch unit is reduced by the improved level shifter. Even if a MOS tube with a smaller size is adopted, the turnover rate of high and low levels can still be ensured to a higher degree.

2. In the invention, a series unit is added, and two PMOS tubes in the series unit are respectively connected above the PMOS tube of the original latch unit in series, so that two series PMOS tubes on the same branch, such as Mp1 and Mp3, or Mp2 and Mp4, can not be conducted simultaneously. This makes first branch road and second branch road not have the state of direct switch-on, when first branch road and second branch road realize switching on, all need directly switch on through first or second latch unit to prevent through current, reduced power loss, practiced thrift the power.

3. In the invention, when the input end, namely the grids of the two NMOS transistors Mn1 and Mn2 do not receive the input voltage signal provided by the superior circuit, the first latch unit and the second latch unit ensure that two points A, B are always at high potential due to the action of the power voltage V _ hi and the small-sized PMOS transistor connected across two ends of the inverter. Therefore, the series unit can be set to be in an open circuit state, the oscillation which can occur in the output process of the level converter in the prior art is prevented, and the output end is always kept in a low level state.

Drawings

FIG. 1 is a schematic circuit diagram of a high-speed level shifter according to the prior art;

fig. 2 is a schematic circuit diagram of a high-speed level shifter according to the present invention.

Detailed Description

The present application is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present application is not limited thereby.

Fig. 1 is a schematic circuit diagram of a high-speed level shifter according to the prior art. As shown in fig. 1, a level shifter includes NMOS transistors Mn2, and Mn7, and PMOS transistors Mp1, mp2, and Mp11, wherein the sources of the NMOS transistors Mn1 and Mn2 are grounded, and the gates are respectively connected to an input level signal and an inverted level signal of the input level signal. And the drain electrodes are respectively connected to the drain electrodes of the PMOS tubes Mp1 and Mp 2. In addition, the sources of the PMOS tubes Mp1 and Mp2 are both connected to the power supply voltage or a higher voltage V _ hi to be converted, and the grid of one of the two tubes is connected with the drain of the other tube. The NMOS transistor Mn7 and the PMOS transistor Mp11 form a common inverter, the input end of the inverter is connected with the drain electrodes of Mp1 and Mn1, and the output end outputs a level signal after level conversion.

As shown in fig. 1, since the input signals of the two NMOS transistor gates are input to the level shift circuit after passing through the inverter with the power supply voltage V _ low, the level of the input signal can be considered to make a transition between 0 and V _ low. Since the device voltages of the latch structure and the inverter structure are both V _ hi, the level of the output signal of the level shifter circuit should jump between 0 and V _ hi, i.e., the level shifter converts the input level logic in the interval from 0 to V _ low into the output level logic from 0 to V _ hi.

Since the prior art level shifter still has various problems, the present invention provides a new high-speed level shifter.

Fig. 2 is a schematic circuit diagram of a high-speed level shifter according to the present invention. As shown in fig. 2, a high speed level shifter includes a latch unit, a series unit, a first latch unit, a second latch unit, and an output unit; the latch unit is respectively connected with the series unit, the first latch unit and the second latch unit and is used for realizing level conversion from low to high; the series unit is respectively connected with the latch unit, the first latch unit and the second latch unit and is used for controlling the opening or closing states of a first branch circuit and a second branch circuit in the latch unit based on the output of the first latch unit and the output of the second latch unit; the first latch unit is connected with the latch unit and the series unit and used for realizing latch output based on the voltage state of the first branch of the latch unit and controlling the on or off of the first branch in the series unit based on the first latch output; the second latch unit is connected with the latch unit, the series unit and the output unit, and is used for realizing latch output based on the voltage state of a second branch of the latch unit and controlling the on or off of the second branch in the series unit based on the second latch output; and the output unit is connected with the second latch unit and is used for realizing level conversion output based on the output of the second latch unit.

It can be understood that, in the present invention, in order to improve the control capability of the NMOS transistor in the latch unit to the operating state of the PMOS transistor, two PMOS transistors in the original circuit are bypassed, a latch structure is added, and the input terminal of the latch structure is allowed to be connected to the drain of the NMOS transistor, and the output terminal is connected to the high level position in the latch unit, so that the drain voltage of the NMOS transistor does not pass through the latch PMOS transistors Mp1 and Mp2, but directly passes through the latch structure to control the on or off state at the high level position.

In order to control the first and second branches, respectively, a first and a second latch unit are provided. In order to enable the output of the latch unit to control the on and off of the first branch and the second branch, a series unit is further arranged, and two PMOS tubes are respectively connected in series on the first branch and the second branch. In addition, the output unit is realized based on the output of the second latch unit.

Specifically, the latch structure In the latch unit is turned on regardless of whether the input voltages In and Inn are applied to the circuit. When the latch structure is turned on, the small-sized PMOS transistor pulls up the drain voltage thereof, that is, the voltage at the input terminals of the first and second latch units, i.e., the voltage at two points A, B in the figure, is pulled up. At this time, the output ends of the first and second latch units are respectively connected to the gates of the PMOS transistors in the first and second branches, so that the high voltage prevents the conduction of the first and second branches, so that both the first and second branches are in the off state, and the voltage at A, B is kept at the high voltage state for a long time.

Therefore, in the invention, even if the power supply voltage V _ low of the input end does not exist, the output of the circuit can still be ensured not to be abnormal, but can be maintained in a low level state, and the subsequent circuit is not influenced. Also, since both the first and second branches are maintained in the off state, power is not consumed.

It is understood that in the first latch unit and the second latch unit, smaller sized PMOS transistors may be provided as latch structures, respectively. Since the PMOS transistor in the latch unit has a smaller size, it is easier to be turned on. That is to say, when one of the input voltages In or Inn is In a higher voltage state, one of the NMOS transistors is turned on, so as to pull down the voltage of the drain of the NMOS transistor, at this time, the effect of the NMOS transistor on the voltage pull-down may not be good enough, and if it is desired to turn on the PMOS transistor In the latch structure above the NMOS transistor, a certain time is required. However, when the small-sized PMOS transistor is connected, the NMOS transistor can immediately turn on the corresponding first or second latch structure, so that the latch unit outputs a low voltage corresponding to the NMOS transistor. Thereby also controlling the conduction of the first or second branch and outputting the corresponding regulated voltage as the level shifted output of the level shifter.

Therefore, by adopting the circuit in the invention, the first and second latch structures can more sensitively acquire the level conversion state, so as to output more immediately. Thus improving the level conversion rate.

Similar to the level shifter In the prior art, the latch unit In the present invention also includes two PMOS transistors connected In a latch manner, and an NMOS transistor below the PMOS transistor, where the NMOS transistor receives the input levels In and Inn In opposite directions. The difference from the prior art is that two PMOS tubes are respectively connected with the PMOS tubes in the series unit instead of being directly connected with the power supply voltage, thereby preventing the generation of through current.

Specifically, the number of PMOS transistors in the latch unit is increased by the series unit, and two PMOS transistors connected in series are respectively arranged in the first branch and the second branch, and since the two PMOS transistors are respectively controlled based on the voltage at the output end of one latch unit and the voltage at the input end of the other latch unit, when the input level is not switched, the two PMOS transistors are not in a conducting state, and therefore, a long-time through current does not exist.

Preferably, the first latch unit and the second latch unit have the same structure and respectively comprise a latch, an NMOS transistor and an inverter; the latch and the phase inverter are sequentially connected in series, the input end of the latch is connected with the drain voltage of the NMOS tube in the first or second branch circuit, and the output end of the phase inverter is connected with the grid of the PMOS tube of the series unit in the first or second branch circuit; and the grid electrode and the drain electrode of the NMOS tube are respectively connected with the latch.

It will be appreciated that when no input voltage is present in the circuit, A, B is at high potential for both points, and the first and second branches are off. When an input voltage is input, for example, when In is high and Inn is low, mn1 is turned on and Mn2 is still In an off state. At this time, the potential at point a is pulled low, while point B remains at a high potential. Under the influence of the potential drop of the point A, the first latch unit starts to work, the voltage of the grid electrode of the Mp6 is increased to be high, the small-sized PMOS tube Mp6 is cut off, the conducting state maintained before the small-sized PMOS tube Mp6 is broken, and after the small-sized PMOS tube Mp6 passes through the phase inverter formed by the Mn6 and the Mp10, the potential output to the point C by the first latch unit is also low. When the potential at the point C is low, the PMOS transistor Mp3 is turned on, and the first branch is in an on state.

Meanwhile, because the point B is still kept in a high potential state, the small-size PMOS tube Mp5 is still in a conducting state, the output of the latch structure is low, the output of the point D after passing through the phase inverter is high, the Mp4 cannot be conducted, and the second branch is in a disconnected state.

When the input signals In and Inn are inverted, in changes from high to low and Inn changes from low to high. At this time, the potential of the point A is increased, the potential of the point B is reduced, so that the first branch is disconnected, the second branch is connected, and the states of the two branches are interchanged.

Preferably, the latch in the first latch unit comprises PMOS transistors Mp6 and Mp9, and the latch in the second latch unit comprises PMOS transistors Mp5 and Mp7; the grid electrode of one of the two PMOS tubes in the latch is connected with the drain electrode of the other tube to form a latch structure.

It can be understood that the latch structure of the first latch unit and the second latch unit replaces the latch structure in the original latch unit, so that when the input level changes, the state of the PMOS transistor in the latch structure is easier to change, thereby controlling the change of the output level.

It will be appreciated that the size of Mp9 and Mp7 in PMOS transistors corresponds to the size of MOS transistors used in inverters commonly used in the prior art. In addition, the size of the PMOS transistors Mp5 and Mp6 forming the latch can be designed to be smaller, so as to ensure that Mn1 and Mn2 are more easily driven by them.

Specifically, the NMOS transistor can be turned on to lower the output of the latch structure when the input of the latch structure is high, and turned off to pull up the output of the latch structure when the input of the latch structure is low.

The function of the inverter in the present invention is the same as that of the inverter in the prior art, and will not be described herein.

Preferably, the output unit comprises an inverter composed of a PMOS transistor Mp11 and an NMOS transistor Mn7, an input end of the inverter is connected to an output of the second latch unit, and an output end of the inverter is used as a level conversion output.

In order to ensure output logic, an inverter is arranged in an output unit, and a signal passing through the inverter is used as the output of a level converter. The output is inversely converted according to the level of the potential at the point D.

Preferably, when the input of the input level In is a high level, the first branch In the latch unit is turned on under the action of the first latch unit, and the level conversion output is a low level; when the input of the input level In is low level, the second branch In the latch unit is conducted under the action of the second latch unit, and the level conversion output is high level.

Specifically, when the input level In is high, mn1 is turned on and Mn2 is turned off, at which time the first latch unit changes state and outputs a low voltage, while the second latch unit still maintains the output of a high voltage, at which time the level-shifted output goes low through one latch structure and two inverters. On the other hand, when the input of the input level In is low and the input of Inn is high, the level-shifted output becomes high.

Compared with the prior art, the high-speed level shifter has the advantages that the first latch unit and the second latch unit with smaller sizes of the series unit and the PMOS tube can be added in the common level shifter, so that the high-speed level shifting is realized. The circuit of the invention has simple structure, low cost, high level conversion speed and good effect.

The present applicant has described and illustrated embodiments of the present invention in detail with reference to the accompanying drawings, but it should be understood by those skilled in the art that the above embodiments are only preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not for the purpose of limiting the scope of the present invention, and on the contrary, any modifications or modifications based on the spirit of the present invention should fall within the scope of the present invention.

Claims

1. A high speed level shifter, characterized by:

the converter comprises a latch unit, a series unit, a first latch unit, a second latch unit and an output unit; wherein the content of the first and second substances,

the latch unit is respectively connected with the series unit, the first latch unit and the second latch unit and is used for realizing level conversion from low to high;

the series unit is respectively connected with the latch unit, the first latch unit and the second latch unit and is used for controlling the on or off states of a first branch and a second branch in the latch unit based on the output of the first latch unit and the output of the second latch unit;

the first latch unit is connected with the latch unit and the series unit, and is used for realizing latch output based on the voltage state of a first branch of the latch unit and controlling the on or off of the first branch in the series unit based on the first latch output;

the second latch unit is connected with the latch unit, the series unit and the output unit, and is used for realizing latch output based on the voltage state of a second branch of the latch unit and controlling the on or off of the second branch in the series unit based on the second latch output;

and the output unit is connected with the second latch unit and used for realizing level conversion output based on the output of the second latch unit.

2. A high speed level shifter as claimed in claim 1, wherein:

the size of the PMOS tube in the first latch unit and the second latch unit is smaller than that of the PMOS tube in the latch unit.

3. A high speed level shifter as recited in claim 2, wherein:

the latch unit comprises NMOS tubes Mn1 and Mn2 and PMOS tubes Mp1 and Mp2; wherein the content of the first and second substances,

the Mn1 and the Mp1 form a first branch, drains of the first branch are connected with each other, sources of the first branch are respectively grounded and connected with a drain of a PMOS (P-channel metal oxide semiconductor) tube Mp3 In the series unit, a grid of the Mp1 is connected with a drain of an Mp2, and a grid of the Mn1 is connected with an input level In;

the Mn2 and the Mp2 form a second branch, the drains of the second branch are connected with each other, the sources of the second branch are respectively grounded and the drain of a PMOS tube Mp4 in the series unit, the grid of the Mp2 is connected with the drain of the Mp1, and the grid of the Mn2 is connected with the inverted level Inn of the input level.

4. A high speed level shifter as claimed in claim 3, wherein:

the series unit comprises PMOS tubes Mp3 and Mp4; wherein the content of the first and second substances,

the source electrode of the PMOS tube Mp3 is connected with a power supply voltage V _ hi, the drain electrode of the PMOS tube Mp3 is connected with the source electrode of the PMOS tube Mp1 in the latch unit to form a part of a first branch, and the grid electrode of the PMOS tube Mp3 is connected with the first latch output of the first latch unit;

the source of the PMOS tube Mp4 is connected with a power supply voltage V _ hi, the drain of the PMOS tube Mp4 is connected with the source of the PMOS tube Mp2 in the latch unit to form a part of a second branch, and the grid of the PMOS tube Mp4 is connected with the second latch output of the second latch unit.

5. A high speed level shifter as claimed in claim 4, wherein:

the first latch unit and the second latch unit have the same structure and respectively comprise a latch, an NMOS (N-channel metal oxide semiconductor) tube and a phase inverter;

the latch and the phase inverter are sequentially connected in series, the input end of the latch is connected with the drain voltage of an NMOS tube in the first or second branch circuit, and the output end of the phase inverter is connected with the grid electrode of a PMOS tube of the series unit in the first or second branch circuit;

and the grid electrode and the drain electrode of the NMOS tube are respectively connected with the latch.

6. A high speed level shifter as claimed in claim 5, wherein:

the latch in the first latch unit comprises PMOS tubes Mp6 and Mp9, and the latch in the second latch unit comprises PMOS tubes Mp5 and Mp7;

and the grid electrode of one of the two PMOS tubes in the latch is connected with the drain electrode of the other tube to form a latch structure.

7. A high speed level shifter as recited in claim 6, wherein:

the NMOS tube in the first latch unit is Mn5, and the NMOS tube in the second latch unit is Mn3;

the source electrode of an NMOS tube in the first latch unit is grounded, and the grid electrode and the drain electrode are respectively connected with a latch in the first latch unit;

and the source electrode of an NMOS tube in the second latch unit is grounded, and the grid electrode and the drain electrode are respectively connected with the latch in the second latch unit.

8. A high speed level shifter as claimed in claim 7, wherein:

the phase inverter in the first latch unit comprises a PMOS tube Mp10 and an NMOS tube Mn6; the phase inverter in the second latch unit comprises a PMOS tube Mp8 and an NMOS tube Mn4;

the drain electrodes of the NMOS tube and the PMOS tube are connected with each other, the grid electrodes of the NMOS tube and the PMOS tube are connected with each other, and the source electrodes of the NMOS tube and the PMOS tube are respectively connected to the ground potential and the power voltage V _ hi.

9. A high speed level shifter as recited in claim 8, wherein:

the output unit comprises a phase inverter composed of a PMOS (P-channel metal oxide semiconductor) transistor Mp11 and an NMOS (N-channel metal oxide semiconductor) transistor Mn7, the input end of the phase inverter is connected with the output end of the second latch unit, and the output end of the phase inverter is used as level conversion output.

10. A high speed level shifter as claimed in claims 1-9, wherein:

when the input of the input level In is a high level, a first branch In the latch unit is conducted under the action of the first latch unit, and the level conversion output is a low level;

when the input of the input level In is a low level, a second branch In the latch unit is conducted under the action of the second latch unit, and the level conversion output is a high level.