CN115706574A - 无闩锁高压器件 - Google Patents

无闩锁高压器件 Download PDF

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CN115706574A
CN115706574A CN202210640419.8A CN202210640419A CN115706574A CN 115706574 A CN115706574 A CN 115706574A CN 202210640419 A CN202210640419 A CN 202210640419A CN 115706574 A CN115706574 A CN 115706574A
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drain
diode
substrate
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赵利杰
郭仲贤
赖苏明
方召
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Xidi Microelectronics International Co ltd
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Abstract

本发明公开了一种无闩锁负载开关装置，包括由形成在衬底上方的隔离环围绕的第一漏极/源极区和第二漏极/源极区，隔离环被配置为浮动的，并且第一二极管连接于衬底与隔离环之间，其中第一二极管为肖特基二极管。通过上述方式，能够避免闩锁。

Description

无闩锁高压器件
优先权主张和交叉引用
本申请主张2021年8月4日提交的标题为“无闩锁高压器件”的美国临时申请号17/393,875的权益，该申请由此以引用的方式并入到本文。
技术领域
本发明涉及负载开关技术领域，特别是涉及包括一对背靠背连接的晶体管的无闩锁负载开关。
背景技术
随着半导体技术的进一步发展，金属氧化物半导体场效应晶体管(MOSFET)器件已广泛应用于集成电路中。MOSFET是电压控制器件。当控制电压加在MOSFET的栅极上，并且控制电压大于MOSFET的阈值时，MOSFET的漏极和源极之间就建立了导电沟道。建立导电通道后，电流在MOSFET的漏极和源极之间流动。另一方面，当施加到栅极的控制电压小于MOSFET的阈值时，MOSFET相应地关闭。
负载开关用于建立第一电子装置(例如，负载)与第二电子装置(例如，电源)之间的连接，或用于断开第一电子装置与第二电子装置之间的连接。负载开关可由外部控制信号控制。在操作中，当负载开关关闭时，负载开关能够阻止电流双向流动。另一方面，当负载开关开启时，第一电子装置与第二电子装置之间会建立导电路径。负载开关可以实现为具有两个背靠背连接的晶体管的隔离开关。背靠背连接的晶体管能够实现双向电流阻断。
负载开关可以包括多个N型区域和P型区域。负载开关的N型区域和P型区域可以形成PNP双极晶体管和NPN双极晶体管。两个双极晶体管都是寄生晶体管。负载开关的NPN双极晶体管和PNP双极晶体管构成一个晶闸管，其中PNP双极晶体管堆叠在NPN双极晶体管上。如果其中一个寄生晶体管无意中导通，则可能发生闩锁。一旦负载开关处于闩锁状态，负载开关可能会因大漏电流引起的过大功耗而损坏。闩锁是一种非常不希望的操作条件。希望有一个简单可靠的电路来避免闩锁。
发明内容
本发明实施例旨在提供包括一对背靠背连接的晶体管的无闩锁负载开关，能够解决或规避上述问题，并且实现技术优势。
为实现上述目的，第一方面，本发明提供一种无闩锁负载开关装置，包括：由形成在衬底上方的隔离环围绕的第一漏极/源极区和第二漏极/源极区，隔离环被配置为浮动的，并且第一二极管连接于衬底与隔离环之间，其中第一二极管为肖特基二极管。
第二方面，本发明提供一种形成负载开关的方法，该方法包括在具有第一导电类型的衬底上生长具有第一导电类型的外延层，在外延层中形成具有第二导电类型的隔离环，隔离环包括埋层、多个第一区域和多个第二区域，在隔离环中形成第一漏极/源极区和第二漏极/源极区，并在衬底上方形成第一肖特基二极管，其中第一肖特基二极管的阳极为与衬底连接的金属触点，第一肖特基二极管的阴极为与隔离环连接的第二导电型区域。
第三方面，本发明提供一种负载开关，包括第一晶体管和背靠背连接到第一晶体管的第二晶体管，其中第一晶体管的漏极、第二晶体管的漏极和两个晶体管共享的源极形成在衬底上方且位于隔离环内，隔离环被配置为浮动的，并且第一肖特基二极管连接在衬底和隔离环之间。
本发明实施例的有益效果是：本发明提供的无闩锁负载开关装置包括：由形成在衬底上方的隔离环围绕的第一漏极/源极区和第二漏极/源极区，形成的隔离环被配置为浮动的，并且第一二极管连接于衬底与隔离环之间，其中第一二极管为肖特基二极管。通过上述方式，能够避免闩锁。
前面已经相当广泛地概述了本申请的特征和技术优点，以便可以更好地理解以下公开的详细描述。下文将描述本申请的附加特征和优点，其形成本申请权利要求的主题。本领域技术人员应当理解，所公开的概念和具体实施例可以容易地用作修改或设计用于实现本申请的相同目的的其他结构或过程的基础。本领域技术人员还应该认识到，这样的等效结构不脱离所附权利要求中阐述的本申请的精神和范围。
附图说明
为了更全面地理解本申请及其优点，现在结合附图参考以下描述，图中：
图1示出根据本申请的各种实施例的包括共享源极晶体管的负载开关的示意图；
图2示出根据本申请的各种实施例的在图1所示的负载开关中形成的寄生结构的示意图；
图3示出根据本申请的各种实施例的无闩锁负载开关装置的框图；
图4示出根据本申请的各种实施例的图3所示的无闩锁负载开关装置的负载开关的简化截面图；
图5示出根据本申请的各种实施例的图3所示的无闩锁负载开关装置的肖特基二极管的简化截面图；
图6示出根据本申请的各种实施例的用于形成图1中所示的负载开关的方法的流程图；
图7示出根据本申请的各种实施例的在传统负载开关中形成的寄生结构的示意图。
除非另外指示，否则不同图中的对应数字和符号一般指对应部分。绘制附图是为了清楚地说明各种实施例的相关方面，它们不一定按比例绘制。
具体实施方式
下文详细论述目前较佳的实施例的制作和使用。但是，应明白，本申请提供可在各种各样的特定背景中实施的许多适用的发明概念。论述的特定实施例只是说明制作和使用本申请的特定方式，而不是限制本申请的范围。
本申请将针对具体上下文中的实施例进行描述，即包括一对背靠背连接的金属氧化物半导体场效应晶体管(MOSFET)器件的无闩锁负载开关。本申请的实施例还可以应用于各种半导体器件。在下文中，将参照附图详细说明各种实施例。
图1图示了根据本申请的各种实施例的包括共享源极晶体管的负载开关的示意图。负载开关可以实现为两个背靠背连接的MOSFET器件。这两个MOSFET器件共享一个源极。在整个描述中，负载开关可以替代地称为共享源极晶体管。
如图1所示，负载开关包括两个背靠背连接的N型MOSFET器件。第一MOSFET器件S1具有连接到第一输入/输出端子IO1的漏极。第二MOSFET器件S2具有连接到第二输入/输出端子IO2的漏极。第一MOSFET器件S1的栅极连接到第二MOSFET器件S2的栅极，还通过电流源I1连接到偏置电压源VDD。第一MOSFET器件S1的源极直接连接到第二MOSFET器件S2的源极。换言之，第一MOSFET器件S1和第二MOSFET器件S2共用一个源极。如图1所示，电阻R1连接在两个MOSFET器件的栅极和公共源极之间。
在一些实施例中，偏置电压源VDD的输出电压大于两个MOSFET器件的公共源极电压。偏置电压源VDD可以通过诸如电荷泵、自举电路等合适的偏置电路来建立。电流源I1为可控电流源。电阻R1是栅极到源极电阻。电阻R1两端的电压(I1×R1)是用于控制负载开关通断的栅极电压。
图1所示的共享源极晶体管可以用作负载开关。负载开关能够实现双向电流阻断。因此，负载开关也称为隔离开关。
在一些实施例中，两个背靠背连接的N型MOSFET器件形成在衬底上方的隔离环(ISO)中。在一些实施例中，衬底102是P型衬底(如图4所示)。隔离环ISO包括一个N型埋层104和两个N型侧壁136、146(如图4所示)。隔离环ISO被配置为将P型体端子112(例如，图4中所示的DPW，deep P-type well,或深P阱)与P型衬底102隔离。
二极管D4形成在两个MOSFET器件的公共源极和隔离环ISO之间。如图1所示，二极管D4的阳极连接到公共源极。二极管D4的阴极连接到隔离环ISO。此外，在P型衬底PSUB和隔离环ISO之间形成二极管D3。如图1所示，二极管D3的阳极连接到P型衬底PSUB。二极管D3的阴极连接到隔离环ISO。二极管D5形成在第一MOSFET器件S1的公共源极和漏极之间。在第二MOSFET器件S2的公共源极和漏极之间形成二极管D6。需要注意的是，D3、D5和D6是由负载开关的各种器件P/N结形成的寄生二极管。
负载开关还包括两个肖特基二极管和一个寄生电阻。如图1所示，第一肖特基二极管D1连接在P型衬底PSUB和隔离环ISO之间。在一些实施例中，第一肖特基二极管D1的阳极是金属触点。第一肖特基二极管D1的金属触点通过合适的半导体互连器件(例如，多条金属线和通孔)连接到P型衬底PSUB的金属触点。第一肖特基二极管D1的阴极是连接到隔离环的N型区域(例如，图5所示的HDNW210)。后面将结合图5描述第一肖特基二极管D1的详细结构。
第二肖特基二极管D2连接在P型衬底PSUB和地(例如，接地平面GND)之间。在一些实施例中，第二肖特基二极管D2的阳极是金属触点。第二肖特基二极管D2的金属触点通过合适的互连器件(例如，多条金属线和通孔)连接到P型衬底PSUB的金属触点。第二肖特基二极管D2的阴极是通过合适的互连器件(例如，多条金属线和通孔)连接到接地平面的N型区域。后面将结合图5对第二肖特基二极管D2的详细结构进行说明。
寄生电阻表示为连接在P型衬底PSUB和地之间的电阻器R2。电阻器R2表示从负载开关的衬底到连接多个衬底的接地平面的寄生电阻。在一些实施例中，负载开关下方的衬底不直接连接到接地平面。负载开关下方的衬底通过多个P型区域和合适的互连器件(例如，多个金属线和通孔)连接到接地平面。多个P型区域和合适的互连器件被配置成使得从负载开关的衬底到地的寄生电阻大于1千欧。
在操作中，第一MOSFET器件S1的漏极可以连接到交流电源，例如无线充电接收器线圈的端子。在一些实施例中，馈入第一MOSFET器件S1的漏极的电压在从大约-40V到大约40V的范围内。第二MOSFET器件S2的漏极可以连接到诸如整流器的接收器设备。在这种配置中，负载开关可以由电阻R1两端的电压(I1×R1)控制。在操作中，当负载开关关断时，负载开关能够阻止电流双向流动。另一方面，当负载开关通过施加大于阈值电压(例如0.7V)的栅源电压(I1×R1)而导通时，在第一输入/输出端子IO1和第二输入/输出端子IO2之间建立导电通路。通过该导电通路，电流流过负载开关。
在操作中，隔离环被配置为浮动的。换言之，隔离环没有连接到任何电源(例如，偏置电压源VDD)。由于没有连接任何电源，隔离环不具备强电流驱动能力。因此，隔离环对寄生电阻的变化不敏感。P型衬底PSUB也不直接接地。相反，PSUB通过寄生电阻R2接地。换言之，P型衬底PSUB弱耦合到地。第一个肖特基二极管D1用于通过中断负载开关中形成的晶闸管中的正反馈来防止发生闩锁。当第一输入/输出端子IO1/第二输入/输出端子IO2接收到极限的负压(例如，-40V)时，浮动的隔离环(ISO)可防止产生过大的电流和热量。此外，浮动的隔离环(ISO)可防止由二极管D4和二极管D5形成的NPN晶体管意外导通。第二肖特基二极管D2用作钳位二极管。如果在P型衬底PSUB处出现大于正向二极管压降(例如，0.3V或0.4V)的正电压，则第二肖特基二极管D2能够防止P型衬底PSUB处的电压超过一个正向二极管压降。这可以防止弱接地的P型衬底PSUB在正电压方向上波动过高，从而防止依赖于P型衬底PSUB电位作为参考的电路发生故障。
需要说明的是，图1所示的负载开关由两个N型MOSFET器件构成。具有N型MOSFET器件的一个有利特征是与尺寸相似的P型MOSFET器件相比，N型MOSFET器件具有低导通电阻。此外，N型MOSFET器件的控制电路简单、鲁棒性好，提高了负载开关的可靠性。
图2示出了根据本申请的各种实施例的在图1所示的负载开关中形成的寄生结构的示意图。寄生结构包括彼此相邻堆叠的PNP晶体管Q1和NPN晶体管Q2。回到图1，PNP晶体管Q1由寄生二极管D3和寄生二极管D4形成，NPN晶体管Q2由寄生二极管D4和寄生二极管D5/D6形成。PNP晶体管Q1的发射极连接到P型衬底PSUB。PNP晶体管Q1的基极连接到隔离环。NPN晶体管Q2的发射极连接到第一输入/输出端子IO1和/或第二输入/输出端子IO2。PNP晶体管Q1的集电极和NPN晶体管Q2的基极连接到两个N型MOSFET器件的公共源极节点。图2所示的寄生结构相当于一个晶闸管。
图7示出了在传统负载开关设计中形成的寄生结构的示意图。在传统的负载开关设计中，为了防止闩锁，隔离环总是连接到负载开关所在电路的最高电位(例如，偏置电压源VDD)，而P型衬底PSUB总是连接到地(GND)。然而，在本发明所提供的负载开关的目标应用中，负载开关在第一输入/输出端子IO1/第二输入/输出端子IO2端的输入被配置为接收高达-40V的极限负电压。在这种情况下，将P型衬底PSUB接地并将隔离环ISO连接到偏置电压源VDD不再能提供足够的防闩锁保护。例如，当电路中的扰动产生微小的电流I1从PNP晶体管Q1的集电极流到NPN晶体管Q2的基极时，它将允许电流I2在NPN晶体管Q2的集电极和发射极之间产生。如图7所示，NPN晶体管Q2的发射极连接到配置为接收极限负电压的第一输入/输出端子IO1/第二输入/输出端子IO2。隔离环ISO连接到具有强驱动能力的电源(例如，偏置电压源VDD)。产生的电流I2能够将PNP晶体管Q1的基极拉低至低于地GND的电压电位。这样的电压电位超过了PN结(二极管D3)的开启电压阈值。结果，产生更高的电流I1。较高的电流被馈入NPN晶体管Q2的基极。虽然隔离环ISO与电源(例如，偏置电压源VDD)相关联，但馈入NPN晶体管Q2的更高的基极电流将通过NPN晶体管Q2产生更高的电流I2以形成正反馈。这种正反馈会增加流经PNP晶体管Q1和NPN晶体管Q2的电流，直至过大的功耗损坏负载开关。这种现象称为闩锁。
为了防止闩锁发生，第一肖特基二极管D1连接在P型衬底PSUB和隔离环ISO之间。第一个肖特基二极管D1用于消除PNP晶体管Q1的作用。特别地，第一肖特基二极管D1具有小于从发射极到基极(VBE)的正向电压降(例如0.6V)的正向电压降(例如0.4V)。第一肖特基二极管D1的低正向压降有助于旁路流过PNP晶体管Q1的VBE的电流，从而防止PNP晶体管Q1导通，从而中断晶闸管中的正反馈。由于中断晶闸管中的正反馈，闩锁不会发生。保护负载开关所在的集成电路不被损坏。
返回参考图1，第一肖特基二极管D1连接在P型衬底PSUB和隔离环ISO之间。第一肖特基二极管D1和寄生二极管D3并联。第一肖特基二极管D1用于旁路流过寄生二极管D3的电流，因为第一肖特基二极管D1的正向压降远小于寄生二极管D3的正向压降。寄生二极管D3形成图2所示PNP晶体管Q1的基极和发射极间的P/N结。通过旁路流过基极和发射极的电流，第一个肖特基二极管D1有助于防止发生闩锁。为了进一步减少NPN晶体管Q2意外开启时的发热，可以将隔离环ISO配置为浮动。例如，隔离环ISO与偏置电压源VDD断开。在不连接具有强电流驱动能力的电源的情况下，即使第一输入/输出端子IO1/第二输入/输出端子IO2配置为接收极限的负电压，无意中导通的NPN晶体管Q2也不会产生流过NPN晶体管Q2的大电流，从而防止NPN晶体管Q2产生过多的热量。可选地，当第一肖特基二极管D1与PNP晶体管Q1的发射极-基极结并联时，当第一输入/输出端子IO1/第二输入/输出端子IO2被配置为接收极限的负电压并且NPN晶体管Q2无意中导通时，如果P型衬底PSUB直接接地，P型衬底PSUB将能够提供通过肖特基二极管D1馈入NPN晶体管Q2的高电流。为了防止这种高电流，P型衬底PSUB通过弱连接耦合到地，从而允许P型衬底PSUB通过第一肖特基二极管D1被下拉至负电压，从而在NPN晶体管Q2无意开启时减少流经NPN晶体管Q2的电流。
图3图示了根据本申请的各种实施例的无闩锁负载开关装置的框图。无闩锁负载开关装置包括负载开关310和多个肖特基二极管320(例如，图1中所示的第一个肖特基二极管D1)。负载开关310包括第一漏极/源极区、第二漏极/源极区和第三漏极/源极区，由形成在衬底上方的隔离环(ISO)围绕。负载开关310还包括形成在第一漏极/源极区和第三漏极/源极区之间的第一栅极，以及形成在第二漏极/源极区和第三漏极/源极区之间的第二栅极。
第一漏极/源极区是两个背靠背连接的晶体管的第一漏极。第二漏极/源极区是两个背靠背连接的晶体管的第二漏极。第三漏极/源极区是两个背靠背连接的晶体管的共享源极。
第一肖特基二极管320连接在衬底和隔离环之间。第一肖特基二极管320的阳极连接到衬底。第一肖特基二极管320的阴极连接到隔离环。第一肖特基二极管320由金属触点和N型区域形成。第一肖特基二极管320被布置成防止装置进入如上文关于图2所述的闩锁操作状态。
无闩锁负载开关装置还包括连接在衬底和地之间的第二肖特基二极管320。第二肖特基二极管320的阳极连接到衬底。第二肖特基二极管320的阴极接地。无闩锁负载开关装置还包括与第二肖特基二极管320并联连接的电阻器(例如，图1中所示的电阻器R2)。电阻器是具有由衬底布局确定的寄生电阻值的寄生元件。二极管D2和寄生电阻R2的组合使得P型衬底PSUB可以弱耦合到地GND，从而允许它被下拉到接近第一输入/输出端子IO1/第二输入/输出端子IO2负电位的负电位。通过使用二极管D2，P型衬底PSUB相对于地GND的波动不能超过一个肖特基二极管压降。即使在NPN晶体管Q2无意中导通时，这种布置也会限制流过NPN晶体管Q2的电流，同时仍能防止P型衬底PSUB“反弹”到过大的正电压，这可能会导致系统的其余部分发生故障。
图4示出了根据本申请的各种实施例的图3所示的无闩锁负载开关装置的负载开关的简化截面图。负载开关包括衬底102、外延层103、隔离环、深阱106、形成在深阱106中的第一漂移层123和第二漂移层127、形成在深阱106中的体区112。负载开关还包括形成在第一漂移层123中的第一漏极/源极区124、形成在第二漂移层127中的第二漏极/源极区128、第三漏极/源极区122、第一栅极162和第二栅极164。
隔离环包括底部、第一侧壁和第二侧壁。底部是埋层104。第一侧壁包括多个彼此堆叠的第一区域132、134和136。第二侧壁包括彼此叠置的多个第二区域142、144和146。在每个侧壁中，掺杂剂的浓度从较高浓度的地方(例如，区域132)到较低浓度的地方(例如，区域136)变化。浓度的变化形成梯度。由于这个梯度，在梯度掺杂区形成了稳定的电场，从而提高了负载开关的击穿电压。
负载开关还包括多个隔离区，包括浅沟槽隔离区151、152、153和154、深沟槽隔离区182和184。这些隔离区用于防止泄漏电流在相邻半导体区之间流动。
负载开关还包括多个衬底接触区172和174。衬底接触区172、174和外延层103在衬底102和外部电路之间形成导电通道。
在一些实施例中，衬底102、外延层103、深阱106、体区112和衬底接触区172、174具有第一导电类型。埋层104、第一漂移层123、第二漂移层127、第一漏极/源极区124、第二漏极/源极区128、第三漏极/源极区122、多个第一区域132、134和136以及多个第二区域142、144和146具有第二导电类型。在一些实施例中，第一导电类型为P型，第二导电类型为N型，负载开关由两个N型晶体管组成；或者，第一导电型为N型，第二导电型为P型，负载开关由两个P型晶体管组成。
衬底102可以由诸如硅、硅锗、碳化硅等合适的半导体材料形成。根据不同的应用和设计需要，衬底102可以是N型或P型。在一些实施例中，衬底102是P型衬底，适当的P型掺杂剂例如硼等被掺杂到衬底102中；或者，衬底102是N型衬底，适当的N型掺杂剂例如磷等被掺杂到衬底102中。
负载开关形成在晶片中。负载开关可以包括多个电路，且每个电路形成在衬底上。所有衬底都连接到晶片的公共节点，在该节点形成负载开关。公共节点可以连接到接地平面。
外延层103可以实现为P型外延层。在整个描述中，外延层103可以替代地称为P-EPI层103。外延层103从衬底102生长。P型外延层103的外延生长可以通过使用任何合适的半导体制造工艺，例如化学气相沉积(CVD)等。
埋层104是N型埋层。埋层104被沉积在衬底102上以达到隔离目的。埋层104是隔离环的底部，用于防止电流流入衬底102，从而避免负载开关中的泄漏。
隔离环的第一侧壁包括区域132、134和136。区域136是高密度N型阱(HDNW)。HDNW136可以通过注入诸如磷等的N型掺杂材料来形成；或者，HDNW 136可以通过扩散工艺形成。区域134是N型阱(NW)。NW134可以通过注入诸如磷等的N型掺杂材料来形成；或者，可以通过扩散工艺形成NW134。区域132是N+区域。N+区域132形成在NW134中。N+区域可以通过注入诸如磷等的N型掺杂材料来形成。区域142、144和146的形成分别类似于区域132、134和136，因此不再详细讨论。
深阱106被隔离环围绕。深阱106是深P型阱(DPW)。DPW106可以通过注入诸如硼等的P型掺杂材料来形成。或者，DPW106可以通过扩散工艺形成。
第一漂移层123和第二漂移层127是形成在DPW106中的N型层。在一些实施例中，第一漂移层123和第二漂移层127可以掺杂有N型掺杂剂，例如磷。
体区112是P型体(PBODY)区。P型体区可以通过注入诸如硼等的P型掺杂材料来形成。或者，可以通过扩散工艺形成P型体区。
第一漏极/源极区124是形成在第一漂移层123中的N+区。在一实施例中，第一漏极/源极区124用作共享源极晶体管的第一漏极区。可以通过注入诸如磷的N型掺杂剂来形成第一漏极区。此外，在第一漏极/源极区124上方形成第一漏极触点(未示出)。第一漏极触点对应于图1中所示的第一输入/输出端子IO1。
第二漏极/源极区128是形成在第二漂移层127中的N+区。根据实施例，第二漏极/源极区128用作共享源极晶体管的第二漏极区。可以通过注入诸如磷的N型掺杂剂来形成第二漏极区。此外，在第二漏极/源极区128上方形成第二漏极触点(未示出)。第二漏极触点对应于图1中所示的第二输入/输出端子IO2。
第三漏极/源极区122是形成在体区112中的N+区。在一实施例中，第三漏极/源极区122用作共享源极晶体管的公共源极。可以通过注入诸如磷的N型掺杂剂来形成公共源极。此外，在第三漏极/源极区122上方形成源极触点(未示出)。源极触点对应于图1中所示的源极。
应当注意，P+区114形成在体区112中，并与公共源极相邻。P+区114可以通过注入诸如硼的P型掺杂剂来形成。P+区114可以接触P型体区112。为了消除体效应，P+区可以通过源极触点直接连接到公共源极。
第一栅极162形成在第一漏极/源极区124和第三漏极/源极区122之间。如图4所示，第一栅极162的第一部分在STI152上方。第一栅极162在第一漂移层123之上。第一栅极162的第三部分在DPW 106之上。第一栅极162的第四部分在体区112之上。第一栅极162可以由多晶硅、多晶硅锗、硅化镍或其他金属、金属合金等材料形成。
第二栅极164形成在第二漏极/源极区128和第三漏极/源极区122之间。如图4所示，第二栅极164的第一部分在STI153上方。第二栅极164在第二漂移层127之上。第二栅极164的第三部分在DPW 106之上。第二栅极164的第四部分在体区112之上。第二栅极164可以由多晶硅、多晶硅锗、硅化镍或其他金属、金属合金等材料形成。
返回参考图1，图1中所示的二极管D3形成在衬底102和隔离环之间。具体地，二极管D3的阳极形成在衬底102中，二极管D3的阴极形成在埋层104中。图1所示的二极管D4形成在埋层104和深阱106之间。具体地，二极管D4的阳极形成在深阱106中，二极管D4的阴极形成在埋层104中。
图1所示的二极管D5形成在体区112和第一漂移层123之间。具体地，二极管D5的阳极形成在体区112中，二极管D5的阴极形成在第一漂移层123中。图1所示的二极管D6形成在体区112和第二漂移层127之间。具体地，二极管D6的阳极形成在体区112中。二极管D6的阴极形成在第二漂移层127中。
应当注意，虽然图4示出了包括两个背靠背连接的晶体管的负载开关，但是本申请的各种实施例也适用于单个晶体管。例如，一个晶体管由多个晶体管单元形成。N+区124是第一晶体管单元的漏极，N+区128是第二晶体管单元的漏极，第一晶体管单元的漏极通过合适的互连器件连接到第二晶体管单元的漏极。同样，栅极162是第一晶体管单元的栅极，栅极164是第二晶体管单元的栅极，第一晶体管单元的栅极通过合适的互连器件连接到第二晶体管单元的栅极。无闩锁结构(第一肖特基二极管D1、第二肖特基二极管D2和电阻器R2)有助于防止单个晶体管进入闩锁操作状态，如上文关于图2所述的内容。
图5示出了根据本申请的各种实施例的图3中所示的无闩锁负载开关装置的肖特基二极管的简化截面图。回到图1，第一肖特基二极管D1和第二肖特基二极管D2可以由图5所示的半导体结构形成。衬底102、外延层103和埋层104与图4所示的类似，因此下文不再讨论。
如图5所示，在埋层104上方和两个深沟槽隔离区282和284之间形成高密度N型阱(HDNW)。第一P型阱216和第二P型阱226形成在HDNW210中。金属触点形成在P型阱和HDNW210之上。如图5所示，金属触点包括下部264和上部273。金属触点与HDNW210接触。金属触点的边缘部分与P型阱216和226接触。图5进一步显示金属触点连接到接触插塞263和265。金属触点和N型区域(例如，HDNW210)形成金属-半导体结。肖特基二极管是基于金属-半导体结形成的。P型阱216和226有助于形成肖特基二极管的金属-半导体结。
图5进一步示出了HDNW210通过N型阱214、N+区234和接触插塞262耦合到第一阴极端子272。HDNW210通过N耦合到第二阴极端子276。N-型阱224、N+区244和接触插塞266。
金属触点的上部273用作肖特基二极管的阳极端子。当图1中所示的第一肖特基二极管D1被实施为图5中所示的肖特基二极管时，第一阴极端子272和第二阴极端子276耦合在一起并且耦合到隔离环。肖特基二极管的阳极(例如，金属触点273)耦合到衬底。
图5进一步示出了衬底102通过外延层103、P型阱212、P+区232和接触插塞261耦合到第一衬底接触端子271。衬底102还穿过外延层103、P型阱222、P+区242和接触插塞267耦合到第二衬底接触端子277。
图5进一步示出了多个STI区域251、252、253、254、255和256。STI区域用于防止出现在相邻半导体区域之间流动的泄漏电流。
图6示出了根据本申请的各种实施例的用于形成图1中所示的负载开关的方法的流程图。图6所示的这个流程图仅仅是一个例子，它不应过度限制权利要求的范围。本领域普通技术人员将认识到许多变化、替代和修改。例如，可以添加、移除、替换、重新排列和重复图6中所示的各种步骤。
再参考图1，负载开关包括两个背靠背连接的N型晶体管。第一晶体管包括第一漏极、第一栅极和第一源极。第二晶体管包括第二漏极、第二栅极和第二源极。这两个N型晶体管的源极直接相连，如图1所示。第一晶体管的第一漏极可以连接到无线充电接收器线圈的一端。第二晶体管的第二漏极可以连接到接收器电路。负载开关能够实现无线充电接收器线圈和接收器电路之间的双向电流阻断。负载开关可以通过以下步骤制造。
在步骤602，在具有第一导电类型的衬底上生长具有第一导电类型的外延层。
在步骤604，在外延层中形成具有第二导电类型的隔离环，隔离环包括底部、第一侧壁以及第二侧壁。底部是埋层(例如，图4中所示的层104)。第一侧壁包括多个第一区域(例如，图4中所示的区域132、134和136)。第二侧壁包括多个第二区域(例如，图4中所示的区域142、144和146)。
在一些实施例中，第一导电类型是P型，第二导电类型是N型。
在步骤606，对于单个晶体管，在隔离环中形成第一漏极/源极区和第二漏极/源极区。或者，对于负载开关，第一漏极/源极区(例如，图4中所示的区域124)、第二漏极/源极区(例如，图4中所示的区域128)和第三漏极/源极区(例如，图4所示的区域122)形成在隔离环中。
在步骤608，在衬底上方形成第一肖特基二极管(例如，图5中所示的肖特基二极管)。第一肖特基二极管的阳极是通过第一半导体互连器件连接到衬底的金属触点。第一肖特基二极管的阴极是通过第二半导体互连器件连接到隔离环的N型区域。
返回参考图4，该方法还包括在隔离环内形成具有第一导电类型的深阱，在深阱中形成具有第二导电类型的第一漂移层，以及形成具有第二导电类型的第二漂移层。在深阱中形成第一导电类型的体区，注入第二导电类型的离子，在第一漂移层中形成第一漏极/源极区和第二漏极/源极区。第二漂移层，分别注入第二导电类型的离子，在体区形成第三漏源区，在第一漏源区和第三漏源区之间形成第一栅极，形成第二栅极在第二漏极/源极区和第三漏极/源极区之间。
返回参考图5，该方法还包括在埋层上方形成N型阱，在N型阱中形成多个P型阱，以及在P型阱上方形成金属触点，其中金属触点的中央部分与N型阱接触，而金属触点的边缘部分与多个P型阱接触。
虽然已经详细描述了本发明的实施例及其优点，但是应当理解，在不脱离由所附权利要求限定的本发明的精神和范围的情况下，可以在本文中进行各种改变、替换和变更。
此外，本申请的范围不旨在限于说明书中描述的过程、机器、制造、物质组成、手段、方法和步骤的特定实施例。作为本领域的普通技术人员，从本发明的公开内容中将容易理解目前存在的或以后将开发的执行基本相同功能的过程、机器、制造、物质组合物、手段、方法或步骤或者实现与根据本发明可以利用的在此描述的相应实施例基本相同的结果。因此，所附权利要求旨在将这样的过程、机器、制造、物质组成、手段、方法或步骤包括在它们的范围内。

Claims (20)

1.一种无闩锁负载开关装置，其特征在于，包括：
第一漏极/源极区和第二漏极/源极区，所述第一漏极/源极区和所述第二漏极/源极区被形成在衬底上方的隔离环围绕，所述隔离环被配置为浮动的；
和第一二极管，所述第一二极管连接在所述衬底与所述隔离环之间，其中，所述第一二极管为肖特基二极管。
2.根据权利要求1所述的装置，其特征在于，还包括：
第三漏极/源极区，所述第三漏极/源极区被所述隔离环围绕；
第一栅极，所述第一栅极形成于所述第一漏极/源极区和所述第二漏极/源极区之间；
第二栅极，所述第二栅极形成于所述第二漏极/源极区与所述第三漏极/源极区之间；
其中，所述第一漏极/源极区、所述第二漏极/源极区、所述第三漏极/源极区、所述第一栅极和所述第二栅极形成两个背靠背连接的晶体管，所述第一漏极/源极区为背靠背连接的两个晶体管的第一漏极，所述第二漏极/源极区为背靠背连接的两个晶体管的公共源极，所述第三漏极/源极区是背靠背连接的两个晶体管的第二漏极。
3.根据权利要求1所述的装置，其特征在于，还包括：
第二二极管以及与所述第二二极管并联的电阻器，所述第二二极管连接在衬底与地之间；
其中，所述第二二极管为肖特基二极管。
4.根据权利要求3所述的装置，其特征在于，所述第二二极管的阳极连接于所述衬底，所述第二二极管的阴极接地。
5.根据权利要求3所述的装置，其特征在于，所述电阻器是寄生元件，所述电阻器的寄生电阻值由所述衬底的布局决定。
6.根据权利要求1所述的装置，其特征在于，所述第一二极管的阳极与所述衬底连接，所述第一二极管的阴极与所述隔离环连接。
7.根据权利要求1所述的装置，其特征在于，还包括：
位于具有第一导电类型的衬底上方，且具有所述第一导电类型的外延层；
具有第二导电类型的埋层、具有所述第二导电类型的多个第一区域和具有所述第二导电类型的多个第二区域，其中所述埋层、所述多个第一区域和所述多个第二区域形成隔离环；
在所述埋层上方和所述隔离环内形成的具有所述第一导电类型的深阱；
在所述深阱中具有所述第二导电类型的第一漂移层，其中，所述第一漏极/源极区在所述第一漂移层中形成；
在所述深阱中具有所述第二导电类型的第二漂移层，其中，第三漏极/源极区在所述第二漂移层中形成；
在所述深阱中，且在所述第一漂移层和所述第二漂移层之间形成的具有所述第一导电类型的体区，其中，所述第二漏极/源极区在所述体区中形成。
8.根据权利要求7所述的装置，其特征在于，所述第一导电类型为P型，所述第二导电类型为N型。
9.根据权利要求7所述的装置，其特征在于，还包括：
第三二极管，所述第三二极管形成于所述衬底与所述埋层之间，所述第三二极管的阳极连接所述衬底，第三二极管的阴极连接所述埋层；
第四二极管，所述第四二极管形成于所述埋层与所述深阱之间，所述第四二极管的阳极连接所述深阱，所述第四二极管的阴极连接所述埋层；
第五二极管，所述第五二极管形成于所述体区与所述第一漂移层之间，所述第五二极管的阳极连接所述体区，所述第五二极管的阴极连接所述第一漂移层；
第六二极管，所述第六二极管形成于所述体区与所述第二漂移层之间，所述第六二极管的阳极连接所述体区，所述第六二极管的阴极连接所述第二漂移层。
10.根据权利要求1所述的装置，其特征在于，所述肖特基二极管由金属触点和N型区域构成。
11.根据权利要求10所述的装置，其特征在于，配置所述肖特基二极管以防止设备进入闩锁操作状态。
12.一种形成负载开关的方法，其特征在于，包括：
在具有第一导电类型的衬底上生长具有所述第一导电类型的外延层；
在所述外延层中形成具有第二导电类型的隔离环，所述隔离环包括埋层、多个第一区域以及多个第二区域；
在所述隔离环中形成第一漏极/源极区和第二漏极/源极区；
在衬底上方形成第一肖特基二极管，其中，所述第一肖特基二极管的阳极为与所述衬底连接的金属触点，所述第一肖特基二极管的阴极为与所述隔离环连接的具有所述第二导电类型的区域。
13.根据权利要求12所述的方法，其特征在于，还包括：
所述隔离环中的第三漏极/源极区，其中，所述第一漏极/源极区、所述第二漏极/源极区、所述第三漏极/源极区形成共享源极的晶体管；
所述第一导电类型为P型，所述第二导电类型为N型。
14.根据权利要求13所述的方法，其特征在于，还包括：
在所述隔离环内形成具有所述第一导电类型的深阱；
在所述深阱中形成具有所述第二导电类型的第一漂移层；
在所述深阱中形成具有所述第二导电类型的第二漂移层；
在所述深阱中形成具有所述第一导电类型的体区；
在所述第一漂移层和所述第二漂移层中分别注入具有所述第二导电类型的离子，以形成所述第一漏极/源极区和所述第三漏极/源极区；
在所述体区中注入具有所述第二导电类型的离子，以形成所述第二漏极/源极区；
在所述第一漏极/源极区与所述第二漏极/源极区之间形成第一栅极；
在所述第二漏极/源极区和所述第三漏极/源极区之间形成第二栅极。
15.根据权利要求14所述的方法，其特征在于，还包括：
在所述埋层上形成具有所述第二导电类型的区域；
在具有所述第二导电类型的区域上方形成所述金属触点。
16.根据权利要求12所述的方法，其特征在于，还包括：
在所述衬底上方形成第二肖特基二极管，其中，所述第二肖特基二极管的阳极为与所述衬底连接的金属触点，所述第二肖特基二极管的阴极为接地的具有所述第二导电类型的区域。
17.一种负载开关，其特征在于，包括：
第一晶体管和第二晶体管，所述第二晶体管背靠背连接到所述第一晶体管，其中，所述第一晶体管的漏极、所述第二晶体管的漏极和共享源极形成在衬底上方和隔离环内，所述隔离环被配置为浮动的；
第一肖特基二极管，所述第一肖特基二极管连接在所述衬底和所述隔离环之间。
18.根据权利要求17所述的负载开关，其特征在于，所述隔离环包括：
具有N型埋层的底部、包括多个第一N型区域的第一侧壁和包括多个第二N型区域的第二侧壁。
19.根据权利要求17所述的负载开关，其特征在于，所述第一肖特基二极管由金属触点和N型区域形成；
所述第一肖特基二极管的阳极与所述衬底连接，所述第一肖特基二极管的阴极与所述隔离环连接。
20.根据权利要求17所述的负载开关，其特征在于，还包括：
连接在所述衬底和地之间的第二肖特基二极管，其中，所述第二肖特基二极管的阳极与所述衬底连接，所述第二肖特基二极管的阴极接地；
电阻器，所述电阻器与所述第二肖特基二极管并联连接，所述电阻器为寄生元件，所述电阻器的寄生电阻值由所述衬底的布局决定。
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