CN115701565A

CN115701565A - Abrupt waveform generation control system

Info

Publication number: CN115701565A
Application number: CN202110879286.5A
Authority: CN
Inventors: 唐向前; 安旸; 郝东; 王文宇; 叶霞; 单欣岩; 陆兴华
Original assignee: Institute of Physics of CAS
Current assignee: Institute of Physics of CAS
Priority date: 2021-08-02
Filing date: 2021-08-02
Publication date: 2023-02-10

Abstract

There is provided an abrupt waveform generation control system including: a first transistor switch including a first terminal for receiving a first waveform, a second terminal connected to a load, and a control terminal; a second transistor switch including a first terminal connected to the load, a second terminal for receiving a second waveform, and a control terminal; a driver comprising, a first control input and a second control input for receiving a first digital signal and a second digital signal, respectively; a first power input terminal and a second power input terminal connected to the first power supply and the second power supply, respectively, and a first output terminal and a second output terminal connected to the control terminal of the first switch and the control terminal of the second switch, respectively; and the driver controls the first transistor switch and the second transistor switch to be alternately conducted according to the first digital signal and the second digital signal so as to switch the waveform output to the load between the first waveform and the second waveform.

Description

Abrupt waveform generation control system

Technical Field

The invention relates to the field of electronic circuits, in particular to a sudden change waveform generation control system.

Background

The voltage waveform generation system is widely applied to the fields of automation control, signal excitation, detection and the like. Precision manipulation systems based on voltage driving often require voltage signals that can be precisely regulated to achieve free operation. For example, the drive of scanning probe microscope piezoceramic electric motors relies on an abrupt voltage waveform, with voltage amplitudes on the order of hundreds of volts. The time for the voltage to change rapidly from one high voltage value to another voltage value is controlled within 1 mus, otherwise the driving efficiency of the piezoelectric ceramic is greatly reduced, and the shorter the time, the higher the driving efficiency. In addition, since the piezoelectric ceramic has a withstand voltage limit and is damaged when a high voltage is exceeded, it is a desirable embodiment if the high voltage waveform can be rapidly switched between different polarities. At present, the sudden change voltage waveform generator on the market is high in cost and complex to use, and the sudden change time is about hundreds of nanoseconds.

Disclosure of Invention

Based on the above-mentioned drawbacks of the prior art, the present invention provides an abrupt waveform generation control system, which includes:

a first transistor switch including a first terminal for receiving a first waveform, a second terminal connected to a load, and a control terminal;

a second transistor switch including a first terminal connected to the load, a second terminal for receiving a second waveform, and a control terminal;

a driver comprising, a first control input and a second control input for receiving a first digital signal and a second digital signal, respectively; a first power input terminal and a second power input terminal connected to a first power supply and a second power supply, respectively, and a first output terminal and a second output terminal connected to a control terminal of the first switch and a control terminal of the second switch, respectively; and

the driver controls the first transistor switch and the second transistor switch to be alternately conducted according to the first digital signal and the second digital signal, so that the waveform output to the load is switched between the first waveform and the second waveform.

Preferably, the first waveform is opposite to the second waveform.

Preferably, the driver is a dual channel isolated gate driver, and the first and second power supplies are isolated dc power supplies.

Preferably, the first transistor switch and the second transistor switch are field effect transistors or triodes.

Preferably, the method further comprises the following steps:

a waveform generation circuit for generating a low voltage waveform;

an amplification circuit to amplify the low voltage waveform to generate the first waveform and the second waveform.

Preferably, the waveform generation circuit is a field programmable gate array.

Preferably, an analog output terminal of the field programmable gate array is used for outputting the low voltage waveform, and a digital output terminal of the field programmable gate array is used for outputting the first digital signal and the second digital signal.

Preferably, the amplifying circuit comprises a first operational amplifier, one end of a first resistor is connected to a first analog output end of the field programmable logic gate array, and the other end of the first resistor is connected to an inverting input end of the first operational amplifier;

the first capacitor is connected with the second resistor in parallel, one end of the first capacitor is connected to the inverting input end of the first operational amplifier, and the other end of the first capacitor is connected to the output end of the first operational amplifier;

one end of a third resistor is connected to a second analog output end of the field programmable logic gate array, the other end of the third resistor is connected to a second capacitor and a fourth resistor, the other end of the second capacitor is grounded, and the other end of the fourth resistor is connected to an inverting input end of the first operational amplifier;

the non-inverting input end of the first operational amplifier is grounded, and the output end of the first operational amplifier outputs the first waveform.

Preferably, the amplifying circuit comprises a second operational amplifier, one end of a fifth resistor is connected to the output end of the first operational amplifier, and the other end of the fifth resistor is connected to the inverting input end of the second operational amplifier; the third capacitor is connected with the sixth resistor in parallel, one end of the third capacitor is connected to the inverting input end of the second operational amplifier, and the other end of the third capacitor is connected to the output end of the second operational amplifier; the non-inverting input end of the second operational amplifier is grounded, and the output end of the second operational amplifier outputs the second waveform.

Preferably, the first analog output terminal outputs a low voltage waveform, and the second analog output terminal outputs a fixed voltage.

According to the abrupt waveform generation control system, the two transistor switches are used as the switches of the two waveforms, the driver drives the two transistor switches to be alternately conducted, so that the output voltage waveform is rapidly switched between the two waveforms, and the waveform switching time can reach about 50 nanoseconds.

The sudden change waveform generation control system can also generate high-precision low-voltage waveforms by using the FPGA, obtain high-voltage waveforms by using the amplifying circuit and realize the sudden change voltage waveforms by using the high-speed waveform switching circuit. The low-voltage waveform and the control sequence can be controlled by programming, so that the system has strong flexibility and expandability.

Drawings

FIG. 1 is a schematic block diagram of an abrupt waveform generation control system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of programming to achieve the generation and output of waveform data;

FIG. 3 is a schematic diagram of an amplification circuit according to one embodiment of the invention;

FIG. 4 is a schematic diagram of the output of a waveform switching circuit according to one embodiment of the present invention;

FIG. 5 is a schematic diagram of a waveform switching circuit according to one embodiment of the present invention;

FIG. 6 is a schematic diagram of a waveform switching circuit according to another embodiment of the present invention;

FIG. 7A is a voltage switching curve measured with a capacitive load of 1nF capacitance;

FIG. 7B is a plot of the voltage switching measured after the addition of a 20 ohm current limiting resistor;

FIG. 7C is a voltage switching curve measured after adding a 200 ohm current limiting resistor;

FIG. 8A shows a waveform diagram of a three-way fast switching channel during fast switching;

fig. 8B shows a waveform diagram of three fast switching channels when high voltage switching is performed at a given interval of 10 microseconds per channel.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail by way of specific embodiments with reference to the accompanying drawings. It should be noted that the examples given herein are for illustration only and do not limit the scope of the invention.

Fig. 1 is a schematic structural diagram of an abrupt waveform generation control system according to an embodiment of the present invention. The abrupt-change waveform generation control system includes a waveform generation circuit 101, an amplification circuit 102, and a waveform switching circuit 103. The waveform generating circuit 101 is used for generating a low-voltage waveform; the amplifying circuit 102 is configured to amplify the low-voltage waveform generated by the waveform generating circuit 101 to generate a high-voltage waveform; the waveform switching circuit 103 is used to generate a high voltage waveform that rapidly switches between the first high voltage waveform and the second high voltage waveform. Here, the waveform generation circuit 101 and the amplification circuit 102 may be omitted, and the first high-voltage waveform and the second high-voltage waveform may be directly supplied by other means. In the present invention, the ranges of the high pressure and the low pressure may not be limited, but for the sake of understanding, the low pressure may be defined as-10V or more and +10V or less, and the high pressure as +10V or less.

The waveform generation circuit 101 is preferably able to communicate with the outside world, generating the corresponding waveform by program control. The waveform generating circuit 101 may be, for example, a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), an application specific integrated circuit, a single chip microcomputer, or the like. For convenience of description and understanding, the waveform generation circuit of the present invention is introduced by using an FPGA board of the NI corporation, which is USB7856R, but the present invention is not limited thereto, and those skilled in the art can easily replace other waveform generation circuits. The FPGA board is provided with 32 digital signal output ports, and the output frequency can reach 80MHz;8 analog signal output ports, the highest update rate is 1MSa/s,16 bit precision, and the output level can reach +/-10V. The maximum response speed that the digital signal control circuit can reach is 12.5ns, the time control precision of the output low-voltage analog signal waveform is 1 mu s, and the voltage control precision is 0.3mV.

The FPGA can be programmed by using a graphic language LabVIEW, and other languages capable of communicating with the FPGA, such as C language, can also be used. In the LabVIEW program, waveforms of arbitrary shapes can be freely programmed and then stored in the memory of the FPGA. When the trigger generates the waveform, only the waveform data defined in the memory needs to be output through the analog output channel. As shown in FIG. 2, a programmed sinusoidal waveform of amplitude 1V, period 100 μ s, and duty cycle 0.5 may be stored in memory banks 1-6, which may be output as needed through analog outputs AO0-AO7, either individually or simultaneously.

Fig. 3 is a schematic diagram of an amplification circuit according to one embodiment of the invention. The resistors R1, R2, and R3 are connected in parallel, one end of each resistor is connected to the analog output AO0 of the FPGA 301, the other end of each resistor is connected to the selection switch 304, and the other end of the selection switch 304 is connected to the inverting input terminal of the operational amplifier 302. The capacitor C2 is connected in parallel with the resistor R6, and has one end connected to the inverting input terminal of the operational amplifier 302 and the other end connected to the output terminal of the operational amplifier 302. One end of the resistor R4 is connected to the analog output end AO1 of the FPGA 301, the other end is connected to the capacitor C1 and the resistor R5, the other end of the capacitor C1 is grounded, and the other end of the resistor R5 is connected to the inverting input end of the operational amplifier 302. The non-inverting input terminal of the operational amplifier 302 is grounded, and the output terminal outputs a first high voltage waveform HV1. One end of the resistor R7 is connected to the output end of the operational amplifier 302, and the other end is connected to the inverting input end of the operational amplifier 303. The capacitor C3 is connected in parallel to the resistor R8, and has one end connected to the inverting input terminal of the operational amplifier 303 and the other end connected to the output terminal of the operational amplifier 303. The non-inverting input terminal of the operational amplifier 303 is grounded, and the output terminal outputs the second high voltage waveform HV2.

Assuming that the output voltage of the analog output terminal AO0 is V1 and the output voltage of the analog output terminal AO1 is V2, the output of the operational amplifier 302 is

Output of operational amplifier 303

For example, if R6 is set to 100K Ω; r4 and R5 are 5K omega; r1, R2 and R3 are respectively 10K omega, 100K omega and 1M omega, when V2 is 0, the corresponding amplification factor of the operational amplifier 302 is

I.e., -10, -1, -0.1 times, respectively, so that R1, R2, R3 can be used to control the magnification. C1 C2 is used for filtering, where C1 may be 1nF and C2 may be 100pF. Thus, the output bandwidth may be limited to 100kHz (R6 =100k Ω, C2=100 pF). Preferably, R6 is ten times the sum of R4 and R5, which can be used as a constant magnification voltage waveform.

Preferably, the analog output AO0 may output a voltage waveform, and the analog output AO1 outputs a fixed voltage (which may also be referred to as a dc bias). The output voltage of the analog output terminal AO1 may be 0, and the operational amplifier 302 amplifies the output voltage waveform of the analog output terminal AO0 and outputs the amplified output voltage waveform as the first high voltage waveform HV1. The analog output terminal AO1 can output a fixed voltage (non-zero voltage), which is equivalent to the situation that an operational amplifier 302 superposes a bias voltage on the basis of amplifying the output voltage waveform of the analog output terminal AO0, namely superposes the bias voltage

I.e. the bias voltage is superimposed on the basis of the first high voltage waveform HV1. Thus, in this embodiment, two analog output ports AO0, AO1 of the FPGA 301 may be utilized to output two high voltage waveforms, i.e., an unbiased high voltage waveform and a biased high voltage waveform. The operational amplifier 303 is used for inverting and amplifying the first high voltage waveform HV1 with an amplification factor of

Preferably, R8 is equal to R7 such that the second high voltage waveform HV2 is opposite to the first high voltage waveform HV1.

The amplifying circuit in fig. 3 can amplify the low-voltage signal output by the FPGA by using the high-voltage operational amplifier, so that the voltage fluctuation range can be changed from low voltage (for example, ± 10V) to high voltage (for example, ± 200V). The same configuration can also be applied to the other analog output ports (AO 2-AO 7) of the FPGA 301. However, the amplification circuit can only give a slowly varying high voltage waveform, since the slew rate of the high voltage op amp is often only a few volts per microsecond. For capacitive load, assuming a capacitance value of 1nF and a voltage variation of 100V, it takes several microseconds to complete the voltage variation process of 100V.

Fig. 4 is a schematic diagram of the output of a waveform switching circuit according to one embodiment of the present invention. As shown in fig. 4, the first high voltage waveform HV1 and the second high voltage waveform HV2 are opposite, and after passing through the high voltage fast waveform switching circuit of nanosecond order, the high voltage waveform HV3 that switches fast between the first high voltage waveform HV1 and the second high voltage waveform HV2 is generated.

Fig. 5 is a schematic diagram of a waveform switching circuit according to one embodiment of the invention. The waveform switching circuit includes a driver 501, a power supply 502, a power supply 503, a transistor switch 507, and a transistor switch 508. The driver 501 preferably includes two channels, which may be a single driver with two channels or two drivers to drive two transistor switches. The first channel of the driver 501 comprises a first control input INA for receiving a digital signal; a first power input terminal VDDA connected to the power supply 502, the power supply 502 serving as a bias power supply for the first channel to provide power for driving the first channel; and a first output terminal OUTA connected to the control terminal of the transistor switch 507. The first channel outputs a driving current from the first output terminal OUTA to the control terminal of the transistor switch 507 under the control of the digital signal received by the first control input terminal INA, so as to control the transistor switch 507 to be turned on. At this time, the first high voltage waveform HV1 is output to the load 506. The second channel comprises a second control input INB for receiving the digital signal; a second power input VDDB connected to a power supply 503, the power supply 503 serving as a bias power supply for the second channel to supply power for driving the second channel; and a second output terminal OUTB connected to the control terminal of the transistor switch 508. The second channel outputs a driving current from the second output node OUTB to the transistor switch 508 under the control of the digital signal received by the second control input node INB, so as to turn on the transistor switch 508. At this time, the second high voltage waveform HV2 is output to the load 506. Wherein the digital signal may be provided by a digital output of the FPGA, i.e. the first control input INA and the second control input INB of the driver 501 may be connected to the digital output of the FPGA. Wherein, the timing control of the digital signal can be realized by programming. Driver 501 may be a gate driver, and preferably may be an isolated gate driver, to facilitate fast switching of higher voltage waveforms. The isolated gate driver may be, for example, UCC21520. The power supplies 502 and 503 may preferably be isolated dc power supplies, such as RM0512.

The transistor switch 507 has a first terminal for receiving the first high voltage waveform HV1, and a second terminal connected to the load 506 for outputting the first high voltage waveform HV1 to the load 506 when turned on. The transistor switch 508 has a first terminal connected to the load 506, a second terminal for receiving the second high voltage waveform HV2, and the transistor switch 508 for outputting the second high voltage waveform HV2 to the load 506 when turned on. The transistor switches 507 and 508 may be current driven switches, which may be Field Effect Transistor (FET) switches, such as Junction Field Effect Transistors (JFETs) and metal-oxide semiconductor field effect transistors (MOS-FETs); but also a triode, etc. When the transistor switch 507/508 is a field effect transistor, the first terminal thereof may also be referred to as a drain, the second terminal thereof may also be referred to as a source, and the control terminal thereof may also be referred to as a gate.

The transistor switch has the advantage of high switching speed, and can improve the speed of waveform switching. The switching speed of the transistor is also related to the drive current, so it is preferable that the driver 501 can output a larger drive current. The first end of the transistor switch 507 may be connected to an energy storage capacitor 504, which plays a role of energy storage and has a size of 0.1 μ F. The second terminal of the transistor switch 508 may also be connected to an energy storage capacitor 505, which plays a role of energy storage and has a size of 0.1 μ F.

It should be noted that the waveform switching circuit in fig. 5 can be applied not only to rapidly switch between two high-voltage waveforms, but also to switch of low-voltage waveforms.

Fig. 6 is a schematic diagram of a waveform switching circuit according to another embodiment of the invention. As shown, driver 601 is a dual channel isolated gate driver UCC21520,

power supplies

602 and 603 are isolated dc-to-dc power supplies RM0512, transistor switches Q3 and Q4 are fet switches IRF840, and a high voltage operational amplifier in the amplifier circuit is PA88. In practical application, other components with similar functions can be selected according to requirements. The digital signal is transmitted to the input of the driver 601 through the channels DO2 and DO 3. The first high voltage waveform is a positive high voltage waveform + HV, and the second high voltage waveform is a negative high voltage waveform-HV.

As shown in fig. 6, the resistor and capacitor at the input end of the driver 601 basically function as current limiting and filtering, for example, the capacitors C28, C29, C31, C33, and the resistors R25, R27, R29, and the capacitance and resistance values can be selected as required. The role of the power supplies 602 and 603 is to convert a 5V common ground supply into a 12V isolated dc supply relative to its own OUT-. As shown in fig. 6, the output cathode OUT-of the power supply 602 is connected to the source of the fet Q4, the output anode OUT + is connected to VDDB of the driver 601 for power supply after passing through the filtering and protection diode D23, and the diode D23 is used for protecting the power supply 602. Both the input and output terminals of the power supply 602 have standard pi circuits for filtering, such as inductor L8 and capacitors C37, C38; and an inductance L7 and capacitances C35, C36. The configuration of the power supply 603 is similar to that of the power supply 602, and is not described in detail here. C30 and C34 are bootstrap capacitors that can boost VDDA or VDDB of driver 601 with respect to VSSA or VSSB, but keep the voltage drops in absolute value. D18, D19, D22 and D24 play a role in stabilizing voltage; r23, R24, R26 and R28 are current limiting resistors; d16 and D20 are for increasing the current in the circuit when the voltage drops. In practical application, suitable devices can be selected according to requirements.

The first output terminal OUTA of the driver 601 is connected to the gate of Q3, and the second output terminal OUTB is connected to the gate of Q4. The drain of Q3 is for receiving a positive high voltage waveform + HV and the source is connected to a load 604. The drain of Q4 is connected to load 604 and the source is used to receive the negative high voltage waveform-HV.

The control program controls the driver to work through the digital signal, and the output voltage is enabled to change from one waveform to another waveform. For example, when the channel DO2 in fig. 6 is applied with a high level and the channel DO3 is applied with a low level, the fet Q3 is turned on and the fet Q4 is turned off, and the output waveform is a positive high voltage waveform + HV; if the channel DO2 is low and DO3 is high, the fet Q3 is turned off, Q4 is turned on, and the output voltage rapidly changes from a positive high voltage waveform + HV to a negative high voltage waveform-HV. The digital signal may be provided by a digital output of the FPGA.

In the waveform switching circuit of the above embodiment, two field effect transistors Q3 and Q4 are used as switches of two polarity high-voltage waveforms, and a bipolar insulated gate driver is used as a transistor switch for driving. When the capacitive load is at 1nF, the voltage switching time is less than 100ns. Actual circuit testing as shown in fig. 7A-7C, the voltage switch from +100V to-100V only takes about 50ns. The capacitance of a single capacitive load in most application scenarios tends to be less than 1nF. The voltage ripple noise in the figure arises from coupling of capacitance and parasitic inductance in the circuit. By adding a current limiting resistor, the voltage ripple can be reduced. Fig. 7A is the voltage switching curve measured with only one 1nF capacitor, fig. 7B is the voltage switching curve measured after adding a 20 ohm current limiting resistor, and fig. 7C is the voltage switching curve measured after adding a 200 ohm current limiting resistor, with much reduced oscillation amplitude after current limiting, but without increased time for voltage change.

In this embodiment, multiple (e.g. 3) fast switching channels that can be controlled independently can be configured, that is, the same first high voltage waveform HV1 and second high voltage waveform HV2 can be connected to multiple (e.g. 3) fast switching circuits connected in parallel, and the output of the fast switching circuits is controlled by a digital signal at the input terminal of the driver. In an actual application scene, a plurality of piezoelectric ceramics are often used, and each piezoelectric ceramic is controlled independently, so that the plurality of piezoelectric ceramics operate more stably and efficiently at the same time, and the flexibility is higher. Fig. 8A shows the waveform of the three-way fast switching channel during fast switching, and fig. 8B shows the waveform of the three-way fast switching channel during high voltage switching given a 10 microsecond interval between each channel. By copying the switching circuit and simultaneously realizing independent control of different paths at different moments through programming, the sub-waveform generation is realized by only using two FPGA analog output channels, and meanwhile, a plurality of piezoelectric ceramics can be independently controlled, thereby greatly increasing the expansibility of the system.

According to the abrupt waveform generation control system, the two transistor switches are used as the switches of the two high-voltage waveforms, the driver drives the two transistor switches to be alternately conducted, so that the output voltage waveform is rapidly switched between the two high-voltage waveforms, and the waveform switching time can reach about 50 nanoseconds.

The two high voltage waveforms may be provided externally or may be generated by the waveform generation circuit and the amplification circuit of the present invention. According to one embodiment of the abrupt change waveform generation control system, high-precision low-voltage waveforms can be generated by using an FPGA, high-voltage waveforms are obtained by an amplifying circuit, and abrupt change voltage waveforms are realized by a high-speed waveform switching circuit. The low-voltage waveform and the control sequence can be controlled by programming, so that the system has strong flexibility and expandability.

Although the present invention has been described by way of preferred embodiments, the present invention is not limited to the embodiments described herein, and various changes and modifications may be made without departing from the scope of the present invention.

Claims

1. An abrupt waveform generation control system, comprising:

2. The abrupt waveform generation control system of claim 1, wherein the first waveform is opposite the second waveform.

3. The abrupt waveform generation control system of claim 1, wherein the driver is a dual channel isolated gate driver, and the first and second power supplies are isolated dc power supplies.

4. The abrupt waveform generation control system of claim 1, wherein the first transistor switch and the second transistor switch are field effect transistors or triodes.

5. The abrupt waveform generation control system of any one of claims 1-4, further comprising:

a waveform generation circuit for generating a low voltage waveform;

6. The abrupt waveform generation control system of claim 5, wherein the waveform generation circuit is a field programmable gate array.

7. The burst waveform generation control system of claim 6, wherein an analog output of the field programmable gate array is configured to output the low voltage waveform and a digital output of the field programmable gate array is configured to output the first digital signal and the second digital signal.

8. The burst waveform generation control system according to claim 6, wherein the amplification circuit includes a first operational amplifier, one end of a first resistor is connected to a first analog output terminal of the field programmable gate array, and the other end is connected to an inverting input terminal of the first operational amplifier;

one end of a third resistor is connected to a second analog output end of the field programmable logic gate array, the other end of the third resistor is connected to a second capacitor and a fourth resistor, the other end of the second capacitor is grounded, and the other end of the fourth resistor is connected to the inverting input end of the first operational amplifier;

9. The abrupt waveform generation control system according to claim 8, wherein the amplification circuit includes a second operational amplifier, and a fifth resistor has one end connected to an output terminal of the first operational amplifier and the other end connected to an inverting input terminal of the second operational amplifier; the third capacitor is connected with the sixth resistor in parallel, one end of the third capacitor is connected to the inverting input end of the second operational amplifier, and the other end of the third capacitor is connected to the output end of the second operational amplifier; the non-inverting input end of the second operational amplifier is grounded, and the output end of the second operational amplifier outputs the second waveform.

10. The burst waveform generation control system of claim 8 wherein the first analog output outputs a low voltage waveform and the second analog output outputs a fixed voltage.