CN115701241A - Display device - Google Patents

Abstract

The present disclosure relates to a display device, and the display device includes: a first light emitting element, a second light emitting element, and a third light emitting element which are respectively provided on a substrate and emit light of different colors; a first insulating layer disposed on the first, second, and third light emitting elements and including at least one opening; and a second insulating layer disposed on the first insulating layer and in the at least one opening, wherein a refractive index of the second insulating layer is higher than a refractive index of the first insulating layer, and the at least one opening overlaps with at least one of the first light emitting element, the second light emitting element, and the third light emitting element in a plan view and does not overlap with at least another one of the first light emitting element, the second light emitting element, and the third light emitting element in a plan view.

Description

Display device

Cross Reference to Related Applications

This application claims priority and benefit of korean patent application No. 10-2021-0096366, filed on Korean Intellectual Property Office (KIPO) at 22/7/2021, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to a display device capable of improving light emitting efficiency and display quality.

Background

The display device is a device that displays a screen, and includes a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, and the like. Such a display device is used in various electronic devices such as a portable phone, a navigation device, a digital camera, an electronic book, a portable game device, or various terminals.

The display device has a multi-layer structure. For example, the display device may have a multilayer structure in which light-emitting elements, touch sensors, and the like are stacked on a substrate. Light generated by the light emitting element passes through the plurality of layers and is emitted to the outside of the display device, and thus a screen can be displayed. However, some of the light generated by the light emitting element may be reflected and lost by an interface between adjacent layers, and may not be emitted to the outside. Therefore, front light emitting efficiency and display quality of the display device may be deteriorated.

The above information disclosed in this background section is only for enhancement of understanding of the background of the technology and therefore it may contain information as follows: this information does not form the prior art known to those of ordinary skill in the art in this country.

Disclosure of Invention

Embodiments provide a display device capable of improving light emitting efficiency and display quality.

The display device according to the embodiment includes: a first light emitting element, a second light emitting element, and a third light emitting element which are respectively disposed on the substrate and emit light of different colors; a first insulating layer disposed on the first, second, and third light emitting elements, the first insulating layer including at least one opening; and a second insulating layer disposed on the first insulating layer, the second insulating layer being disposed in the at least one opening, wherein a refractive index of the second insulating layer is higher than a refractive index of the first insulating layer, and the at least one opening overlaps with at least one of the first, second, and third light emitting elements in a plan view, and the at least one opening does not overlap with at least another one of the first, second, and third light emitting elements in a plan view.

The at least one opening may overlap the first light emitting element and the third light emitting element in a plan view, and may not overlap the second light emitting element in a plan view.

The first insulating layer may cover the entire second light emitting element.

The first light emitting element may emit red light, the second light emitting element may emit green light, and the third light emitting element may emit blue light.

The at least one opening may overlap with the third light emitting element in a plan view, and the at least one opening may not overlap with the first light emitting element and the second light emitting element in a plan view.

The first light emitting element may emit red light, the second light emitting element may emit green light, and the third light emitting element may emit blue light.

The display device according to an embodiment may further include a first pixel electrode, a second pixel electrode, and a third pixel electrode disposed on the substrate; and a bank layer disposed on the first, second, and third pixel electrodes, and including a plurality of pixel openings overlapping the first, second, and third pixel electrodes in a plan view, at least one opening may overlap at least one of the plurality of pixel openings in a plan view, and at least one opening may not overlap at least another one of the plurality of pixel openings in a plan view.

The display device according to the embodiment may further include a first emission layer disposed on the first pixel electrode; a second emission layer disposed on the second pixel electrode; a third emission layer disposed on the third pixel electrode; and a common electrode disposed on the first emission layer, the second emission layer, the third emission layer, and the bank layer. The at least one opening may overlap at least one of the first, second, and third emission layers in a plan view, and the at least one opening may not overlap at least another one of the first, second, and third emission layers in a plan view.

The first pixel electrode, the first emission layer, and the common electrode may form a first light emitting element, the second pixel electrode, the second emission layer, and the common electrode may form a second light emitting element, and the third pixel electrode, the third emission layer, and the common electrode may form a third light emitting element.

The at least one opening may overlap the first pixel electrode and the first emission layer in a plan view, and may overlap the third pixel electrode and the third emission layer in a plan view, and the at least one opening may not overlap the second pixel electrode and the second emission layer in a plan view.

The at least one opening may not overlap the first pixel electrode and the first emission layer in a plan view, may not overlap the second pixel electrode and the second emission layer in a plan view, and may overlap the third pixel electrode and the third emission layer in a plan view.

The first emission layer may include an organic material emitting red light, the second emission layer may include an organic material emitting green light, and the third emission layer may include an organic material emitting blue light.

The plurality of pixel openings may be located within the at least one opening in a plan view.

The refractive index of the first insulating layer may be in a range of about 1.40 to about 1.59, and the refractive index of the second insulating layer may be in a range of about 1.60 to about 1.80.

The thickness of the first insulating layer may be in a range of about 2.0 μm to about 3.5 μm.

The second insulating layer may be formed of a light-transmitting organic insulating material or a pressure-sensitive adhesive.

The display device according to the embodiment may further include an encapsulation layer disposed on the first light emitting element, the second light emitting element, and the third light emitting element; and a sensing electrode disposed on the encapsulation layer, wherein the first insulating layer may be disposed on the sensing electrode.

The display device according to the embodiment includes: a first pixel electrode, a second pixel electrode, and a third pixel electrode disposed on the substrate; a bank layer disposed on the first, second, and third pixel electrodes, the bank layer including a plurality of pixel openings overlapping the first, second, and third pixel electrodes in a plan view; a first emission layer disposed on the first pixel electrode; a second emission layer disposed on the second pixel electrode; a third emission layer disposed on the third pixel electrode; a common electrode disposed on the first emission layer, the second emission layer, and the third emission layer; an encapsulation layer disposed on the common electrode; a sensing electrode disposed on the encapsulation layer; a first insulating layer disposed on the sensing electrode and including at least one opening; and a second insulating layer provided in the first insulating layer and having a refractive index higher than that of the first insulating layer, and the at least one opening overlaps with at least one of the plurality of pixel openings in a plan view and does not overlap with at least another one of the plurality of pixel openings in a plan view.

The first emission layer may include an organic material emitting red light, the second emission layer may include an organic material emitting green light, and the third emission layer may include an organic material emitting blue light.

The at least one opening may overlap, in a plan view, at least a portion of the plurality of pixel openings that overlaps the first pixel electrode and at least a portion of the plurality of pixel openings that overlaps the third pixel electrode, and the at least one opening may not overlap, in a plan view, at least a portion of the plurality of pixel openings that overlaps the second pixel electrode.

In a plan view, the first insulating layer may cover the entire pixel opening overlapping with the second pixel electrode.

The at least one opening may overlap the first pixel electrode, the first emission layer, the third pixel electrode, and the third emission layer in a plan view, and the at least one opening may not overlap the second pixel electrode and the second emission layer in a plan view.

The opening may overlap with a pixel opening overlapping with the third pixel electrode, and may not overlap with a pixel opening overlapping with the first pixel electrode and a pixel opening overlapping with the second pixel electrode.

The first insulating layer may completely cover the pixel opening overlapping the first pixel electrode and the pixel opening overlapping the second pixel electrode.

The opening may not overlap with the first pixel electrode and the first emission layer, may not overlap with the second pixel electrode and the second emission layer, and may overlap with the third pixel electrode and the third emission layer.

According to the embodiment, the light emitting efficiency and the display quality of the display device can be improved.

Drawings

Additional understanding of embodiments of the present disclosure will become apparent from the detailed description of the embodiments with reference to the drawings, in which:

fig. 1 is a schematic plan view of a display device according to an embodiment;

fig. 2 is a schematic plan view of a part including a detection portion in a display device according to an embodiment;

fig. 3 is a schematic plan view of a part of a display device according to an embodiment;

fig. 4 is a schematic cross-sectional view of a portion of a display device according to an embodiment;

fig. 5 is a schematic cross-sectional view of a first pixel and a periphery of the first pixel of a display device according to an embodiment;

fig. 6 is a schematic cross-sectional view of a second pixel and a periphery of the second pixel of the display device according to the embodiment;

fig. 7 is a schematic cross-sectional view of a third pixel and a periphery of the third pixel of the display device according to the embodiment;

fig. 8 shows the distribution of light in the display device according to the first reference example;

fig. 9 shows a distribution of light in a display device according to a second reference example;

fig. 10 shows a distribution of light in a display device according to a second reference example and a distribution of light in a display device according to an embodiment;

fig. 11 is a schematic cross-sectional view of a portion of a display device according to an embodiment;

fig. 12 is a schematic cross-sectional view of a portion of a display device according to an embodiment;

fig. 13 is a schematic cross-sectional view of a portion of a display device according to an embodiment;

fig. 14 is a schematic cross-sectional view of a portion of a display device according to an embodiment;

fig. 15 shows a distribution of light in a display device according to a second reference example and a distribution of light in a display device according to an embodiment; and

fig. 16 is a schematic cross-sectional view of a portion of a display device according to an embodiment.

Detailed Description

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. The described embodiments may be modified in various different ways, as will be appreciated by those skilled in the art.

The drawings and description are to be regarded as illustrative in nature, and not as restrictive. Like reference numerals refer to like elements throughout the specification.

Further, since the size and thickness of each configuration shown in the drawings are arbitrarily indicated for better understanding and ease of description, the present disclosure is not necessarily limited to the drawings. In the drawings, the thickness of layers, films, panels, regions, etc. may be exaggerated for clarity. In addition, in the drawings, the thickness of some layers and regions may be exaggerated for better understanding and ease of description.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. Further, throughout the specification, the word "on" in the target element will be understood to mean above or below the target element, and will not necessarily be understood to mean "at the upper side" based on the direction opposite to the direction of gravity.

Furthermore, unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

Further, throughout the specification, the phrase "on a plane" or "in a plan view" means to observe a target portion from the top, and the phrase "on a cross section" or "in a sectional view" means to observe a cross section formed by vertically cutting the target portion from a side.

The term "about" or "approximately" as used herein includes the stated value and the average value over an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art in view of the error associated with the measurement in question and the measurement of the specified quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%.

It will be understood that the terms "contacting," "connecting," and "coupled" may include physical and/or electrical contacting, connecting, or coupling.

For purposes of its meaning and explanation, at least one of the phrases "\8230"; 8230; "is intended to include the meaning of" at least one selected from the group of \8230; ". For example, "at least one of a and B" may be understood to mean "a, B, or a and B.

Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, with reference to fig. 1 and 2, a display device according to an embodiment will be described.

Fig. 1 is a schematic plan view of a display device according to an embodiment, and fig. 2 is a schematic plan view of a portion including a detection portion in the display device according to the embodiment.

Referring to fig. 1, a display device according to an embodiment may include a substrate 100 and a pad portion 30.

The substrate 100 may include a display area DA and a non-display area NA. The display area DA may be an area in which pixels (not shown in fig. 1 and 2) including light emitting diodes and transistors are formed to display an image. The non-display area NA may be an area in which an image is not displayed. The non-display area NA may surround the display area DA. The non-display area NA may be an area including the PAD part 30 in which a PAD for applying a driving signal to the pixel is formed in the PAD part 30.

Pixels (not shown in fig. 1 and 2) including transistors, light emitting diodes, and the like may be located in the display area DA. The pixels may be arranged in various shapes, for example, in a matrix format. A sensing area TA including the sensing electrodes 520 and 540 (e.g., refer to fig. 2) may be further positioned on an upper portion of the display area DA to recognize a touch (e.g., a touch event).

In the non-display area NA, a driving voltage line (not shown) for transmitting a driving signal such as a voltage and a signal to a pixel formed in the display area DA, a driving low voltage line (not shown), and the pad portion 30 may be positioned. The sensing lines 512 and 522 (e.g., refer to fig. 2) may be further positioned in the non-display area NA. The sensing lines 512 and 522 may be electrically connected to the sensing electrodes 520 and 540. Sense lines 512 and 522 and sense electrodes 520 and 540 will be further described with reference to fig. 2.

The PAD part 30 is positioned on a portion of the non-display area NA and includes a PAD. A voltage, a signal, or the like may be applied to a voltage line (not shown) electrically connected to the display area DA through the PAD, the sensing lines 512 and 522 (refer to fig. 2), or the like. A Flexible Printed Circuit Board (FPCB) (not shown) may be attached to the non-display area NA. A Flexible Printed Circuit Board (FPCB) may be electrically connected to the pad part 30. The Flexible Printed Circuit Board (FPCB) and the pad portion 30 may be electrically connected through an anisotropic conductive film. The Flexible Printed Circuit Board (FPCB) may include a driver Integrated Chip (IC) (not shown), and a driving signal output from the driver IC may be provided to each pixel through a PAD of the PAD part 30.

As shown in fig. 2, the substrate 100 may further include a sensing area TA having sensing electrodes 520 and 540 formed on the display area DA, and a peripheral area PA surrounding the sensing area TA. In an embodiment, the sensing area TA may include at least a portion of the display area DA and the non-display area NA of fig. 1, and the peripheral area PA may include an area other than the sensing area TA in the non-display area NA of fig. 1. For example, the peripheral area PA may include another portion of the non-display area NA of fig. 1 that does not overlap the sensing area TA. However, the positions of the sensing area TA and the peripheral area PA may be changed differently. For example, the sensing area TA may include a portion of the display area DA, and the peripheral area PA may include an area other than the sensing area TA in the display area DA and the non-display area NA. For example, the peripheral area PA may include another portion of the display area DA and the non-display area NA. As another example, the sensing area TA may include a display area DA and a non-display area NA.

The sensing electrodes 520 and 540 may be located in the sensing region TA. Sensing electrodes 520 and 540 may include a first sensing electrode 520 and a second sensing electrode 540. The sensing electrodes 520 and 540 may be formed on the same substrate as the substrate 100 including the pixels. For example, the sensing electrodes 520 and 540 may be formed on the substrate 100 including the pixels. For example, the pixel and sensing electrodes 520 and 540 may be located in a single panel.

The first sensing electrode 520 and the second sensing electrode 540 may be electrically insulated from each other. In an embodiment, the first sensing electrode 520 may be a sensing input electrode, and the second sensing electrode 540 may be a sensing output electrode. However, the present disclosure is not limited thereto, and the first sensing electrode 520 may be a sensing output electrode and the second sensing electrode 540 may be a sensing input electrode.

In a plan view, the first and second sensing electrodes 520 and 540 may be alternately disposed in the sensing region TA and not overlap each other. Accordingly, the first sensing electrode 520 and the second sensing electrode 540 may be disposed in a mesh shape. The first sensing electrodes 520 may be arranged in plurality along each of the column and row directions, and the second sensing electrodes 540 may also be arranged in plurality along each of the column and row directions. The first sensing electrodes 520 may be electrically connected to each other in the column direction through the first sensing electrode connection part 521. The second sensing electrodes 540 may be electrically connected to each other in the row direction through the second sensing electrode connection portions 541.

The first sensing electrode 520 and the second sensing electrode 540 may be located on the same layer. In an embodiment, the first sensing electrode 520 and the second sensing electrode 540 may be located on different layers. The first and second sensing electrodes 520 and 540 may have a diamond shape, but are not limited thereto. The first and second sensing electrodes 520 and 540 may have a polygonal shape such as a quadrangle or a hexagon, or a circular shape or an elliptical shape. However, the present disclosure is not limited thereto, and the first and second sensing electrodes 520 and 540 may be implemented in various shapes (such as a protruding shape having a protruding portion) to improve the sensitivity of the sensing sensor. The first sensing electrode 520 and the second sensing electrode 540 may be formed of a transparent conductor or an opaque conductor. For example, the first and second sensing electrodes 520 and 540 may include a Transparent Conductive Oxide (TCO), and the Transparent Conductive Oxide (TCO) may include at least one of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), zinc oxide (ZnO), carbon Nanotube (CNT), and graphene. First sensing electrode 520 and second sensing electrode 540 may include openings. The openings formed on the sensing electrodes 520 and 540 serve to allow light emitted from the light emitting diode to be emitted to the front without interference.

The first sensing electrodes 520 may be electrically connected to each other through a first sensing electrode connection part 521 (also referred to as a bridge), and the second sensing electrodes 540 may be electrically connected to each other through a second sensing electrode connection part 541. In the case where the first sensing electrodes 520 are electrically connected in a first direction, the second sensing electrodes 540 may be electrically connected in a second direction crossing the first direction. In a case where the first and second sensing electrodes 520 and 540 are located on the same layer, one of the first and second sensing electrode connection parts 521 and 541 may be located on the same layer as that of the first and second sensing electrodes 520 and 540, and the other of the first and second sensing electrode connection parts 521 and 541 may be located on a different layer from that of the first and second sensing electrodes 520 and 540. Thus, first sensing electrode 520 and second sensing electrode 540 may be electrically disconnected or electrically separated (or electrically insulated). The other of the first and second sensing electrode connection portions 521 and 541, which is located on the other layer, may be located on an upper or lower layer of the first and second sensing electrodes 520 and 540. In the embodiments described below, the other of the first and second sensing electrode connection portions 521 and 541 may be located on a lower layer (e.g., a layer closer to the substrate 100 than the first and second sensing electrodes 520 and 540), and thus will be mainly described.

Sensing lines 512 and 522 electrically connected to the first and second sensing electrodes 520 and 540 may be located in the peripheral area PA, respectively. Sensing lines 512 and 522 can include a first sensing line 512 and a second sensing line 522. The first sensing line 512 may be electrically connected to the second sensing electrode 540 disposed in the row direction, and the second sensing line 522 may be electrically connected to the first sensing electrode 520 disposed in the column direction. In an embodiment, the first sensing line 512 and the second sensing line 522 may be electrically connected to some of PADs PAD included in the PAD part 30 of fig. 1.

In fig. 2, a sensing part of a mutual capacitance type for sensing a touch (or touch event) using two sensing electrodes 520 and 540 is illustrated. However, in the embodiment, the sensing part may also be formed as or implemented with, for example, a self-capacitance type sensor that senses a touch (or touch event) using only one sensing electrode.

Hereinafter, with reference to fig. 3 to 7, an arrangement form of each pixel in the display device according to the embodiment will be described.

Fig. 3 is a schematic plan view of a portion of a display device according to an embodiment, and fig. 4 is a schematic cross-sectional view of a portion of a display device according to an embodiment. Fig. 5 is a schematic cross-sectional view of a first pixel and a periphery of the first pixel of a display device according to an embodiment, fig. 6 is a schematic cross-sectional view of a second pixel and a periphery of the second pixel of the display device according to the embodiment, and fig. 7 is a schematic cross-sectional view of a third pixel and a periphery of the third pixel of the display device according to the embodiment.

Referring to fig. 3 to 7, a display device according to an embodiment may include pixels R, G, and B. The pixels R, G, and B may include a first pixel R, a second pixel G, and a third pixel B. The first pixel R may display red, the second pixel G may display green, and the third pixel B may display blue. However, this is merely an example, and the pixels may also include pixels displaying other colors than red, green, and blue. For example, the display device may also include white pixels. As another example, the display device may include a pixel for displaying cyan, a pixel for displaying magenta, and a pixel for displaying yellow.

In the display region DA of the substrate 100 of the display device according to the embodiment, a transistor TFT including a semiconductor 131, a gate electrode 124, a source electrode 173, and a drain electrode 175, a gate insulating layer 120, a first interlayer insulating layer 160, a second interlayer insulating layer 180, pixel electrodes 191R, 191G, and 191B, emission layers 370R, 370G, and 370B, a bank layer 350, a common electrode 270, and an encapsulation layer 400 may be located in each of the pixels R, G, and B. The pixel electrodes 191R, 191G, and 191B, the emission layers 370R, 370G, and 370B, and the common electrode 270 may form light emitting elements EDR, EDG, and EDB. The display device according to the embodiment may further include a sensing region TA over the display region DA, and the sensing region TA may include a first sensing insulating layer 510, a second sensing insulating layer 530, sensing electrodes 520 and 540, a first sensing electrode connection portion 521, and a second sensing electrode connection portion 541. The display device according to the embodiment may further include a first insulating layer 550 and a second insulating layer 560 disposed over the sensing region TA.

The substrate 100 may include a material having a rigid characteristic such as glass or a flexible material that can be bent such as plastic or polyimide. On the substrate 100, a buffer layer 111 may be further positioned, the buffer layer 111 serving to planarize the surface of the substrate 100 and block penetration of impurity elements (or impurities). The buffer layer 111 may include an inorganic material. For example, the buffer layer 111 may include a material such as silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) Or silicon oxynitride (SiO) _x N _y ) The inorganic insulating material of (1). The buffer layer 111 may have a single-layer structure or a multi-layer structure of the above materials. A barrier layer (not shown) may further be positioned on the substrate 100. In this case, the barrier layer may be positioned between the substrate 100 and the buffer layer 111. The barrier layer may comprise, for example, silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) Or silicon oxynitride (SiO) _x N _y ) The inorganic insulating material of (1). The barrier layer may have a single-layer structure or a multi-layer structure of the above materials.

The semiconductor 131 may be located on the substrate 100. For example, the semiconductor 131 may be disposed on the buffer layer 111. The semiconductor 131 may include at least one of amorphous silicon, polycrystalline silicon, and an oxide semiconductor. For example, the semiconductor 131 may include Low Temperature Polysilicon (LTPS) or an oxide semiconductor material including at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and a mixture thereof. For example, the semiconductor 131 may include Indium Gallium Zinc Oxide (IGZO). The semiconductor 131 may include a channel region, a source region, and a drain region classified according to whether impurity doping is performed. The source and drain regions may have conductive characteristics corresponding to a conductor.

The gate insulating layer 120 may cover the semiconductor 131 and the substrate 100 (or overlap with the semiconductor 131 and the substrate 100). For example, the gate insulating layer 120 may cover the semiconductor 131 and the buffer layer 111. The gate insulating layer 120 may include, for example, silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) Or silicon oxynitride (SiO) _x N _y ) At least one inorganic insulating material. The gate insulating layer 120 may have a single-layer structure or a multi-layer structure of the above-described materials.

The gate electrode 124 may be positioned on the gate insulating layer 120. The gate electrode 124 may include a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), and titanium (Ti). The gate electrode 124 may include a metal alloy of the above metals. The gate electrode 124 may be formed as a single layer or a multi-layer. A region overlapping with the gate electrode 124 in a plan view in the semiconductor 131 may be a channel region.

The first interlayer insulating layer 160 may cover the gate electrode 124 and the gate insulating layer 120. The first interlayer insulating layer 160 may include, for example, silicon (SiN) _x ) Silicon oxide (SiO) _x ) Or silicon oxynitride (SiO) _x N _y ) The inorganic insulating material of (1). The first interlayer insulating layer 160 may have a single-layer structure or a multi-layer structure of the above-described materials.

The source electrode 173 and the drain electrode 175 may be positioned on the first interlayer insulating layer 160. The source electrode 173 and the drain electrode 175 may be electrically connected to a source region and a drain region of the semiconductor 131 through openings (e.g., contact holes) formed through the first interlayer insulating layer 160 and the gate insulating layer 120, respectively. The semiconductor 131, the gate electrode 124, the source electrode 173, and the drain electrode 175 described above form one transistor TFT. In an embodiment, the transistor TFT may include only source and drain regions of the semiconductor 131 without including the source and drain electrodes 173 and 175. Although the transistor TFT is provided in each of the pixels R, G, and B, a plurality of transistors TFT may be located in each of the pixels R, G, and B.

The source electrode 173 and the drain electrode 175 may include at least one metal or metal alloy of aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), or the like. The source electrode 173 and the drain electrode 175 may be formed in a single layer or a plurality of layers. The source electrode 173 and the drain electrode 175 according to an embodiment may be formed of three layers including an upper layer, an intermediate layer, and a lower layer. For example, the upper and lower layers of the three layers may include titanium (Ti), and the middle layer of the three layers may include aluminum (Al).

The second interlayer insulating layer 180 may be positioned on the source and drain electrodes 173 and 175. The second interlayer insulating layer 180 may cover the source electrode 173, the drain electrode 175, and the first interlayer insulating layer 160. The second interlayer insulating layer 180 may planarize a surface of the substrate 100 on which the transistor TFT is disposed. The second interlayer insulating layer 180 may be, for example, an organic insulator, and may include at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin.

The pixel electrodes 191R, 191G, and 191B may be on the second interlayer insulating layer 180. The first pixel electrode 191R may be positioned in the first pixel R, the second pixel electrode 191G may be positioned in the second pixel G, and the third pixel electrode 191B may be positioned in the third pixel B. The pixel electrodes 191R, 191G, and 191B may also be referred to as anodes, and may be formed of a single layer including a transparent conductive oxide film or a metal material or formed of multiple layers including a transparent conductive oxide film and a metal material. The transparent conductive oxide film of the pixel electrodes 191R, 191G, and 191B may include at least one of Indium Tin Oxide (ITO), poly ITO, indium Zinc Oxide (IZO), indium Gallium Zinc Oxide (IGZO), and Indium Tin Zinc Oxide (ITZO). The metal material of the pixel electrodes 191R, 191G, and 191B may include at least one of silver (Ag), molybdenum (Mo), copper (Cu), gold (Au), and aluminum (Al).

The second interlayer insulating layer 180 may include a via hole 81 exposing the drain electrode 175. The drain electrode 175 and the pixel electrodes 191R, 191G, and 191B may be physically and electrically connected through the via holes 81 of the second interlayer insulating layer 180. Accordingly, the pixel electrodes 191R, 191G, and 191B may receive the output current transferred from the drain electrode 175 to the emission layers 370R, 370G, and 370B.

The bank 350 may be positioned on the pixel electrodes 191R, 191G, and 191B and the second interlayer insulating layer 180. The bank layer 350 may also be referred to as a Pixel Defining Layer (PDL), and includes a pixel opening 351 overlapping with at least a portion of the pixel electrodes 191R, 191G, and 191B in a plan view. In this case, the pixel opening 351 may overlap with the center portions of the pixel electrodes 191R, 191G, and 191B in a plan view, and may not overlap with the edge portions of the pixel electrodes 191R, 191G, and 191B in a plan view. Accordingly, the size of the pixel opening 351 may be smaller than the size of each of the pixel electrodes 191R, 191G, and 191B. The bank 350 may partition (e.g., partition walls or banks) the formation positions of the emission layers 370R, 370G, and 370B so that the emission layers 370R, 370G, and 370B may be located on portions exposing the upper surfaces of the pixel electrodes 191R, 191G, and 191B. The bank layer 350 may be an organic insulator including at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. In an embodiment, the bank layer 350 may be formed as or implemented with, for example, a Black Pixel Defining Layer (BPDL) including a black pigment.

In a plan view, the pixel openings 351 may each have a shape similar to that of the pixel electrodes 191R, 191G, and 191B. For example, the pixel opening 351 and the pixel electrodes 191R, 191G, and 191B may be formed in a polygonal shape in a plan view. In this case, corners of the pixel opening 351 and the pixel electrodes 191R, 191G, and 191B may be chamfered. However, the shape of the pixel opening 351 and the shapes of the pixel electrodes 191R, 191G, and 191B are not limited thereto and may be variously changed.

The pixel electrodes 191R, 191G, and 191B corresponding to the first, second, and third pixels R, G, and B, respectively, may have different sizes in a plan view. Similarly, the pixel openings 351 corresponding to the first, second, and third pixels R, G, and B, respectively, may have different sizes in a plan view. For example, the pixel opening 351 and the first pixel electrode 191R corresponding to the first pixel R may have sizes larger than those of the pixel opening 351 and the second pixel electrode 191G corresponding to the second pixel G, respectively, in a plan view. In a plan view, the pixel opening 351 and the first pixel electrode 191R corresponding to the first pixel R may have a size smaller than or similar to a size of the pixel opening 351 and the third pixel electrode 191B corresponding to the third pixel B, respectively. However, the present disclosure is not limited thereto, and each of the pixel opening 351 and the pixel electrodes 191R, 191G, and 191B may have various sizes.

The pixels of the display device according to the embodiment may be arranged in a row direction and a column direction. For example, the second pixel electrodes 191G may be spaced apart from each other at a predetermined (or selected) interval in the nth row, and the third pixel electrodes 191B and the first pixel electrodes 191R may be alternately disposed in the adjacent (N + 1) th row. Similarly, the second pixel electrodes 191G may be spaced apart from each other at predetermined intervals in the adjacent (N + 2) th row, and the first and third pixel electrodes 191R and 191B may be alternately disposed in the adjacent (N + 3) th row.

The second pixel electrode 191G disposed in the nth row may be disposed to cross (or intersect) the third pixel electrode 191B and the first pixel electrode 191R disposed in the mth column. For example, the third pixel electrodes 191B and the first pixel electrodes 191R may be alternately disposed in the M-th column, and the second pixel electrodes 191G may be disposed in the adjacent (M + 1) -th column at predetermined intervals. Similarly, the first and third pixel electrodes 191R and 191B may be alternately disposed in the adjacent (M + 2) th column, and the second pixel electrode 191G may be disposed in the adjacent (M + 3) th column and spaced apart from each other at a predetermined interval. For example, the pixel electrodes 191R, 191G, and 191B may be repeatedly disposed on the substrate 100 in the above-described structure.

Each of the emission layers 370R, 370G, and 370B may be located within the pixel opening 351 separated by the bank layer 350. The emission layers 370R, 370G, and 370B may include organic materials emitting light such as red, green, and blue. The emission layers 370R, 370G, and 370B emitting red, green, and blue light may include a low molecular weight or high molecular weight organic material. In the first pixel R, the first emission layer 370R may be positioned on the first pixel electrode 191R. The first emission layer 370R may include an organic material emitting red light. In the second pixel G, a second emission layer 370G may be positioned on the second pixel electrode 191G. The second emission layer 370G may include an organic material emitting green light. In the third pixel B, a third emission layer 370B may be positioned on the third pixel electrode 191B. The third emission layer 370B may include an organic material emitting blue light.

In fig. 4 to 7, the emission layers 370R, 370G, and 370B are illustrated as single layers, but basically, auxiliary layers such as an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer may also be included above and/or below each of the emission layers 370R, 370G, and 370B. The hole injection layer and the hole transport layer may be positioned below the emission layers 370R, 370G, and 370B, and the electron transport layer and the electron injection layer may be positioned above the emission layers 370R, 370G, and 370B.

Other emission layers may be further positioned on the emission layers 370R, 370G, and 370B. For example, the fourth emission layer may be further positioned on the first emission layer 370R, and the fourth emission layer may emit light having a wavelength substantially equal to that of the light emitted by the first emission layer 370R. The fifth emission layer may be further positioned on the second emission layer 370G, and the fifth emission layer may emit light having a wavelength substantially equal to that of the light emitted by the second emission layer 370G. The sixth emission layer may be further positioned on the third emission layer 370B, and the sixth emission layer may emit light having a wavelength substantially equal to that of the light emitted from the third emission layer 370B. In the above case, it has been described that the two emission layers overlap each other in a plan view, but is not limited thereto. For example, three or more emission layers may be stacked and formed.

Although not shown, spacers may be further positioned on the bank layer 350. The spacers and the bank layer 350 may include the same material. However, the present disclosure is not limited thereto, and the spacer may be formed of a material different from that of the bank layer 350. The spacer may be an organic insulator including at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin.

The common electrode 270 may be positioned on the bank layer 350 and the emission layers 370R, 370G, and 370B. The common electrode 270 of each of the pixels R, G, and B may be electrically connected to each other. The common electrode 270 may be integrally connected to the substrate 100. The common electrode 270 may also be referred to as a cathode, and may be formed of a transparent conductive layer including at least one of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Gallium Zinc Oxide (IGZO), and Indium Tin Zinc Oxide (ITZO). The common electrode 270 may be formed of at least one metal material such as silver (Ag) or magnesium (Mg) or a mixture thereof. The thickness of the common electrode 270 may be adjusted to form a transparent conductive layer. For example, the thickness of the common electrode 270 including a metal material may be reduced, and the common electrode 270 may transmit light. For example, the common electrode 270 may have a semi-transparent property, and may form a micro cavity together with the pixel electrodes 191R, 191G, and 191B. According to the microcavity structure, light of a specific wavelength may be emitted to the upper portion of the display device through the interval and characteristics between the two electrodes, and the result may be displayed in red, green, or blue.

The pixel electrodes 191R, 191G, and 191B, the emission layers 370R, 370G, and 370B, and the common electrode 270 may form light emitting elements EDR, EDG, and EDB. In the first pixel R, the first pixel electrode 191R, the first emission layer 370R, and the common electrode 270 may form a first light emitting element EDR emitting red light. A portion where the first pixel electrode 191R, the first emission layer 370R, and the common electrode 270 overlap each other may be a light emitting region of the first light emitting element EDR in a plan view. In the second pixel G, the second pixel electrode 191G, the second emission layer 370G, and the common electrode 270 may form a second light emitting element EDG emitting green light. A portion where the second pixel electrode 191G, the second emission layer 370G, and the common electrode 270 overlap each other in a plan view may be a light emitting region of the second light emitting element EDG. In the third pixel B, the third pixel electrode 191B, the third emission layer 370B, and the common electrode 270 may form a third light emitting element EDB emitting blue light. A portion where the third pixel electrode 191B, the third emission layer 370B, and the common electrode 270 overlap each other in a plan view may be a light emitting region of the third light emitting element EDB.

The encapsulation layer 400 may be positioned on the common electrode 270. The encapsulation layer 400 may include at least one inorganic layer and at least one organic layer. In an embodiment, the encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430. However, this is merely an example, and the number of inorganic layers and organic layers forming the encapsulation layer 400 may be variously changed. For example, the encapsulation layer 400 may be stacked in the order of a first inorganic encapsulation layer, a second inorganic encapsulation layer, a first organic encapsulation layer, and a third inorganic encapsulation layer. In another example, the encapsulation layer 400 may be stacked in the order of a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, and a third inorganic encapsulation layer. The first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430 may be positioned in at least a portion of the display area DA and the non-display area NA. In an embodiment, the organic encapsulation layer 420 may be formed around the display area DA, and the first and second inorganic encapsulation layers 410 and 430 may be formed up to the non-display area NA. The encapsulation layer 400 may protect the light emitting elements EDR, EDG, and EDB from moisture or oxygen that may flow in from the outside, and the ends of the first and second inorganic encapsulation layers 410 and 430 may be formed to be in direct contact with each other.

The buffer layer 501 may be on the encapsulation layer 400. The buffer layer 501 may be formed as, or implemented with, an inorganic insulating layer, for example. The inorganic material included in the inorganic insulating layer of the buffer layer 501 may be at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. In an embodiment, the buffer layer 501 may be omitted.

The second sensing electrode connection portion 541, the first sensing insulation layer 510, and the sensing electrodes 520 and 540 may be located on the buffer layer 501. Although not shown, the first sensing electrode connection part 521 (e.g., refer to fig. 2) may be disposed on the buffer layer 501. One of the first sensing electrode connection part 521 (for example, refer to fig. 2) and the second sensing electrode connection part 541 may be disposed on the same layer as the sensing electrodes 520 and 540, and the other may be disposed on a different layer from the sensing electrodes 520 and 540. Hereinafter, an example in which the second sensing electrode connection portion 541 is located on a different layer from the sensing electrodes 520 and 540 will be described.

The second sensing electrode connection portion 541, the first sensing electrode connection portion 521, the first sensing insulation layer 510, and the sensing electrodes 520 and 540 may form a sensing sensor. The sensing sensor may be classified into a resistance type, a capacitance type, an electromagnetic type, an optical type, and the like. The sensing sensor according to the embodiment may use a capacitive type sensor.

The second sensing electrode connection portion 541 may be positioned on the buffer layer 501, and the first sensing insulation layer 510 may be positioned on the buffer layer 501 and the second sensing electrode connection portion 541. The first sensing insulating layer 510 may include an inorganic insulating material or an organic insulating material. The inorganic insulating material of the first sensing insulating layer 510 may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The organic insulating material of the first sensing insulating layer 510 may include at least one of acryl-based resin, methacrylic resin, polyisoprene, vinyl-based resin, epoxy-based resin, urethane-based resin, cellulose-based resin, and perylene-based resin.

The sensing electrodes 520 and 540 may be on the first sensing insulation layer 510. Sensing electrodes 520 and 540 may include a first sensing electrode 520 and a second sensing electrode 540. First sensing electrode 520 and second sensing electrode 540 may be electrically insulated. The first sensing insulating layer 510 may include an opening (e.g., a contact hole) exposing an upper surface of the second sensing electrode connection portion 541, and the second sensing electrode connection portion 541 may be electrically connected to the second sensing electrode 540, and thus two adjacent second sensing electrodes 540 may be electrically connected through the opening of the first sensing insulating layer 510. The first sensing electrode connection part 521 for connecting the first sensing electrode 520, and the second sensing electrode 540 may be formed on the same layer.

The sensing electrodes 520 and 540 may include a conductive material having good conductivity. For example, the sensing electrodes 520 and 540 may include a metal such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta), or a metal alloy thereof. The sensing electrodes 520 and 540 may be formed of a single layer or a plurality of layers. The sensing electrodes 520 and 540 may include openings, and thus light emitted from the light emitting diodes is emitted upward without interference. In an embodiment, the sensing electrodes 520 and 540 may be formed as three layers including an upper layer, an intermediate layer, and a lower layer. For example, the upper and lower layers of the three layers may include titanium (Ti), and the middle layer of the three layers may include aluminum (Al).

The second sensing insulating layer 530 may be disposed on the sensing electrodes 520 and 540 and the first sensing insulating layer 510. The second sensing insulating layer 530 may include an inorganic insulating material or an organic insulating material. The inorganic insulating material of the second sensing insulating layer 530 may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The organic insulating material of the second sensing insulating layer 530 may include at least one of acryl-based resin, methacrylic resin, polyisoprene, vinyl-based resin, epoxy-based resin, urethane-based resin, cellulose-based resin, and perylene-based resin.

The first insulating layer 550 may be disposed on the second sensing insulating layer 530. The first insulating layer 550 may include a light-transmitting organic insulating material having a low refractive index. For example, the first insulating layer 550 may include at least one of acrylic (acrylic) resin, polyimide resin, polyamide resin, and Alq3[ tris (8-quinolinolato) aluminum ]. The first insulating layer 550 may have a relatively small refractive index compared to that of the second insulating layer 560, which will be described below. For example, the first insulating layer 550 may have a refractive index in the range of about 1.40 to about 1.59. The thickness of the first insulating layer 550 may be in a range of about 2.0 μm to about 3.5 μm.

The first insulating layer 550 may include an opening 551. The opening 551 may mean a portion where the second sensing insulating layer 530 is not covered by the first insulating layer 550. The opening 551 of the first insulating layer 550 may overlap with the pixel openings 351 of some (or part of) the pixels R, G, and B in a plan view. The opening 551 of the first insulating layer 550 may be larger than the pixel opening 351 and may be formed in a shape surrounding the pixel opening 351. In this specification, the opening 551 and the pixel opening 351 may be used in the singular, however, the opening 551 and the pixel opening 351 may also be understood as a plurality of openings 551 and a plurality of pixel openings 351, respectively.

In a plan view, the opening 551 of the first insulating layer 550 may overlap some of the pixels R, G, and B, and may not overlap some other of the pixels R, G, and B. For example, the opening 551 of the first insulating layer 550 may overlap with at least one of the first, second, and third pixels R, G, and B, and may not overlap with at least another one of the first, second, and third pixels R, G, and B in a plan view. Accordingly, the opening 551 of the first insulating layer 550 may overlap at least one of the first light emitting element EDR, the second light emitting element EDG, and the third light emitting element EDB and may not overlap at least another one of the first light emitting element EDR, the second light emitting element EDG, and the third light emitting element EDB in a plan view. The opening 551 of the first insulating layer 550 may overlap at least one of the first, second, and third pixel electrodes 191R, 191G, and 191B, and may not overlap at least another one of the first, second, and third pixel electrodes 191R, 191G, and 191B, in a plan view. In a plan view, the opening 551 of the first insulating layer 550 may overlap the pixel opening 351 located in at least one of the first, second, and third pixels R, G, and B, and may not overlap the pixel opening 351 located in at least another one of the first, second, and third pixels R, G, and B. In a plan view, the opening 551 of the first insulating layer 550 may overlap at least one of the first, second, and third emission layers 370R, 370G, and 370B, and may not overlap at least another one of the first, second, and third emission layers 370R, 370G, and 370B.

For example, the opening 551 of the first insulating layer 550 may overlap the first pixel R and the third pixel B in a plan view, and may not overlap the second pixel G in a plan view. Accordingly, in the first and third pixels R and B, at least a portion of the second sensing insulating layer 530 may not be covered by the first insulating layer 550, but may be exposed. The second sensing insulating layer 530 exposed by the opening 551 in the first and third pixels R and B may contact the second insulating layer 560. In the second pixel G, the entire second sensing insulating layer 530 may be covered (or overlapped) by the first insulating layer 550, and the second sensing insulating layer 530 may not be exposed. In a plan view, the opening 551 of the first insulating layer 550 may overlap the first and third light emitting elements EDR and EDB, and may not overlap the second light emitting element EDG. At least a portion of the first and third light emitting elements EDR and EDB may not be covered by the first insulating layer 550, and the second light emitting element EDG may be completely covered by the first insulating layer 550. The opening 551 of the first insulating layer 550 may overlap the first and third pixel electrodes 191R and 191B, and may not overlap the second pixel electrode 191G in a plan view. In a plan view, the opening 551 of the first insulating layer 550 may overlap the pixel opening 351 located at the first pixel R and the pixel opening 351 located at the third pixel B, and may not overlap the pixel opening 351 located at the second pixel G. The opening 551 of the first insulating layer 550 may overlap the first and third emission layers 370R and 370B, and may not overlap the second emission layer 370G in a plan view.

In the first and third pixels R and B, the spaced distance between the pixel opening 351 and the opening 551 of the first insulating layer 550 may be constant. The spacing distance between the pixel opening 351 and the opening 551 of the first insulating layer 550 may mean the shortest distance between the edge of the pixel opening 351 and the edge of the opening 551. The edge of the pixel opening 351 may mean a point at which the edge of the bank layer 350 contacts the pixel electrodes 191R, 191G, and 191B. The edge of the opening 551 may mean a point at which the edge of the first insulating layer 550 contacts the second sensing insulating layer 530. The separation distance between the pixel opening 351 and the opening 551 of the first insulating layer 550 may be in the range of about 0.5 μm to about 3.0 μm. In an embodiment, the spaced distance between the pixel opening 351 and the opening 551 of the first insulating layer 550 may be constant, but is not limited thereto. The separation distance between the pixel opening 351 and the opening 551 of the first insulating layer 550 in the first and third pixels R and B may be different according to the position thereof. A spacing distance between the pixel opening 351 in the first pixel R and the opening 551 of the first insulating layer 550 may be different from a spacing distance between the pixel opening 351 in the third pixel B and the opening 551 of the first insulating layer 550.

The second insulating layer 560 may be on the second sensing insulating layer 530 and the first insulating layer 550. The second insulating layer 560 may include a light-transmitting organic insulating material having a high refractive index. The second insulating layer 560 may have a relatively large refractive index compared to that of the first insulating layer 550. For example, the second insulating layer 560 may have a refractive index in the range of about 1.60 to about 1.80.

The second insulating layer 560 may be positioned within the opening 551 of the first insulating layer 550. The second insulating layer 560 may contact a side surface of the first insulating layer 550 (or may contact a side surface of the first insulating layer 550). In addition, the second insulating layer 560 may be positioned on the upper surface of the first insulating layer 550 so as to be in contact with the upper surface of the first insulating layer 550.

After the opening 551 is formed on the first insulating layer 550, a material having a high refractive index may be applied on the first insulating layer 550 as a whole by an inkjet method, and a curing process may be performed to form the second insulating layer 560. The high refractive index material may have fluidity and may move. Accordingly, the high refractive index material may migrate into the opening 551 of the first insulating layer 550 and fill the opening 551. However, a portion of the opening 551 of the first insulating layer 550 may not be filled with a high refractive index material. The smaller the size of the opening 551 of the first insulating layer 550 is, the higher the probability that the high refractive index material cannot enter. The second pixel G may have a relatively small size compared to the first and third pixels R and B. In the embodiment, the opening 551 of the first insulating layer 550 overlaps the first pixel R and the third pixel B in a plan view, but does not overlap the second pixel G in a plan view. In the case where the opening 551 of the first insulating layer 550 overlaps the second pixel G, the size of the opening 551 may be relatively small compared to other pixels. Therefore, the high refractive index material may not be filled in the opening 551 overlapped with the second pixel G. In an embodiment, the opening 551 of the first insulating layer 550 may not overlap the second pixel G having a relatively small size in a plan view, but may overlap the first pixel R and the third pixel B having a relatively large size in a plan view. Accordingly, the high refractive index material may be appropriately filled in the opening 551 of the first insulating layer 550 overlapping the first and third pixels R and B. For example, a problem that the second insulating layer 560 is not formed in some of the openings 551 of the first insulating layer 550 can be solved.

The thicker the thickness of the first insulating layer 550, the higher the obstruction of the high refractive index material into the opening 551. In the embodiment, since the opening 551 of the first insulating layer 550 does not overlap the second pixel G having a relatively small size, such an entry obstacle can be formed high. For example, although the thickness of the first insulating layer 550 is formed thick, a high refractive index material may be appropriately filled in the opening 551 of the first insulating layer 550, and the second insulating layer 560 may be formed in the opening 551. For example, the thickness of the first insulating layer 550 may be formed up to about 3.5 μm. Since the thickness of the first insulating layer 550 is increased, the light collection efficiency may be increased to the front. For example, front visibility and light output efficiency of the display device can be improved.

Although the method of forming the second insulating layer 560 by applying the high refractive index material having fluidity on the first insulating layer 550 has been described above, the method for forming the second insulating layer 560 is not limited thereto. For example, the second insulation layer 560 may be formed of a Pressure Sensitive Adhesive (PSA) having a high refractive index. The pressure-sensitive adhesive may include an adhesive material that is tacky upon application of pressure applied to an adhesive surface thereof. The pressure-sensitive adhesive can be made by mixing various types of rubbers and various resins. The strength of the adhesive may be affected by the amount of pressure applied to the surface of the adhesive. After forming the opening 551 on the first insulating layer 550, a pressure sensitive adhesive of high refractive index may be positioned on the first insulating layer 550, and pressure may be applied to form the second insulating layer 560. In the case where pressure may be applied to the high refractive index pressure sensitive adhesive, the second insulating layer 560 may be positioned within the opening 551 of the first insulating layer 550. In the case where the second insulating layer 560 is made of a pressure-sensitive adhesive of a high refractive index, the second insulating layer 560 may be located within the opening 551 regardless of the size of the opening 551. Accordingly, the thickness of the first insulating layer 550 may be increased, and front visibility and light output efficiency of the display device may be improved.

The polarizing layer 600 may be further positioned on the second insulating layer 560. The polarizing layer 600 may be located in the sensing region TA (e.g., refer to fig. 2) and may include a linear polarizer, a retarder, and the like.

The cover window 620 protecting the sensing area TA and the display area DA may be further positioned on the sensing area TA. The adhesive layer 610 may be further positioned between the polarizing layer 600 and the cover window 620.

The display device according to the embodiment may include a first insulating layer 550 and a second insulating layer 560, wherein the first insulating layer 550 includes an opening 551, and the second insulating layer 560 is positioned within the opening 551 of the first insulating layer 550, thereby improving front visibility and light output efficiency of the display device. For example, at least a portion of light generated by the first and third light emitting elements EDR and EDB may be totally reflected at an interface between the first and second insulating layers 550 and 560, and thus the light may be condensed to the front.

The light L generated from the emission layers 370R, 370G, and 370B of the pixels R, G, and B may be emitted in various directions and may be incident on the sensing region TA at various incidence angles. As shown in fig. 5 to 7, a portion of the light L emitted from the first light emitting element EDR of the first pixel R and the third light emitting element EDB of the third pixel B and incident on the second insulating layer 560 of the sensing region TA may be emitted to the front, and another portion of the light L may be reflected at an interface between the first insulating layer 550 and the second insulating layer 560. For example, in the case where the incident angle of the light L incident to the second insulating layer 560 is greater than a threshold angle, the incident light L may be totally reflected at the interface between the first insulating layer 550 and the second insulating layer 560. For example, when light L incident on the second insulating layer 560 having a relatively large refractive index reaches the first insulating layer 550 having a relatively small refractive index, total reflection at the interface between the first insulating layer 550 and the second insulating layer 560 may occur. An interface between the first insulating layer 550 and the second insulating layer 560 may intersect a straight line parallel to the substrate 100 at a predetermined angle. The interface between the first insulating layer 550 and the second insulating layer 560 may be a side surface of the first insulating layer 550. Accordingly, the side surface of the first insulating layer 550 may be inclined at a predetermined inclination angle with respect to the upper surface of the second sensing insulating layer 530.

Referring to fig. 6, a portion of light L emitted from the second light emitting element EDG of the second pixel G and incident on the first insulating layer 550 of the sensing region TA may be emitted to the front after passing through the second insulating layer 560, and the other light L may return after being reflected by the cover window 620. The opening 551 may be formed in a portion of the first insulating layer 550 overlapping the first and third pixels R and B in a plan view, and the light L is totally reflected at an interface of the first insulating layer 550 and the second insulating layer 560 within the opening 551, and thus the front light output rate may be increased.

The opening 551 may not be formed in a portion of the first insulating layer 550 overlapping the second pixel G in a plan view, and may relatively increase a side light emissivity as compared to the first pixel R and the third pixel B. In the case where the opening 551 of the first insulating layer 550 overlaps with all the pixels R, G, and B in a plan view, the side luminance ratio may be lowered. In the display device according to the embodiment, by not forming the opening 551 in a portion of the first insulating layer 550 which overlaps with some pixels in a plan view, the side luminance ratio can be improved.

Hereinafter, referring to fig. 8 to 10, the display device according to the embodiment will be compared with the display device according to the reference example.

Fig. 8 shows the distribution of light in the display device according to the first reference example REF1, and fig. 9 shows the distribution of light in the display device according to the second reference example REF 2. Fig. 10 shows the distribution of light in the display device according to the second reference example REF2 and the distribution of light in the display device according to embodiment EMB 1. In fig. 10, the distribution of light in the display device according to the second reference example REF2 is shown on the left side, and the distribution of light in the display device according to the embodiment EMB1 is shown on the right side.

In fig. 8 to 10, the forward direction perpendicular to the substrate is 0 degree, and light emitted from both sides of the front surface is shown at an angle of about +90 degrees to about-90 degrees, and the amount of light emitted from the respective angles is indicated. The illustration shows that a majority of the light is shown as being distributed over a range between about +30 degrees and about-30 degrees. The remaining light is shown as being distributed between about +30 degrees and about +60 degrees, and between about-30 degrees and about-60 degrees. The light is divided into red, green and blue light.

In the display device according to the first reference example REF1, an opening is not formed in the first insulating layer. In the display device according to the second reference example REF2, the opening of the first insulating layer overlaps with all the pixels in a plan view. In the display device according to embodiment EMB1, the opening of the first insulating layer is formed to overlap some pixels in a plan view and not overlap some other pixels in a plan view. In this case, the opening of the first insulating layer is formed to overlap with the red pixel and the blue pixel in a plan view, and not overlap with the green pixel in a plan view.

As shown in fig. 8, in the display device according to the first reference example REF1, the ratio of the amount of light emitted from the side to the amount of light emitted from the front, i.e., the side luminance ratio, may be about 47.1%. In this case, the amount of light emitted from the side surface may represent the amount of light at about 45 degrees. As shown in fig. 9, in the display device according to the second reference example REF2, the side luminance ratio may be about 40.4%. In the display device according to the second reference example REF2, the opening of the first insulating layer is formed to overlap all the pixels in a plan view, and thus the front luminance ratio may be relatively high and the side luminance ratio may be relatively low. In the display device according to the first reference example REF1, since the opening is not formed in the first insulating layer, the front light emission ratio may be relatively low, and the side luminance ratio may be relatively high.

As shown in fig. 10, in the display device according to embodiment EMB1, the side luminance ratio may be about 46.9%. In the display device according to embodiment EMB1, the side luminance ratio can be increased by increasing the amount of light emitted to the side by not forming an opening in a portion of the first insulating layer overlapping with the green pixel. In the display device according to the second reference example REF2, at a low angle (a range between 0 degree and about +30 degrees, 0 degree and about-30 degrees), the light emission efficiency of the red pixel is high, and thus a reddish phenomenon may occur. In the display device according to embodiment EMB1, the reddish phenomenon may be prevented from occurring at the low-angle side by increasing the side luminance ratio of the green pixel.

For example, the display device according to embodiment EMB1 may improve a front light emission ratio by forming openings in portions of the first insulating layer overlapping some pixels, and may improve a side luminance ratio and may reduce a reddish phenomenon by not forming openings in portions of the first insulating layer overlapping some other pixels.

Next, with reference to fig. 11, a display device according to an embodiment will be described.

The display device according to the embodiment shown in fig. 11 is almost the same as the display device according to the embodiment of fig. 1 to 7, and thus description of the same parts will be omitted. This embodiment differs from the previous embodiment at least in that: the opening of the first insulating layer does not overlap with the third pixel in a plan view, and will be described further below.

Fig. 11 is a schematic cross-sectional view of a portion of a display device according to an embodiment.

Referring to fig. 11, a display device according to an embodiment may include a substrate 100, a transistor TFT disposed on the substrate 100, and light emitting elements EDR, EDG, and EDB electrically connected to the transistor TFT. The display device according to the embodiment may include pixels R, G, and B, and the pixels R, G, and B may include a first pixel R, a second pixel G, and a third pixel B. The first light emitting element EDR may include a first pixel electrode 191R, a first emission layer 370R, and a common electrode 270, and may be positioned in the first pixel R. The second light emitting element EDG may include a second pixel electrode 191G, a second emission layer 370G, and a common electrode 270, and may be positioned in the second pixel G. The third light emitting element EDB may include a third pixel electrode 191B, a third emission layer 370B, and a common electrode 270, and may be positioned in the third pixel B. The first light emitting element EDR may emit red light, the second light emitting element EDG may emit green light, and the third light emitting element EDB may emit blue light. The display device according to the embodiment may further include a first sensing insulating layer 510, a second sensing insulating layer 530, and sensing electrodes 520 and 540 on the light emitting elements EDR, EDG, and EDB. The display device according to the embodiment may further include a first insulating layer 550 having an opening 551 and a second insulating layer 560 on the first insulating layer 550. The first and second insulating layers 550 and 560 may be disposed on the sensing electrodes 520 and 540.

The opening 551 of the first insulating layer 550 may overlap the first pixel R and the second pixel G in a plan view, and may not overlap the third pixel B in a plan view. For example, the opening 551 of the first insulating layer 550 may overlap only each of the first and second pixels R and G in a plan view. Accordingly, in the first and second pixels R and G, at least a portion of the second sensing insulating layer 530 may not be covered (or overlapped) by the first insulating layer 550, but may be exposed by the opening 551. In the first and second pixels R and G, the second sensing insulating layer 530 may be exposed by the opening 551 and may be in contact with the second insulating layer 560. In the third pixel B, the entire second sensing insulating layer 530 may be covered by the first insulating layer 550, and the second sensing insulating layer 530 may not be exposed. In a plan view, the opening 551 of the first insulating layer 550 may overlap the first and second light emitting elements EDR and EDG, and may not overlap the third light emitting element EDB. At least a portion of the first and second light emitting elements EDR and EDG may not be covered by the first insulating layer 550, and the third light emitting element EDB may be completely covered by the first insulating layer 550. The opening 551 of the first insulating layer 550 may overlap with the first and second pixel electrodes 191R and 191G in a plan view, and may not overlap with the third pixel electrode 191B in a plan view. The opening 551 of the first insulating layer 550 may overlap the pixel opening 351 located at the first pixel R and the pixel opening 351 located at the second pixel G in a plan view, and may not overlap the pixel opening 351 located at the third pixel B in a plan view. The opening 551 of the first insulating layer 550 may overlap the first and second emission layers 370R and 370G, and may not overlap the third emission layer 370B in a plan view.

For example, the display device according to the embodiment may improve a front light emission ratio by forming openings in portions of the first insulating layer overlapping some of the pixels, and may improve a side luminance ratio and may adjust a color of light emitted from the display device by not forming openings in portions of the first insulating layer overlapping some of the other pixels.

Next, with reference to fig. 12, a display device according to an embodiment will be described.

The display device according to the embodiment shown in fig. 12 is almost the same as the display device according to the embodiment shown in fig. 1 to 7, and thus description of the same parts will be omitted. This embodiment differs from the previous embodiment at least in that: the opening of the first insulating layer does not overlap the first pixel in a plan view, which will be described further below.

Fig. 12 is a schematic cross-sectional view of a portion of a display device according to an embodiment.

Referring to fig. 12, a display device according to an embodiment may include a substrate 100, a transistor TFT disposed on the substrate 100, and light emitting elements EDR, EDG, and EDB electrically connected to the transistor TFT. The display device according to the embodiment may include pixels R, G, and B, and the pixels R, G, and B may include a first pixel R, a second pixel G, and a third pixel B. The first light emitting element EDR may include a first pixel electrode 191R, a first emission layer 370R, and a common electrode 270, and may be positioned in the first pixel R. The second light emitting element EDG may include a second pixel electrode 191G, a second emission layer 370G, and a common electrode 270, and may be positioned in the second pixel G. The third light emitting element EDB may include a third pixel electrode 191B, a third emission layer 370B, and a common electrode 270, and may be positioned in the third pixel B. The first light emitting element EDR may emit red light, the second light emitting element EDG may emit green light, and the third light emitting element EDB may emit blue light. The display device according to the embodiment may further include a first sensing insulating layer 510, a second sensing insulating layer 530, and sensing electrodes 520 and 540 on the light emitting elements EDR, EDG, and EDB. The display device according to the embodiment may further include a first insulating layer 550 having an opening 551 and a second insulating layer 560 on the first insulating layer 550. The first and second insulating layers 550 and 560 may be disposed on the sensing electrodes 520 and 540.

The opening 551 of the first insulating layer 550 may overlap the second pixel G and the third pixel B in a plan view, and may not overlap the first pixel R in a plan view. For example, the opening 551 of the first insulating layer 550 may overlap only with each of the second and third pixels G and B in a plan view. Accordingly, in the second and third pixels G and B, at least a portion of the second sensing insulating layer 530 may not be covered by the first insulating layer 550, but may be exposed by the opening 551. In the second and third pixels G and B, the second sensing insulating layer 530 may be exposed by the opening 551 and may be in contact with the second insulating layer 560. In the first pixel R, the entire second sensing insulating layer 530 may be covered by the first insulating layer 550, and the second sensing insulating layer 530 may not be exposed. The opening 551 of the first insulating layer 550 may overlap the second and third light emitting elements EDG and EDB, and may not overlap the first light emitting element EDR in a plan view. At least a portion of the second and third light emitting elements EDG and EDB may not be covered by the first insulating layer 550, and the first light emitting element EDR may be completely covered by the first insulating layer 550. The opening 551 of the first insulating layer 550 may overlap with the second and third pixel electrodes 191G and 191B, and may not overlap with the first pixel electrode 191R in a plan view. The opening 551 of the first insulating layer 550 may overlap the pixel opening 351 at the second pixel G and the pixel opening 351 at the third pixel B in plan view, and may not overlap the pixel opening 351 at the first pixel R. The opening 551 of the first insulating layer 550 may overlap the second and third emission layers 370G and 370B, and may not overlap the first emission layer 370R in a plan view.

The display device according to the embodiment may improve a front light emission ratio by forming openings in portions of the first insulating layer overlapping some of the pixels, and may improve a side luminance ratio by not forming openings in portions of the first insulating layer overlapping some of the other pixels, and may adjust a color of light emitted from the display device.

Next, with reference to fig. 13, a display device according to an embodiment will be described.

The display device according to the embodiment shown in fig. 13 is almost the same as the display device according to the embodiment shown in fig. 1 to 7, and thus description of the same parts will be omitted. This embodiment differs from the previous embodiment at least in that: the opening of the first insulating layer does not overlap with the second pixel and the third pixel in a plan view, which will be described further below.

Fig. 13 is a schematic cross-sectional view of a portion of a display device according to an embodiment.

Referring to fig. 13, a display device according to an embodiment may include a substrate 100, a transistor TFT disposed on the substrate 100, and light emitting elements EDR, EDG, and EDB electrically connected to the transistor TFT. The display device according to the embodiment may include pixels R, G, and B, and the pixels R, G, and B may include a first pixel R, a second pixel G, and a third pixel B. The first light emitting element EDR may include a first pixel electrode 191R, a first emission layer 370R, and a common electrode 270, and may be positioned in the first pixel R. The second light emitting element EDG may include a second pixel electrode 191G, a second emission layer 370G, and a common electrode 270, and may be positioned in the second pixel G. The third light emitting element EDB may include a third pixel electrode 191B, a third emission layer 370B, and a common electrode 270, and may be positioned in the third pixel B. The first light emitting element EDR may emit red light, the second light emitting element EDG may emit green light, and the third light emitting element EDB may emit blue light. The display device according to the embodiment may further include a first sensing insulating layer 510, a second sensing insulating layer 530, and sensing electrodes 520 and 540 on the light emitting elements EDR, EDG, and EDB. The display device according to an embodiment may further include a first insulating layer 550 having an opening 551 and a second insulating layer 560 on the first insulating layer 550. The first and second insulating layers 550 and 560 may be disposed on the sensing electrodes 520 and 540.

The opening 551 of the first insulating layer 550 may overlap the first pixel R in a plan view, and may not overlap the second pixel G and the third pixel B in a plan view. Accordingly, in the first pixel R, at least a portion of the second sensing insulating layer 530 may be exposed without being covered by the first insulating layer 550. For example, a portion of the first insulating layer 550 may be opened in the first pixel R to expose a portion of the second sensing insulating layer 530. The second sensing insulating layer 530 exposed by the opening 551 in the first pixel R may be in contact with the second insulating layer 560. In the second and third pixels G and B, the entire second sensing insulating layer 530 may be covered by the first insulating layer 550, and the second sensing insulating layer 530 may not be exposed. In a plan view, the opening 551 of the first insulating layer 550 may overlap the first light emitting element EDR, and may not overlap the second light emitting element EDG and the third light emitting element EDB. At least a portion of the first light emitting element EDR may not be covered by the first insulating layer 550, and the second and third light emitting elements EDG and EDB may be completely covered by the first insulating layer 550. The opening 551 of the first insulating layer 550 may overlap the first pixel electrode 191R, and may not overlap the second and third pixel electrodes 191G and 191B in a plan view. The opening 551 of the first insulating layer 550 may overlap the pixel opening 351 located at the first pixel R in a plan view, and may not overlap the pixel opening 351 located at the second pixel G and the pixel opening 351 located at the third pixel B in a plan view. The opening 551 of the first insulating layer 550 may overlap the first emission layer 370R in a plan view, and may not overlap the second emission layer 370G and the third emission layer 370B in a plan view.

The display device according to the embodiment may improve a front light emission ratio by forming openings in portions of the first insulating layer overlapping some of the pixels, and may improve a side luminance ratio by not forming openings in portions of the first insulating layer overlapping some of the other pixels, and may adjust a color of light emitted from the display device.

Next, a display device according to an embodiment will be described with reference to fig. 14 and 15.

The display device according to the embodiment shown in fig. 14 and 15 is almost the same as the display device according to the embodiment shown in fig. 1 to 7, and thus description of the same parts will be omitted. This embodiment differs from the previous embodiment at least in that: the opening of the first insulating layer does not overlap with the first pixel and the second pixel in a plan view, and will be further described below.

Fig. 14 is a schematic cross-sectional view of a part of a display device according to an embodiment, and fig. 15 shows the distribution of light in the display device according to the second reference example REF2 and the distribution of light in the display device according to the embodiment. In fig. 15, the distribution of light in the display device according to the second reference example REF2 is shown on the left, and the distribution of light in the display device according to the embodiment EMB2 is shown on the right.

As shown in fig. 14, a display device according to an embodiment may include a substrate 100, a transistor TFT disposed on the substrate 100, and light emitting elements EDR, EDG, and EDB electrically connected to the transistor TFT. The display device according to the embodiment may include pixels R, G, and B, and the pixels R, G, and B may include a first pixel R, a second pixel G, and a third pixel B. The first light emitting element EDR may include a first pixel electrode 191R, a first emission layer 370R, and a common electrode 270, and may be located in the first pixel R. The second light emitting element EDG may include a second pixel electrode 191G, a second emission layer 370G, and a common electrode 270, and may be positioned in the second pixel G. The third light emitting element EDB may include a third pixel electrode 191B, a third emission layer 370B, and a common electrode 270, and may be positioned in the third pixel B. The first light emitting element EDR may emit red light, the second light emitting element EDG may emit green light, and the third light emitting element EDB may emit blue light. The display device according to the embodiment may further include a first sensing insulating layer 510, a second sensing insulating layer 530, and sensing electrodes 520 and 540 on the light emitting elements EDR, EDG, and EDB. The display device according to the embodiment may further include a first insulating layer 550 having an opening 551 and a second insulating layer 560 on the first insulating layer 550. The first and second insulating layers 550 and 560 may be disposed on the sensing electrodes 520 and 540.

The opening 551 of the first insulating layer 550 may overlap the third pixel B in a plan view, and may not overlap the first and second pixels R and G in a plan view. Accordingly, in the third pixel B, at least a portion of the second sensing insulating layer 530 may be exposed without being covered by the first insulating layer 550. For example, a portion of the first insulating layer 550 may be opened in the third pixel B to expose a portion of the second sensing insulating layer 530. The second sensing insulating layer 530 exposed by the opening 551 in the third pixel B may be in contact with the second insulating layer 560. In the first and second pixels R and G, the entire second sensing insulating layer 530 may be covered by the first insulating layer 550, and the second sensing insulating layer 530 may not be exposed. The opening 551 of the first insulating layer 550 may overlap the third light emitting element EDB in a plan view, and may not overlap the first and second light emitting elements EDR and EDG in a plan view. At least a portion of the third light emitting element EDB may not be covered by the first insulating layer 550, and the first and second light emitting elements EDR and EDG may be completely covered by the first insulating layer 550. The opening 551 of the first insulating layer 550 may overlap with the third pixel electrode 191B, and may not overlap with the first and second pixel electrodes 191R and 191G in a plan view. In a plan view, the opening 551 of the first insulating layer 550 may overlap the pixel opening 351 located at the third pixel B, and may not overlap the pixel opening 351 located at the first pixel R and the pixel opening 351 located at the second pixel G. In a plan view, the opening 551 of the first insulating layer 550 may overlap with the third emission layer 370B, and may not overlap with the first and second emission layers 370R and 370G.

The display device according to the embodiment may improve a front light emission ratio by forming openings in portions of the first insulating layer overlapping some of the pixels, and may improve a side luminance ratio by not forming openings in portions of the first insulating layer overlapping some of the other pixels, and may adjust a color of light emitted from the display device.

As shown in fig. 15, in the display device according to embodiment EMB2, the side luminance ratio of light emitted from the side may be about 48.1%. In the display device according to embodiment EMB2, an opening is not formed in a portion of the first insulating layer overlapping with the red pixel and the green pixel, and thus the amount of light emitted to the side surface is increased, thereby increasing the side surface luminance ratio. In the display device according to the second reference example REF2, the side luminance ratio is about 40.4%, and the side luminance ratio in the display device according to the embodiment described above with reference to fig. 1 to 10 may be about 46.9%. According to the present embodiment, the side luminance ratio is about 48.1%, and therefore, the side luminance ratio can be further improved. In the present embodiment, it can be determined that the amounts of emitted red light and green light increase at a low angle.

Next, a display device according to an embodiment will be described with reference to fig. 16.

The display device according to the embodiment shown in fig. 16 is almost the same as the display device according to the embodiment shown in fig. 1 to 7, and thus description of the same parts will be omitted. This embodiment differs from the previous embodiment at least in that: the opening of the first insulating layer does not overlap the first pixel and the third pixel, and will be described further below.

Fig. 16 is a schematic cross-sectional view of a portion of a display device according to an embodiment.

As shown in fig. 16, a display device according to an embodiment may include a substrate 100, a transistor TFT disposed on the substrate 100, and light emitting elements EDR, EDG, and EDB electrically connected to the transistor TFT. The display device according to the embodiment may include pixels R, G, and B, and the pixels R, G, and B may include a first pixel R, a second pixel G, and a third pixel B. The first light emitting element EDR may include a first pixel electrode 191R, a first emission layer 370R, and a common electrode 270, and may be located in the first pixel R. The second light emitting element EDG may include a second pixel electrode 191G, a second emission layer 370G, and a common electrode 270, and may be positioned in the second pixel G. The third light emitting element EDB may include a third pixel electrode 191B, a third emission layer 370B, and a common electrode 270, and may be positioned in the third pixel B. The first light emitting element EDR may emit red light, the second light emitting element EDG may emit green light, and the third light emitting element EDB may emit blue light. The display device according to the embodiment may further include a first sensing insulating layer 510, a second sensing insulating layer 530, and sensing electrodes 520 and 540 on the light emitting elements EDR, EDG, and EDB. The display device according to an embodiment may further include a first insulating layer 550 having an opening 551 and a second insulating layer 560 on the first insulating layer 550. The first and second insulating layers 550 and 560 may be disposed on the sensing electrodes 520 and 540.

The opening 551 of the first insulating layer 550 may overlap the second pixel G in a plan view, and may not overlap the first pixel R and the third pixel B in a plan view. Accordingly, in the second pixel G, at least a portion of the second sensing insulating layer 530 may be exposed without being covered by the first insulating layer 550. For example, a portion of the first insulating layer 550 may be opened in the second pixel G to expose a portion of the second sensing insulating layer 530. The second sensing insulating layer 530 exposed by the opening 551 in the second pixel G may be in contact with the second insulating layer 560. In the first and third pixels R and B, the entire second sensing insulating layer 530 may be covered by the first insulating layer 550, and the second sensing insulating layer 530 may not be exposed. The opening 551 of the first insulating layer 550 may overlap the second light emitting element EDG in a plan view, and may not overlap the first light emitting element EDR and the third light emitting element EDB in a plan view. At least a portion of the second light emitting element EDG may not be covered by the first insulating layer 550, and the first and third light emitting elements EDR and EDB may be completely covered by the first insulating layer 550. The opening 551 of the first insulating layer 550 may overlap with the second pixel electrode 191G, and may not overlap with the first and third pixel electrodes 191R and 191B in a plan view. The opening 551 of the first insulating layer 550 may overlap the pixel opening 351 located at the second pixel G in a plan view, and may not overlap the pixel opening 351 located at the first pixel R and the pixel opening 351 located at the third pixel B in a plan view. The opening 551 of the first insulating layer 550 may overlap the second emission layer 370G in a plan view, and may not overlap the first and third emission layers 370R and 370B in a plan view.

The display device according to the embodiment may improve a front light emission ratio by forming openings in portions of the first insulating layer overlapping some of the pixels, and may improve a side luminance ratio by not forming openings in portions of the first insulating layer overlapping some of the other pixels, and may adjust a color of light emitted from the display device.

While the disclosure has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments. On the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (17)

1. A display device, comprising:

a first light emitting element, a second light emitting element, and a third light emitting element which are respectively provided on a substrate and emit light of different colors;

a first insulating layer disposed on the first, second, and third light emitting elements, the first insulating layer including at least one opening; and

a second insulating layer disposed on the first insulating layer, the second insulating layer disposed in the at least one opening,

wherein a refractive index of the second insulating layer is higher than a refractive index of the first insulating layer,

the at least one opening overlaps with at least one of the first light emitting element, the second light emitting element, and the third light emitting element in a plan view, an

The at least one opening does not overlap with at least another one of the first light emitting element, the second light emitting element, and the third light emitting element in a plan view.

2. The display device according to claim 1,

the at least one opening overlaps with the first light emitting element and the third light emitting element in a plan view, an

The at least one opening does not overlap with the second light emitting element in a plan view.

3. The display device according to claim 2, wherein the first insulating layer covers the entire second light-emitting element.

4. The display device according to claim 3,

the first light emitting element emits red light,

the second light emitting element emits green light, an

The third light emitting element emits blue light.

5. The display device according to claim 1,

the at least one opening overlaps with the third light emitting element in a plan view, an

The at least one opening does not overlap with the first light emitting element and the second light emitting element in a plan view.

6. The display device according to claim 5,

the first light emitting element emits red light, the second light emitting element emits green light, and the third light emitting element emits blue light.

7. The display device according to claim 1, further comprising:

a first pixel electrode, a second pixel electrode, and a third pixel electrode disposed on the substrate; and

a bank layer disposed on the first, second, and third pixel electrodes,

wherein the bank layer includes a plurality of pixel openings overlapping with the first pixel electrode, the second pixel electrode, and the third pixel electrode in a plan view,

the at least one opening overlaps with at least one of the plurality of pixel openings in a plan view, an

The at least one opening does not overlap with at least another one of the plurality of pixel openings in a plan view.

8. The display device according to claim 7, further comprising:

a first emission layer disposed on the first pixel electrode;

a second emission layer disposed on the second pixel electrode;

a third emission layer disposed on the third pixel electrode; and

a common electrode disposed on the first emission layer, the second emission layer, the third emission layer, and the bank layer,

wherein the at least one opening overlaps with at least one of the first emission layer, the second emission layer, and the third emission layer in a plan view, an

The at least one opening does not overlap with at least another one of the first emission layer, the second emission layer, and the third emission layer in a plan view.

9. The display device according to claim 8,

the first pixel electrode, the first emission layer and the common electrode form the first light emitting element,

the second pixel electrode, the second emission layer, and the common electrode form the second light emitting element, an

The third pixel electrode, the third emission layer, and the common electrode form the third light emitting element.

10. The display device according to claim 9,

the at least one opening overlaps with the first pixel electrode and the first emission layer in a plan view, and overlaps with the third pixel electrode and the third emission layer in a plan view,

the at least one opening does not overlap with the second pixel electrode and the second emission layer in a plan view.

11. The display device according to claim 9,

the at least one opening does not overlap with the first pixel electrode and the first emission layer in a plan view,

the at least one opening does not overlap the second pixel electrode and the second emission layer in a plan view, an

The at least one opening overlaps the third pixel electrode and the third emission layer in a plan view.

12. The display device according to claim 11,

the first emission layer includes an organic material emitting red light, the second emission layer includes an organic material emitting green light, and the third emission layer includes an organic material emitting blue light.

13. The display device of claim 7, wherein the plurality of pixel openings are located within the at least one opening in plan view.

14. The display device according to claim 1,

the refractive index of the first insulating layer is in the range of 1.40 to 1.59, an

The second insulating layer has a refractive index in a range of 1.60 to 1.80.

15. The display device according to claim 1, wherein a thickness of the first insulating layer is in a range of 2.0 μm to 3.5 μm.

16. The display device according to claim 1, wherein the second insulating layer is formed of a light-transmitting organic insulating material or a pressure-sensitive adhesive.

17. The display device according to claim 1, further comprising:

an encapsulation layer disposed on the first, second, and third light emitting elements; and

a sensing electrode disposed on the encapsulation layer,

wherein the first insulating layer is disposed on the sensing electrode.

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