CN115701208A

CN115701208A - Static random access memory and forming method thereof

Info

Publication number: CN115701208A
Application number: CN202110856135.8A
Authority: CN
Inventors: 金吉松
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2021-07-28
Filing date: 2021-07-28
Publication date: 2023-02-07

Abstract

A static random access memory and a forming method thereof, comprising a substrate; the static random access memory comprises a plurality of channel layers, a plurality of grid structures and a plurality of source-drain doping layers; a first dielectric layer on the substrate; the first conductive structure is electrically connected with part of the grid structure and part of the source-drain doping layer; and the shared conductive structure comprises a second conductive structure and a shared conductive layer positioned on the second conductive structure, and the top surface of the shared conductive structure is lower than that of the first conductive structure. Because the top surface of the shared conductive structure is lower than that of the first conductive structure, the subsequently formed power conductive layer has a larger forming space, so that the process window of the power conductive layer is enlarged, the contact resistance between the power conductive layer and the subsequently formed second pull-up conductive layer is reduced, and the performance of the static random access memory is effectively improved.

Description

Static random access memory and forming method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a static random access memory and a forming method thereof.

Background

With the continuous development of digital integrated circuits, on-chip integrated memories have become an important component in digital systems. Static Random Access Memory (SRAM) is an essential component of on-chip Memory due to its advantages of low power consumption and high speed.

The basic sram typically includes six transistors: 2 first Pull-up transistors (PU), 2 first Pull-down transistors (PD), and 2 first Pass transistors (PG). When the static random access memory works, as long as continuous power supply is provided, the stored data can be continuously stored without any updating operation. Compared with a Dynamic Random Access Memory (DRAM) circuit, the SRAM circuit does not need to be refreshed and charged once every a period of time to avoid disappearance of internal storage data, and therefore, the SRAM circuit has high performance and low power consumption.

However, the sram formed in the prior art still has many problems.

Disclosure of Invention

The invention provides a static random access memory and a forming method thereof, which can effectively improve the performance of the static random access memory.

To solve the above problems, the present invention provides a static random access memory, comprising: a substrate; the static random access memory unit comprises a plurality of channel layers, a plurality of grid structures and a plurality of source-drain doping layers; the first dielectric layer is positioned on the substrate, covers the static random access memory unit and exposes the top surfaces of a plurality of grid structures in the static random access memory unit; the first conductive structure is electrically connected with part of the grid structure and part of the source-drain doping layer; the shared conductive structure comprises a second conductive structure and a shared conductive layer positioned on the second conductive structure, the second conductive structure is electrically connected with part of the grid structure and part of the source-drain doped layer, and the top surface of the shared conductive structure is lower than that of the first conductive structure; a second dielectric layer on the first dielectric layer, the second dielectric layer covering the first conductive structure and the shared conductive structure.

Optionally, the sram cell includes: a first pass transistor, a first pull-up transistor, and a first pull-down transistor.

Optionally, some of the channel layers include: a first transmission channel layer, a first pull-up channel layer and a first pull-down channel layer; a number of the gate structures include: the first transmission grid, the first pull-up grid and the first pull-down grid; the plurality of source-drain doped layers comprise: the first transmission source-drain doped layer, the first pull-up source-drain doped layer and the first pull-down source-drain doped layer.

Optionally, the first transfer transistor includes: the first transmission channel layer, the first transmission grid structure crossing over the first transmission channel layer and the first transmission source-drain doping layers located on two sides of the first transmission grid are arranged in the first transmission channel layer; the first pull-up transistor includes: the first pull-up channel layer, a first pull-up gate structure crossing over the first pull-up channel layer and first pull-up source drain doping layers positioned on two sides of the first pull-up gate, wherein the first pull-up source drain doping layers are positioned in the first pull-up channel layer; the first pull-down transistor includes: the semiconductor device comprises a first pull-down channel layer, a first pull-down gate structure stretching across the first pull-down channel layer, and first pull-down source-drain doped layers located on two sides of the first pull-down gate, wherein the first pull-down source-drain doped layers are located in the first pull-down channel layer.

Optionally, the first conductive structure includes: the first transmission conductive layer is positioned on the first transmission grid electrode, the transmission conductive plug is positioned on the first transmission source-drain doping layer, the second transmission conductive layer is positioned on the transmission conductive plug, and the top surface of the first transmission conductive layer is flush with the top surface of the second transmission conductive layer.

Optionally, the second conductive structure includes: the shared conductive layer is positioned on the first pull-up conductive layer and the pull-down conductive plug, and the top surface of the shared conductive layer is lower than the top surfaces of the first transmission conductive layer and the second transmission conductive layer.

Optionally, the method further includes: a capping layer on the shared conductive structure, a top surface of the capping layer being flush with a top surface of the second dielectric layer.

Optionally, the plurality of channel layers further include: a second pull-up channel layer; a plurality of said gate structures further comprising: a second pull-up gate; the plurality of source-drain doped layers further comprise: and a first pull-up source drain doped layer.

Optionally, the sram cell further comprises: a second pull-up transistor, the second pull-up transistor comprising: the second pull-up channel layer, the second pull-up grid stretching over the second pull-up channel layer and the second pull-up source drain doping layers located on two sides of the second pull-up grid are arranged, and the second pull-up source drain doping layers are located in the second pull-up channel layer.

Optionally, the method further includes: a third conductive structure on the second pull-up transistor, the third conductive structure being within the second dielectric layer, and a top surface of the third conductive structure being flush with a top surface of the first conductive structure.

Optionally, the third conductive structure includes: the second pull-up conductive layer is positioned on the pull-up conductive plug, and the top surface of the second pull-up conductive layer is flush with the top surface of the first transmission conductive layer and the top surface of the second transmission conductive layer.

Optionally, the method further includes: the third dielectric layer is positioned on the second dielectric layer, the fourth conductive structure is positioned in the third dielectric layer, and the fourth conductive structure is electrically connected with the first conductive structure and the third conductive structure respectively.

Optionally, the fourth conductive structure includes: a word line layer electrically connected to the first conductive transmission layer; a bit line layer electrically connected with the second transmission conductive layer; a power conductive layer extending along the first direction, and electrically connected with the second pull-up conductive layer.

Correspondingly, the technical scheme of the invention also provides a method for forming the static random access memory, which comprises the following steps: providing a substrate; forming a plurality of static random access memory units and a first dielectric layer on the substrate, wherein each static random access memory unit comprises a plurality of channel layers, a plurality of grid structures and a plurality of source-drain doping layers, and the first dielectric layer covers the static random access memory units and exposes the top surfaces of the grid structures in the static random access memory units; and forming a second dielectric layer, a first conductive structure and a shared conductive structure, wherein the first conductive structure is electrically connected with part of the gate structure and part of the source-drain doping layer, the shared conductive structure comprises a second conductive structure and a shared conductive layer positioned on the second conductive structure, the second conductive structure is electrically connected with part of the gate structure and part of the source-drain doping layer, the top surface of the shared conductive structure is lower than that of the first conductive structure, the second dielectric layer is positioned on the first dielectric layer, and the second dielectric layer covers the first conductive structure and the shared conductive structure.

Optionally, the plurality of channel layers include: a first transmission channel layer, a first pull-up channel layer and a first pull-down channel layer; a plurality of the gate structures include: the first transmission grid, the first pull-up grid and the first pull-down grid; the plurality of source-drain doped layers comprise: the first transmission source-drain doped layer, the first pull-up source-drain doped layer and the first pull-down source-drain doped layer.

Optionally, the forming method of the shared conductive structure includes: forming the first pull-up conducting layer in the second dielectric layer, wherein the first pull-up conducting layer is in contact with the first pull-up gate; forming a pull-down conductive plug in the second dielectric layer, wherein the pull-down conductive plug is in contact with the first pull-down source drain doped layer; forming an initial shared conductive layer in the second dielectric layer, wherein the initial shared conductive layer is respectively contacted with the first pull-up conductive layer and the pull-down conductive plug, and the top surface of the initial shared conductive layer is flush with the top surface of the first transmission conductive layer and the top surface of the second transmission conductive layer; and etching back the initial shared conducting layer to form the shared conducting layer, wherein the top surface of the shared conducting layer is lower than the top surface of the first transmission conducting layer and the top surface of the second transmission conducting layer.

Optionally, after forming the shared conductive layer, the method further includes: and forming a covering layer on the shared conductive structure, wherein the top surface of the covering layer is flush with the top surface of the second dielectric layer.

Optionally, the sram cell further includes: a second pull-up transistor, the second pull-up transistor comprising: the second pull-up channel layer, a second pull-up grid stretching over the second pull-up channel layer and second pull-up source drain doping layers located on two sides of the second pull-up grid are arranged, and the second pull-up source drain doping layers are located in the second pull-up channel layer.

Optionally, in the process of forming the first conductive structure and the shared conductive structure, the method further includes: forming a third conductive structure on the second pull-up transistor, the third conductive structure being located within the second dielectric layer, and a top surface of the third conductive structure being flush with a top surface of the first conductive structure.

Optionally, after the first conductive structure and the shared conductive structure are formed, the method further includes: and forming a third dielectric layer and a fourth conductive structure, wherein the third dielectric layer is positioned on the second dielectric layer, the fourth conductive structure is positioned in the third dielectric layer, and the fourth conductive structure is respectively and electrically connected with the first conductive structure and the third conductive structure.

Optionally, the fourth conductive structure includes: a word line layer electrically connected with the first conductive transmission layer; a bit line layer electrically connected with the second transmission conductive layer; a power conductive layer extending along the first direction, and electrically connected with the second pull-up conductive layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

the static random access memory of the technical scheme of the invention comprises: the first conductive structure is electrically connected with part of the grid structure and part of the source-drain doping layer; the shared conductive structure comprises a second conductive structure and a shared conductive layer positioned on the second conductive structure, the second conductive structure is electrically connected with part of the grid structure and part of the source-drain doped layer, and the top surface of the shared conductive structure is lower than that of the first conductive structure. Because the top surface of the shared conductive structure is lower than that of the first conductive structure, the power conductive layer has larger forming space, so that the process window of the power conductive layer is enlarged, the contact resistance between the power conductive layer and the second pull-up conductive layer is reduced, and the performance of the static random access memory is effectively improved.

In the method for forming the static random access memory according to the technical scheme of the invention, a first conductive structure and a shared conductive structure are formed, the first conductive structure is electrically connected with part of the grid structure and part of the source-drain doping layer, the shared conductive structure comprises a second conductive structure and a shared conductive layer positioned on the second conductive structure, the second conductive structure is electrically connected with part of the grid structure and part of the source-drain doping layer, and the top surface of the shared conductive structure is lower than that of the first conductive structure. Because the top surface of the shared conductive structure is lower than that of the first conductive structure, a subsequently formed power supply conductive layer has a larger forming space, so that the process window of the power supply conductive layer is enlarged, the contact resistance between the power supply conductive layer and the subsequently formed second pull-up conductive layer is reduced, and the performance of the static random access memory is effectively improved.

Drawings

FIGS. 1-2 are schematic structural diagrams of an SRAM;

fig. 3 to fig. 15 are schematic structural diagrams of steps of a method for forming an sram according to an embodiment of the present invention.

Detailed Description

As described in the background, problems still exist with prior art sram designs. The following detailed description will be made in conjunction with the accompanying drawings.

Referring to fig. 1 and 2, fig. 1 isbase:Sub>A top view ofbase:Sub>A sram, and fig. 2 isbase:Sub>A cross-sectional view taken along linebase:Sub>A-base:Sub>A of fig. 1 and omittingbase:Sub>A substrate,base:Sub>A first pull-up transistor andbase:Sub>A second pull-up transistor, including: a substrate 100; a first pass transistor PG1, a first pull-up transistor PU1, and a first pull-down transistor PD1 on the substrate 100; a first conductive structure (not shown) electrically connected to the first transfer transistor PG 1; a second conductive structure 101, the second conductive structure 101 being electrically connected to the first pull-up transistor PU1 and the first pull-down transistor PD1, respectively, a top surface of the second conductive structure 101 being flush with a top surface of the first conductive structure.

In this embodiment, the first transfer transistor PG1 includes: a first transmission gate and first transmission source-drain doped layers (not labeled) positioned at two sides of the first transmission gate; the first pull-up transistor PU1 includes: the transistor comprises a first upper pull-up gate and first upper pull-up source drain doped layers (not marked) positioned on two sides of the first upper pull-up gate; the first pull-down transistor PD1 includes: the semiconductor device comprises a first pull-down gate and first pull-down source drain doped layers (not marked) positioned at two sides of the first pull-down gate.

The first conductive structure includes: the first transmission conductive layer is positioned on the first transmission grid electrode, the transmission conductive plug is positioned on the first transmission source-drain doping layer, the second transmission conductive layer is positioned on the transmission conductive plug, and the top surface of the first transmission conductive layer is flush with the top surface of the second transmission conductive layer.

The second conductive structure 101 includes: the structure comprises a first pull-up conducting layer 101a positioned on a first pull-up grid, a pull-down conducting plug 101b positioned on a first pull-down source-drain doping layer, and a shared conducting layer 101c positioned on the first pull-up conducting layer and the pull-down conducting plug, wherein the top surface of the shared conducting layer 101c is flush with the top surfaces of the first transmission conducting layer and the second transmission conducting layer.

Please refer to fig. 1 and fig. 2, further comprising: a second pull-up transistor PU2 on the substrate 100; a third conductive structure 102 located on the second pull-up transistor PU2, a top surface of the third conductive structure 102 being flush with a top surface of the first conductive structure.

In this embodiment, the second pull-up transistor PU2 includes a second pull-up gate and second pull-up source drain doped layers (not labeled) located at two sides of the second pull-up gate; the third conductive structure 102 includes: the second pull-up conductive layer 102b is located on the pull-up conductive plug, and the top surface of the second pull-up conductive layer 102b is flush with the top surface of the first transmission conductive layer and the top surface of the second transmission conductive layer.

Please refer to fig. 1 and fig. 2, further comprising: a power conductive layer 103, the power conductive layer 103 being electrically connected to the second pull-up conductive layer 102 b.

In this embodiment, the power conductive layer 103 may not be shorted with the shared conductive layer 101c according to circuit design requirements. However, since the top surface of the shared conductive layer 101c is flush with the top surfaces of the first and second transmitting conductive layers. In order to avoid short circuit between the power conductive layer 103 and the shared conductive layer 101c, the design size of the power conductive layer 103 needs to be reduced, so that the volume of the power conductive layer 103 is reduced, the contact resistance between the power conductive layer 103 and the second pull-up conductive layer 102b is increased, and the process window of the power conductive layer 103 is also reduced, so that the performance of the sram is reduced.

On the basis, the top surface of the shared conductive structure is lower than that of the first conductive structure, so that a subsequently formed power conductive layer has a larger forming space, a process window of the power conductive layer is enlarged, contact resistance between the power conductive layer and the second pull-up conductive layer is reduced, and the performance of the static random access memory is effectively improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to fig. 15 are schematic structural diagrams illustrating a process of forming an sram according to an embodiment of the present invention.

Referring to fig. 3, a substrate is provided.

In this embodiment, silicon is used as the material of the substrate 200; in other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

In this embodiment, after providing a substrate 200, a plurality of sram cells and a first dielectric layer are formed on the substrate 200, where each sram cell includes a plurality of channel layers, a plurality of gate structures, and a plurality of source-drain doping layers, and the first dielectric layer covers the sram cell and exposes top surfaces of the gate structures in the sram cell. Please refer to fig. 4 to fig. 9 for a specific forming process.

In this embodiment, the plurality of channel layers include: a first transmission channel layer, a first pull-up channel layer, a first pull-down channel layer, a second transmission channel layer, a second pull-up channel layer, and a second pull-down channel layer; a plurality of the gate structures include: the first transmission grid, the first pull-up grid, the first pull-down grid, the second transmission grid, the second pull-up grid and the second pull-down grid; the plurality of source-drain doped layers comprise: the semiconductor device comprises a first transmission source-drain doped layer, a first pull-up source-drain doped layer, a first pull-down source-drain doped layer, a second transmission source-drain doped layer, a second pull-up source-drain doped layer and a second pull-down source-drain doped layer.

Referring to fig. 4 to 6, fig. 4 is a perspective view of a static random access memory, fig. 5 is a top view of fig. 4, and fig. 6 is a schematic cross-sectional view taken along line B-B in fig. 5, in which a first transmission channel layer, a first pull-up channel layer, a first pull-down channel layer, a second transmission channel layer, a second pull-up channel layer, and a second pull-down channel layer (not labeled) are formed on the substrate 200.

In this embodiment, the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer extend along the first direction X.

In this embodiment, the materials of the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer and the first pull-down channel layer adopt silicon; in other embodiments, the materials of the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer and the first pull-down channel layer may also adopt germanium, silicon carbide, gallium arsenide or indium gallium arsenide.

In this embodiment, the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer adopt fin structures; in other embodiments, the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer may also adopt a GAA structure or a nanoshieet structure.

Referring to fig. 7, fig. 7 and fig. 6 are shown in the same view direction, and an isolation layer 201 is formed on the substrate.

In this embodiment, the isolation layer covers a portion of the sidewall of the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer, and the top surface of the isolation layer is lower than the top surface of the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer.

In this embodiment, the material of the isolation layer is silicon oxide.

Referring to fig. 8 and 9, fig. 8 is a top view of the sram without a first dielectric layer, fig. 9 is a schematic cross-sectional view along line C-C in fig. 8, a first dielectric layer 202 and a plurality of sram cells are formed on the substrate 200, the first dielectric layer 202 covers the sram cells, and the top surfaces of a plurality of gate structures in the sram cells are exposed.

In this embodiment, the sram cell includes: a first pass transistor PG1, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pass transistor PG2, a second pull-up transistor PU2, and a second pull-down transistor PD2.

In this embodiment, the first transfer transistor PG1 includes: the first transmission channel layer, the first transmission grid structure stretching across the first transmission channel layer and the first transmission source-drain doping layers located on two sides of the first transmission grid are arranged in the first transmission channel layer.

In this embodiment, the first pull-up transistor PU2 includes: the source drain structure comprises a first pull-up channel layer, a first pull-up gate structure stretching over the first pull-up channel layer and first pull-up source drain doping layers located on two sides of the first pull-up gate, wherein the first pull-up source drain doping layers are located in the first pull-up channel layer.

In this embodiment, the first pull-down transistor PD1 includes: the semiconductor device comprises a first pull-down channel layer, a first pull-down gate structure stretching across the first pull-down channel layer, and first pull-down source-drain doped layers located on two sides of the first pull-down gate, wherein the first pull-down source-drain doped layers are located in the first pull-down channel layer.

In this embodiment, the first dielectric layer 202 is made of silicon oxide; in other embodiments, the material of the first dielectric layer may also be a low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).

Referring to fig. 10 to 12, fig. 9 is a top view of a static random access memory without a first dielectric layer, a second dielectric layer, and a covering layer, fig. 11 is a schematic cross-sectional view of fig. 10 taken along line D-D and without a first transfer transistor, fig. 12 is a schematic cross-sectional view of fig. 10 taken along line E-E and without a first pull-up transistor and a second pull-up transistor, forming a second dielectric layer 209, a first conductive structure, and a shared conductive structure, where the first conductive structure is electrically connected to a portion of the gate structure and a portion of the source-drain doping layer, the shared conductive structure includes a second conductive structure and a shared conductive layer 208 located on the second conductive structure, the second conductive structure is electrically connected to a portion of the gate structure and a portion of the source-drain doping layer, a top surface of the shared conductive structure is lower than a top surface of the first conductive structure, the second dielectric layer is located on the first dielectric layer 202, and the second dielectric layer covers the first conductive structure and the shared conductive structure.

In this embodiment, the first conductive structure includes: the first transmission conductive layer 203 is located on the first transmission gate, the transmission conductive plug 204 is located on the first transmission source-drain doping layer, and the second transmission conductive layer 205 is located on the transmission conductive plug 204, wherein the top surface of the first transmission conductive layer 203 is flush with the top surface of the second transmission conductive layer 205.

In this embodiment, the second conductive structure includes: the first pull-up conductive layer 206 is located on the first pull-up gate, the pull-down conductive plug 207 is located on the first pull-down source-drain doped layer, the shared conductive layer 208 is located on the first pull-up conductive layer 206 and the pull-down conductive plug 207, and the top surface of the shared conductive layer 208 is lower than the top surfaces of the first transmission conductive layer 203 and the second transmission conductive layer 205.

In this embodiment, the method for forming the shared conductive structure includes: forming the first pull-up conductive layer 206 in the second dielectric layer 209, wherein the first pull-up conductive layer 206 is in contact with the first pull-up gate; forming a pull-down conductive plug 207 in the second dielectric layer 209, wherein the pull-down conductive plug 207 is in contact with the first pull-down source drain doped layer; forming an initial shared conductive layer (not shown) in the second dielectric layer 209, wherein the initial shared conductive layer is in contact with the first pull-up conductive layer 206 and the pull-down conductive plug 207 respectively, and a top surface of the initial shared conductive layer is flush with a top surface of the first transmission conductive layer 203 and a top surface of the second transmission conductive layer 205; and etching back the initial shared conductive layer to form the shared conductive layer 208, wherein the top surface of the shared conductive layer 208 is lower than the top surfaces of the first transmission conductive layer 203 and the second transmission conductive layer 205.

In this embodiment, after forming the shared conductive layer 208, the method further includes: forming a covering layer 210 on the shared conducting layer 208, wherein the top surface of the covering layer 210 is flush with the top surface of the second dielectric layer 209.

In this embodiment, in the process of forming the first conductive structure and the shared conductive structure, the method further includes: and forming a third conductive structure on the second pull-up transistor PU2, wherein the third conductive structure is positioned in the second dielectric layer 209, and the top surface of the third conductive structure is flush with the top surface of the first conductive structure.

In this embodiment, the third conductive structure includes: a pull-up conductive plug 211 located on the second pull-up source-drain doped layer, and a second pull-up conductive layer 212 located on the pull-up conductive plug 211, wherein the top surface of the second pull-up conductive layer 212 is flush with the top surfaces of the first transmission conductive layer 203 and the second transmission conductive layer 205.

In this embodiment, a first conductive structure and a shared conductive structure are formed, the first conductive structure is electrically connected to a portion of the gate structure and a portion of the source-drain doping layer, the shared conductive structure includes a second conductive structure and a shared conductive layer located on the second conductive structure, the second conductive structure is electrically connected to a portion of the gate structure and a portion of the source-drain doping layer, and a top surface of the shared conductive structure is lower than a top surface of the first conductive structure. Because the top surface of the shared conductive structure is lower than that of the first conductive structure, a subsequently formed power supply conductive layer has a larger forming space, so that the process window of the power supply conductive layer is enlarged, the contact resistance between the power supply conductive layer and the subsequently formed second pull-up conductive layer is reduced, and the performance of the static random access memory is effectively improved.

Referring to fig. 13 to 15, fig. 13 is a top view of a static random access memory without a first dielectric layer, a second dielectric layer and a third dielectric layer, fig. 14 is a schematic cross-sectional view taken along line F-F and without a first transfer transistor in fig. 13, fig. 15 is a schematic cross-sectional view taken along line G-G and without a first pull-up transistor and a second pull-up transistor in fig. 13, after the first conductive structure and the shared conductive structure are formed, a third dielectric layer 213 and a fourth conductive structure are formed, the third dielectric layer 213 is located on the second dielectric layer 209, the fourth conductive structure is located in the third dielectric layer 213, and the fourth conductive structure is electrically connected to the first conductive structure and the third conductive structure, respectively.

In this embodiment, the fourth conductive structure includes: a word line layer 214, the word line layer 214 being electrically connected with the first conductive transmission layer 203; a bit line layer 215, the bit line layer 215 being electrically connected to the second transfer conductive layer 205; a power conductive layer 216, the power conductive layer 216 extending along the first direction X, and the power conductive layer 216 electrically connected with the second pull-up conductive layer 212.

In this embodiment, since the top surface of the shared conductive structure is lower than the top surface of the first conductive structure, the formed power conductive layer 216 has a larger forming space, and the size of the power conductive layer 16 in the first direction X may be equal to the size of the first pull-up channel layer in the first direction, so as to increase the process window of the power conductive layer 216, reduce the contact resistance between the power conductive layer 16 and the second pull-up conductive layer 212 formed subsequently, and effectively improve the performance of the sram.

Accordingly, an embodiment of the present invention further provides a static random access memory, please continue to refer to fig. 13 to fig. 15, including: a substrate 200; a plurality of static random access memory cells on the substrate 200, the static random access memory cells including a plurality of channel layers, a plurality of gate structures, and a plurality of source-drain doped layers; a first dielectric layer 202 on the substrate 200, wherein the first dielectric layer 202 covers the sram cells and exposes top surfaces of a plurality of gate structures in the sram cells; the first conductive structure is electrically connected with part of the grid structure and part of the source-drain doping layer; the shared conductive structure comprises a second conductive structure and a shared conductive layer 208 positioned on the second conductive structure, the second conductive structure is electrically connected with part of the gate structure and part of the source-drain doping layer, and the top surface of the shared conductive structure is lower than that of the first conductive structure; a second dielectric layer 209 located on the first dielectric layer 202, the second dielectric layer 209 covering the first conductive structure and the shared conductive structure.

In this embodiment, since the top surface of the shared conductive structure is lower than the top surface of the first conductive structure, the power conductive layer 216 has a larger forming space, so as to increase the process window of the power conductive layer 216, reduce the contact resistance between the power conductive layer 216 and the second pull-up conductive layer 212, and effectively improve the performance of the sram.

In this embodiment, the sram cell includes: a first pass transistor PG1, a first pull-up transistor PU1, and a first pull-down transistor PD1.

In this embodiment, several of the channel layers include: a first transmission channel layer, a first pull-up channel layer and a first pull-down channel layer; a plurality of the gate structures include: the first transmission grid, the first pull-up grid and the first pull-down grid; the plurality of source-drain doped layers comprise: the first transmission source-drain doped layer, the first pull-up source-drain doped layer and the first pull-down source-drain doped layer.

In this embodiment, the first transfer transistor PG1 includes: the first transmission channel layer, the first transmission grid structure crossing over the first transmission channel layer and the first transmission source-drain doping layers located on two sides of the first transmission grid are arranged in the first transmission channel layer; the first pull-up transistor PU1 includes: the first pull-up channel layer, a first pull-up gate structure crossing over the first pull-up channel layer and first pull-up source drain doping layers positioned on two sides of the first pull-up gate, wherein the first pull-up source drain doping layers are positioned in the first pull-up channel layer; the first pull-down transistor PD1 includes: the semiconductor device comprises a first pull-down channel layer, a first pull-down gate structure stretching across the first pull-down channel layer, and first pull-down source-drain doped layers located on two sides of the first pull-down gate, wherein the first pull-down source-drain doped layers are located in the first pull-down channel layer.

In this embodiment, the first conductive structure includes: the first transmission conductive layer 203 is located on the first transmission gate, the transmission conductive plug 204 is located on the first transmission source drain doping layer, and the second transmission conductive layer 205 is located on the transmission conductive plug 204, and the top surface of the first transmission conductive layer 203 is flush with the top surface of the second transmission conductive layer 205.

In this embodiment, the method further includes: a capping layer 210 located on the shared conductive structure, a top surface of the capping layer 210 being flush with a top surface of the second dielectric layer 209.

In this embodiment, the plurality of channel layers further includes: a second pull-up channel layer; a plurality of the gate structures further comprising: a second pull-up gate; the plurality of source-drain doped layers further comprise: and a first pull-up source drain doped layer.

In this embodiment, the sram cell further includes: a second pull-up transistor PU2, the second pull-up transistor PU2 comprising: the second pull-up channel layer, a second pull-up grid stretching over the second pull-up channel layer and second pull-up source drain doping layers located on two sides of the second pull-up grid are arranged, and the second pull-up source drain doping layers are located in the second pull-up channel layer.

In this embodiment, the method further includes: and a third conductive structure located on the second pull-up transistor PU2, the third conductive structure being located within the second dielectric layer 209, and a top surface of the third conductive structure being flush with a top surface of the first conductive structure.

In this embodiment, the method further includes: the third dielectric layer 213 is located on the second dielectric layer 209, the fourth conductive structure is located in the third dielectric layer 213, and the fourth conductive structure is electrically connected to the first conductive structure and the third conductive structure, respectively.

In this embodiment, the fourth conductive structure includes: a word line layer 214, the word line layer 214 being electrically connected to the first conductive layer 203; a bit line layer 215, the bit line layer 215 being electrically connected to the second transfer conductive layer 205; a power conductive layer 216, the power conductive layer 216 extending along the first direction X, and the power conductive layer 216 electrically connected with the second pull-up conductive layer 212.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A static random access memory, comprising:

a substrate;

the static random access memory unit comprises a plurality of channel layers, a plurality of grid structures and a plurality of source-drain doping layers;

the first dielectric layer is positioned on the substrate, covers the static random access memory unit and exposes the top surfaces of a plurality of grid structures in the static random access memory unit;

the first conductive structure is electrically connected with part of the grid structure and part of the source-drain doping layer;

the shared conductive structure comprises a second conductive structure and a shared conductive layer positioned on the second conductive structure, the second conductive structure is electrically connected with part of the grid structure and part of the source-drain doped layer, and the top surface of the shared conductive structure is lower than that of the first conductive structure;

a second dielectric layer on the first dielectric layer, the second dielectric layer covering the first conductive structure and the shared conductive structure.

2. The sram of claim 1, wherein the sram cell comprises: a first pass transistor, a first pull-up transistor, and a first pull-down transistor.

3. The static random access memory of claim 2 wherein the number of channel layers comprises: a first transmission channel layer, a first pull-up channel layer and a first pull-down channel layer; a plurality of the gate structures include: the first transmission grid, the first pull-up grid and the first pull-down grid; the plurality of source-drain doped layers comprise: the first transmission source-drain doped layer, the first pull-up source-drain doped layer and the first pull-down source-drain doped layer.

4. The sram of claim 3, wherein the first pass transistor comprises: the first transmission channel layer, the first transmission grid structure crossing over the first transmission channel layer and the first transmission source-drain doping layers located on two sides of the first transmission grid are arranged in the first transmission channel layer; the first pull-up transistor includes: the first pull-up channel layer, a first pull-up gate structure crossing over the first pull-up channel layer and first pull-up source drain doping layers positioned on two sides of the first pull-up gate, wherein the first pull-up source drain doping layers are positioned in the first pull-up channel layer; the first pull-down transistor includes: the semiconductor device comprises a first pull-down channel layer, a first pull-down gate structure stretching across the first pull-down channel layer, and first pull-down source-drain doped layers located on two sides of the first pull-down gate, wherein the first pull-down source-drain doped layers are located in the first pull-down channel layer.

5. The static random access memory of claim 4 wherein said first conductive structure comprises: the first transmission conductive layer is positioned on the first transmission grid electrode, the transmission conductive plug is positioned on the first transmission source-drain doping layer, the second transmission conductive layer is positioned on the transmission conductive plug, and the top surface of the first transmission conductive layer is flush with the top surface of the second transmission conductive layer.

6. The static random access memory of claim 5 wherein said second conductive structure comprises: the shared conductive layer is positioned on the first pull-up conductive layer and the pull-down conductive plug, and the top surface of the shared conductive layer is lower than the top surfaces of the first transmission conductive layer and the second transmission conductive layer.

7. The static random access memory of claim 1, further comprising: a capping layer on the shared conductive structure, a top surface of the capping layer being flush with a top surface of the second dielectric layer.

8. The static random access memory of claim 5 wherein said plurality of channel layers further comprises: a second pull-up channel layer; a plurality of the gate structures further comprising: a second pull-up gate; the plurality of source-drain doped layers further comprise: and a first pull-up source drain doped layer.

9. The sram of claim 8, wherein the sram cell further comprises: a second pull-up transistor, the second pull-up transistor comprising: the second pull-up channel layer, the second pull-up grid stretching over the second pull-up channel layer and the second pull-up source drain doping layers located on two sides of the second pull-up grid are arranged, and the second pull-up source drain doping layers are located in the second pull-up channel layer.

10. The static random access memory of claim 9, further comprising: a third conductive structure on the second pull-up transistor, the third conductive structure being within the second dielectric layer, and a top surface of the third conductive structure being flush with a top surface of the first conductive structure.

11. The static random access memory of claim 10 wherein said third conductive structure comprises: the second pull-up conductive layer is positioned on the pull-up conductive plug, and the top surface of the second pull-up conductive layer is flush with the top surface of the first transmission conductive layer and the top surface of the second transmission conductive layer.

12. The static random access memory of claim 11, further comprising: the third dielectric layer is positioned on the second dielectric layer, the fourth conductive structure is positioned in the third dielectric layer, and the fourth conductive structure is electrically connected with the first conductive structure and the third conductive structure respectively.

13. The static random access memory of claim 12 wherein the fourth conductive structure comprises: a word line layer electrically connected to the first conductive transmission layer; a bit line layer electrically connected with the second transmission conductive layer; a power conductive layer extending along the first direction, and electrically connected with the second pull-up conductive layer.

14. A method for forming a Static Random Access Memory (SRAM), comprising:

providing a substrate;

forming a plurality of static random access memory units and a first dielectric layer on the substrate, wherein each static random access memory unit comprises a plurality of channel layers, a plurality of grid structures and a plurality of source-drain doping layers, and the first dielectric layer covers the static random access memory units and exposes the top surfaces of the grid structures in the static random access memory units;

and forming a second dielectric layer, a first conductive structure and a shared conductive structure, wherein the first conductive structure is electrically connected with part of the gate structure and part of the source-drain doping layer, the shared conductive structure comprises a second conductive structure and a shared conductive layer positioned on the second conductive structure, the second conductive structure is electrically connected with part of the gate structure and part of the source-drain doping layer, the top surface of the shared conductive structure is lower than that of the first conductive structure, the second dielectric layer is positioned on the first dielectric layer, and the second dielectric layer covers the first conductive structure and the shared conductive structure.

15. The method of claim 14 wherein the sram cell comprises: a first pass transistor, a first pull-up transistor, and a first pull-down transistor.

16. The method of claim 15, wherein the plurality of channel layers comprises: a first transmission channel layer, a first pull-up channel layer and a first pull-down channel layer; a number of the gate structures include: the first transmission grid, the first pull-up grid and the first pull-down grid; the plurality of source-drain doped layers comprise: the first transmission source-drain doped layer, the first pull-up source-drain doped layer and the first pull-down source-drain doped layer.

17. The method of claim 16, wherein the first pass transistor comprises: the first transmission channel layer, the first transmission grid structure crossing over the first transmission channel layer and the first transmission source-drain doping layers located on two sides of the first transmission grid are arranged in the first transmission channel layer; the first pull-up transistor includes: the first pull-up channel layer, a first pull-up gate structure crossing over the first pull-up channel layer and first pull-up source drain doping layers positioned on two sides of the first pull-up gate, wherein the first pull-up source drain doping layers are positioned in the first pull-up channel layer; the first pull-down transistor includes: the semiconductor device comprises a first pull-down channel layer, a first pull-down gate structure stretching across the first pull-down channel layer, and first pull-down source-drain doped layers located on two sides of the first pull-down gate, wherein the first pull-down source-drain doped layers are located in the first pull-down channel layer.

18. The method of claim 17, wherein the first conductive structure comprises: the first transmission conductive layer is positioned on the first transmission grid electrode, the transmission conductive plug is positioned on the first transmission source-drain doping layer, the second transmission conductive layer is positioned on the transmission conductive plug, and the top surface of the first transmission conductive layer is flush with the top surface of the second transmission conductive layer.

19. The method of claim 18, wherein the second conductive structure comprises: the shared conductive layer is positioned on the first pull-up conductive layer and the pull-down conductive plug, and the top surface of the shared conductive layer is lower than the top surfaces of the first transmission conductive layer and the second transmission conductive layer.

20. The method of claim 19, wherein the shared conductive structure is formed by: forming the first pull-up conducting layer in the second dielectric layer, wherein the first pull-up conducting layer is in contact with the first pull-up gate; forming a pull-down conductive plug in the second dielectric layer, wherein the pull-down conductive plug is in contact with the first pull-down source drain doped layer; forming an initial shared conductive layer in the second dielectric layer, wherein the initial shared conductive layer is respectively contacted with the first pull-up conductive layer and the pull-down conductive plug, and the top surface of the initial shared conductive layer is flush with the top surface of the first transmission conductive layer and the top surface of the second transmission conductive layer; and etching back the initial shared conducting layer to form the shared conducting layer, wherein the top surface of the shared conducting layer is lower than the top surface of the first transmission conducting layer and the top surface of the second transmission conducting layer.

21. The method of forming the sram of claim 14, further comprising, after forming the shared conductive layer: and forming a covering layer on the shared conductive structure, wherein the top surface of the covering layer is flush with the top surface of the second dielectric layer.

22. The method of forming a static random access memory of claim 18 wherein said plurality of channel layers further comprises: a second pull-up channel layer; a plurality of the gate structures further comprising: a second pull-up gate; the plurality of source-drain doped layers further comprise: and a first pull-up source drain doped layer.

23. The method of forming the sram of claim 22, wherein the sram cell further comprises: a second pull-up transistor, the second pull-up transistor comprising: the second pull-up channel layer, a second pull-up grid stretching over the second pull-up channel layer and second pull-up source drain doping layers located on two sides of the second pull-up grid are arranged, and the second pull-up source drain doping layers are located in the second pull-up channel layer.

24. The method of forming a static random access memory of claim 23, wherein in forming the first conductive structure and the shared conductive structure, further comprising: forming a third conductive structure on the second pull-up transistor, the third conductive structure being located within the second dielectric layer, and a top surface of the third conductive structure being flush with a top surface of the first conductive structure.

25. The method of claim 24, wherein the third conductive structure comprises: the second pull-up conductive layer is positioned on the pull-up conductive plug, and the top surface of the second pull-up conductive layer is flush with the top surface of the first transmission conductive layer and the top surface of the second transmission conductive layer.

26. The method of forming the sram of claim 25, further comprising, after forming the first conductive structure and the shared conductive structure: and forming a third dielectric layer and a fourth conductive structure, wherein the third dielectric layer is positioned on the second dielectric layer, the fourth conductive structure is positioned in the third dielectric layer, and the fourth conductive structure is respectively and electrically connected with the first conductive structure and the third conductive structure.

27. The method of claim 26, wherein the fourth conductive structure comprises: a word line layer electrically connected to the first conductive transmission layer; a bit line layer electrically connected with the second transmission conductive layer; a power conductive layer extending along the first direction, and electrically connected with the second pull-up conductive layer.