WO2002089213A1

WO2002089213A1 - Integrated circuit and method for manufacture thereof

Info

Publication number: WO2002089213A1
Application number: PCT/IB2002/001090
Authority: WO
Inventors: Joachim C. Reiner; Paul G. M. Gradenwitz
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2001-04-11
Filing date: 2002-04-02
Publication date: 2002-11-07

Abstract

The present invention relates to an integrated circuit which comprises a number of static memory cells with a flip-flop circuit and a high-ohmic layer which is incorporated in the integrated circuit as load for the transistors of the flip-flop circuit, wherein the resistive layer is directly connected to a contact of one of the transistors.

Description

INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURE THEREOF

In portable equipment, such as telephones, dimensions and a low power consumption are of increasing importance. Portable telephones constantly require more functionality including a processor, integrated circuits with memory, power supply and also extended memory space. The present invention has for its object to provide memory of small dimensions, which therefore enables more functionality for portable equipment.

The present invention provides an integrated circuit (IC) which comprises a number of static memory cells with a flip-flop circuit and a high-ohmic layer which is incorporated in the integrated circuit as load for the transistors of the flip-flop circuit, wherein the resistive layer is directly connected to a contact of one of the transistors.

The integrated circuit can become more compact due to the direct connection of the resistive layer to a contact of one of the transistors.

For mobile devices, such as cellular phones, organizers etc, ICs with increasing processing power are required for better performance, to be able to run more and better software, which requires CMOS (Complementary Metal Oxide Semiconductor) processes with smaller dimensions and higher operating speed. At the same time, the number of components in a telephone have to be reduced for cost and space reasons. To run software, RAM (Random Access Memories) are required in addition to microprocessors. An important step to reduce the number of components is to integrate a microprocessor, and memory, (and even other functionality) onto a single chip. Standard CMOS technologies are not optimized for memories. In a standard CMOS process, SRAMs can be realized, however, with relatively large cell sizes, if the layout rules of a CMOS process used for logic products are maintained. A dedicated SRAM technology that can deliver a very small SRAM cell needs special process steps and will be less optimal for realizing a microprocessor. An advantage of the invention is related to adding as little process steps as possible to a CMOS process for logic products to limit additional costs and/or achieve a significant SRAM cell size reduction. While a standard CMOS process required six transistors to realize an SRAM cell, the number of transistors is reduced to four by adding a high-resistive layer, which reduces the cell area. The high resistive layer is used to form load resistors. They are physically placed on top of the transistor.

An aspect of the invention is to modify as few process steps of the standard CMOS process as possible, in order to be able to use the same libraries and microprocessor designs having the small SRAMs at the same time. It is an important advantage to be able to use the same logic library and micro-core as otherwise high costs for new designs would arise.

The resistive layer preferably extends into a contact region such that the contact for the transistor is arranged and in contact with said layer. A contact plug thus makes contact with three layers, i.e. the source or drain of a MOSFET, the resistive layer and a metal layer located thereabove. Polysilicon lightly doped with phosphor (P) is preferably in the resistive layer. It is of further importance that the contact plug makes contact on two sides i.e. both on the upper side and on the end wall of the resistive layer, since the contact plugs are arranged after selective etching has taken place, wherein atoms or molecules could sputter mainly against the end wall of such a layer. Thus ensured according to the preferred embodiment is that good contact is made, which reduces failure of such integrated circuits.

The present invention further provides a method for manufacturing an integrated circuit, wherein source drain and gate of a static RAM are arranged in an epitaxial layer of a substrate, wherein the relatively thin layer of oxide is arranged over source and drain, wherein a highly resistive layer of polysilicon is then arranged, a thin oxide layer is subsequently arranged, a contact plug is then arranged which makes contact with the thin resistive layer, source or drain region and a metal conducting layer to be arranged thereafter. The resistive layer can be arranged in existing processes with only few modifications, i.e. first of all only half the thickness of the insulation layer is deposited before the resistive layer is deposited, whereafter the second half of the insulation layer can be arranged. As in existing (CMOS) processes, the insulation layers together then preferably could have a thickness of 800 nm.

In particular , the deposition of the Inter Layer Dielectric (ILD) between the polysilicon layer (gates) and the first metal layer is replaced by:

1. deposition of a dielectric

2. deposition of a polysilicon layer with low doping level such that it has a very high sheet resistance, typically a few 100 kOhm/square,

3. a photo step to structure this polysilicon layer 4. deposition of another dielectric.

In order to limit necessary changes as far as possible, the total thickness of this dielectric - poly - dielectric stack should be the same as the thickness of the original dielectric layer. This way, the subsequent processing steps need the smallest if any adaption. To limit topology effects between regions with and without the high-ohmic polysiliocon layer, this layer has to be very thin, typically about 100 nanometers. The poly layer on the other hand must not be too thin in order to avoid that the contact etching step etches through resulting in bad contact quality between the contact plug (tungsten) and the high-resistive poly layer. The resistivity of the high-ohmic layer has to be very high because in the four-transistor CMOS cell, always one of the transistors is conducting, and the standby current of the cell is determined by the load resistor. If the resistor is too high, the cell does not work anymore, an optimum existing between stability of cell operation and standby current.

The cell size resulting from this approach will still be larger compared to a fully optimized SRAM process. However, the cell size has to be compared to a six-transistor cell which would be the alternative that could be integrated together with a microprocessor onto the same chip in a standard CMOS process. The advantages to have microprocessor and SRAM on one chip compared to two separate chips are:

1. reduced number of Input/Output (IO) pads saving silicon area,

2. higher data transfer speed between SRAM and microprocessor, as no pads, bond wires etc. are in between,

3. reduced power consumption resulting from the fact that no pads, bond wires etc. have to be charged and decharged when data are transferred,

4. reduced number of packages reducing significant costs,

5. increase deliability as less pads, bond, solder joints etc. are needed.

Further advantages, features and details of the present invention will be elucidated on the basis of the following description of a preferred embodiment thereof with reference to the annexed drawings, in which: Fig. 1 shows a circuit diagram of two SRAM cells according to the present invention;

Fig. 2 shows a layout of the SRAM cell shown in Fig. 1; and

Fig. 3 shows a cross-section over atypical part of a CMOS layout equivalent to Fig. 2. A Static Random Access Memory (SRAM) cell comprises transistors TrT₄ and resistors K\ and R₂ which are arranged between bit lines BL and B L , voltage level V_DD and Nss and a word line WL. Transistors T₂ and T₃ are connected as flipflop. Transistors T_\ and T are generally referred to as select (or drive) transistors.

The WL selects the cell by opening the select transistor T] and T . The bit line either delivers the data for writing, or senses the cell content for reading. The cell is made such that it shares BL (17, 23) and NSS (12, 25) contacts with neighboring cells (Fig. 2). The metal layers for BC, WL, BL and ΝSS are omitted for clarity reasons.

Transistor T_t (Fig. 2) comprises source and drain contact regions 11 and 12 and a so called active region 13 over which extends the gate 14 with gate contact region 15. Transistor T₂ has an active region 16 which extends between drain contact region 11 and source contact region 17. The gate 18, which is connected via gate contact region 19, extends over active region 16.

Transistor T₃ thus comprises a gate contact region 20 and a gate 21 which extends over an active region 22 which can be connected via source and drain contact regions 23 and 24. This latter contact region 24 also forms part of transistor T₄, which further comprises a source or drain contact region 25, an active region 26, a gate contact region 27 and a gate 28. Further connected to channel contact regions 24 and 11 are resistors R respectively R which are connected to the voltage V_DD via contact region 30 in a manner not further shown. The connections of transistors T{ - T₄ to the bit lines B L , word line WL and voltage Nss situated at a higher level are not shown either in the layout of Fig. 2 for the sake of clarity. Arranged on a substrate 40 is in Fig. 3 an epitaxial layer 1 in which Ν⁺ regions 42 and 43 are defined and on which a thin oxide layer 44 and a gate 45 of polycrystalline silicon are arranged. An SIO₂ oxide layer 39 is arranged to the side of regions 42 and 43. Over the structure is then deposited an oxide layer 38, for instance with a thickness of half a usual thickness, for instance about 400 nm instead of 800 nm. A thin resistive layer 46 in the order of magnitude of 10-200 nm in thickness is then arranged, for instance from polycrystalline silicon with a phosphor doping of 10 atoms per cm³. An oxide layer 37 is then arranged thereover, whereafter contact plugs 47 and 48, for instance of tungsten (W), are arranged therein after selective etching. Tungsten contacts are then connected to metal strips 49 and 50 which can be manufactured from for instance aluminum or other conductive material.

Although the integrated circuit according to the present invention can be manufactured by means of NMOS and PMOS technology, CMOS is preferably used as this is the dominant technology for microprocessor fabrication. According to this process after well formation the sacrificial oxide is formed, whereafter the gate oxide is arranged. Thereafter the gate polysilicon is deposited doped and structured. Thereafter a first Inter Layer Dielectric (ILD) is deposited for instance with the thickness of about 400 nm. Thereafter the high ohmic polysilicon layer is deposited doped and structured, whereafter a second ILD is deposited, again having a thickness of about 400 nm. Thereafter planarisation, a plasma anisotropical contact etching step, the filling of contact holes with tungsten as conducting material and deposition and structuring of a first metal layer (aluminum) takes place.

Contrary to existing processes, the inter layer dielectric step is divided and deposition, doping and structuring of a high-ohmic polisilicon layer is introduced. In the layout given in Fig. 3 a process having 0.35 μm gate length is provided while newer processes use 0.18 or 0.12 μm as gate length for the design. Although further reducing in size could be obtained, such reductions would violate the specific rule of a CMOS base process which would complicate other aspects of the integrated circuit. In not shown embodiments making use of a different manufacturing technologies the transistors can be placed onto the substrate, avoiding the epitaxial layer - for higher resistance even lower doping levels can be used.

In the above outlined preferred embodiment source and drain are arranged in epitaxial layers via diffusion. The oxide layers are deposited, while the contact plug is arranged after selective etching. In this selective etching some material could deposit against an end wall of the resistive layer. Owing to the widening of the contact plug above the resistive layer, good contact therewith is ensured according to the preferred embodiment.

A SRAM cell according to the above preferred embodiment as indicated by the outer broken lines in Fig. 2 can have dimensions of about 3.1 x 3.2 (μm)² (or less). The present invention is not limited to the above described preferred embodiment thereof; the rights sought are defined by the following claims, within the scope of which many modifications can be envisaged.

Claims

CLAIMS:

1. Integrated circuit which comprises a number of static memory cells with a flip-flop circuit and a high-ohmic layer which is incorporated in the integrated circuit as load for the transistors of the flip-flop circuit, wherein the resistive layer is directly connected to a contact of one of the transistors.

2. Integrated circuit as claimed in claim 1, wherein the resistive layer extends into a contact region such that the contact for the transistor is arranged on and in contact with two sides of this layer.

3. Integrated circuit according to claim 1 or 2 further comprising a processor in connection with the memory cells.

4. Portable telephone provided with an integrated circuit as claimed in any of claims 1-3.

5. Method for manufacturing an integrated circuit, wherein source, drain and gate of a static RAM are arranged in an epitaxial layer of a substrate, wherein the relatively thin layer of oxide is arranged over source and drain, wherein a highly resistive layer of polysilicon is then arranged, a thin oxide layer is subsequently arranged, a contact plug must then be arranged which makes contact with the thin resistive layer, source or drain region, and a metal conducting layer to be arranged thereafter.

6. Method as claimed in claim 5, wherein the two thin insulation layers together have a thickness of about 800 nm.

7. Method as claimed in claim 5 or 6, wherein the method steps are MOS process steps, preferably CMOS process steps.