CN115695878A

CN115695878A - SPI-based communication system

Info

Publication number: CN115695878A
Application number: CN202211322781.7A
Authority: CN
Inventors: 王安良; 肖昊
Original assignee: Beijing Huajian Yunding Technology Co ltd
Current assignee: Beijing Huajian Yunding Technology Co ltd
Priority date: 2022-10-27
Filing date: 2022-10-27
Publication date: 2023-02-03
Anticipated expiration: 2042-10-27
Also published as: CN115695878B

Abstract

The invention relates to a communication system based on SPI, comprising a first FPGA module, a first ARM module, a processing module arranged on FPGA, a memory storing computer programs and a processor, wherein the first FPGA module comprises an FPGA register; the first FPGA module is connected with the first ARM module through a TSI (serial peripheral interface) and an SPI (serial peripheral interface), the TSI is used for transmitting data between the first FPGA module and the first ARM module, the SPI is used for transmitting a control command between the first FPGA module and the first ARM module, and the control command is generated based on a preset SPI data structure; the preset SPI data structure comprises a read-write identification data segment, a read-write target data segment, a read-write type data segment, a target address data segment and a target information data segment. The invention improves the communication efficiency between the first FPGA module and the first ARM module.

Description

SPI-based communication system

Technical Field

The invention relates to the technical field of communication, in particular to a communication system based on SPI.

Background

Many existing signal processing devices are realized based on specific chips, so that the flexibility of a signal processing process is poor, the cost is high, and autonomous controllability cannot be realized.

For example, a satellite receiver is a device that receives a satellite signal, descrambles and decrypts the signal, and then forwards the signal through a line. The satellite receiver is usually provided with a module for descrambling and decrypting satellite signals, the structure of the existing satellite receiver is usually realized by adopting an interface chip of CIMAX and an EMIF interface mechanism of specific chips such as TI-DM642, the CIMAX chip and the TI-DM642 chip are connected through an I2C interface, initialization is carried out based on the I2C interface, the initialization efficiency is low, satellite signals which can only be obtained from a PCMCIA interface can be output after scrambling and decryption, signal input sources cannot be selected, the flexibility is poor, and the communication efficiency is low. The output section of the satellite receiver typically implements asynchronous serial output based on a particular FPGA in conjunction with a corresponding ASI _ IP core. In addition, the interface chip of the CIMAX, the TI-DM642 chip, the specific FPGA based chip combined with the corresponding specific chip such as the ASI _ IP core and the like cause the existing satellite receiver to have limitations, high cost and incapability of realizing autonomous controllability.

The satellite receiver can output an ASI signal, the existing other signal processing equipment can also directly process unencrypted and unscrambled video to generate the ASI signal, but the ASI signal is also realized based on a specific FPGA and a corresponding ASI _ IP core, has the advantages of limitation, high cost and incapability of realizing autonomous control, and the satellite receiver or other signal processing equipment can output a plurality of paths of ASI signals.

After the multiple ASI signals are output, radio Frequency (RF) signals are generated and output through the ASI modulation. With the development of modern communication technology, especially the high-speed development of mobile communication technology, new requirements emerge endlessly, which promotes new services to be generated continuously, resulting in more and more tense frequency resources, a large amount of multimedia data needs to be transmitted within a limited bandwidth, and it is important to improve the spectrum utilization rate. Due to the advantages of high spectrum utilization rate, high power spectrum density, etc., quadrature Amplitude Modulation (QAM for short) is widely used in high-speed data transmission systems. The existing modulation of multiple paths of ASI signals also adopts a QAM modulation technology, but the existing modulation method only adopts a specific chip to modulate each path of ASI signal independently and then combine the ASI signals, so that the modulation efficiency is low, and the adoption of the specific chip has high cost and limitation, and autonomous controllability cannot be realized.

Disclosure of Invention

The invention aims to provide a communication system based on SPI, which improves the communication efficiency between a first FPGA module and a first ARM module.

The invention provides a communication system based on SPI, which comprises a first FPGA module, a first ARM module, a processing module arranged on FPGA, a memory storing a computer program and a processor, wherein the first FPGA module comprises an FPGA register;

the first FPGA module is connected with the first ARM module through a TSI interface and an SPI interface, the TSI interface is used for transmitting data between the first FPGA module and the first ARM module, the SPI interface is used for transmitting a control command between the first FPGA module and the first ARM module, and the control command is generated based on a preset SPI data structure;

the preset SPI data structure comprises a read-write identification data segment, a read-write target data segment, a read-write type data segment, a target address data segment and a target information data segment, wherein the read-write identification data segment is used for storing read-write identification, the read-write target data segment is used for storing read-write target identification, and the read-write target comprises an FPGA register or a processing module arranged on the FPGA; the read-write type comprises a processing module universal storage read-write identifier, a processing module attribute storage read-write identifier, a processing module IO read-write identifier and an empty identifier; the target address data segment is used for storing target address information, and the target information data segment is used for storing target information;

when the processor executes the computer program, the following steps are implemented:

d1, the first ARM module generates a target control command based on the preset SPI data structure;

d2, the first ARM module transmits the target control command to an FPGA register through the SPI interface;

d3, the first FPGA module analyzes the target control command from the FPGA register to obtain a read-write identifier, a read-write target, a read-write type, target address information and target information, if the read-write identifier is read, the step D4 is executed, and if the read-write identifier is write, the step D5 is executed;

step D4, the first FPGA module acquires corresponding target reading data from target address information corresponding to the read-write target according to the read-write type, and returns the target reading data to the first ARM module through the TSI;

and D5, the first FPGA module writes the target information into target address information corresponding to the read-write target according to the read-write type.

Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the SPI-based communication system can achieve considerable technical progress and practicability, has wide industrial utilization value and at least has the following advantages:

according to the invention, the target control command is generated through a preset SPI data structure and is sent to the FPGA register, the first FPGA module executes corresponding read-write operation by reading and analyzing the target control command received by the FPGA register, the corresponding target control command can be flexibly generated according to specific control requirements, and the communication efficiency between the first FPGA module and the first ARM module is improved.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.

Drawings

Fig. 1 is a schematic diagram of a satellite signal processing system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an SPI-based communication system architecture according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a satellite signal receiver architecture according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a video signal processing system according to an embodiment of the present invention;

fig. 5 is a flow chart of processing multiple ASI signals according to an embodiment of the present invention.

Detailed Description

To further explain the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description is given according to the preferred embodiments with reference to the accompanying drawings.

In order to avoid the limitation of the core chip in the signal processing system to a specific chip, the present application provides a plurality of signal processing systems built based on a general-purpose FPGA (Field-Programmable Gate Array) and an ARM processor to improve the signal processing efficiency and reduce the signal processing cost, and each of the signal processing systems provided in the present application is described in detail below.

The first embodiment,

In one embodiment, a satellite signal processing system is provided, as shown in fig. 1, including a signal preprocessing module, M decryption descrambling modules { C } ₁ ，C ₂ ，…,C _M A first FPGA module, a first ARM module, a first signal output module, a memory (not shown in fig. 1) storing a computer program, and a processor (not shown in fig. 1). Wherein, the signal preprocessing module and the signal preprocessing module C _i The FPGA module is connected with the first ARM module, and the first signal output module is arranged on the first ARM module. C _i For the ith decryption and descrambling module, the value of i ranges from 1 to M, where M is the number of decryption and scrambling modules, and for example, M may be equal to 2.

When the computer program is executed by the processor, the following steps are implemented:

step S1, a satellite signal to be processed is obtained through the signal preprocessing module and is preprocessed to generate a first Transport Stream (TS) Stream, wherein the satellite signal to be processed is an encrypted and scrambled satellite signal.

The TS stream refers to a TS stream file, and is a file format of a DVD.

S2, the first ARM module generates a first target route control command based on the acquired first route configuration information, and sends the first target route control command to the first FPGA module.

It should be noted that the system may include a display interface, and receive, through the display interface, the first routing configuration information input by the user, where the first routing configuration information may be flexibly configured according to a specific application requirement.

S3, the first FPGA module sends the first TS stream to at least one first target C based on the first target routing control command _i And directly or through the first target C _i And sending the first TS stream to the first ARM module.

It should be noted that the first TS stream is sent to at least one first target C based on the first target route control command _i And directly or through the first target C _i The first TS stream is sent to the first ARM module, the first TS stream may be operated in the system first, but it is understood that the first TS stream circulated in this stage is encrypted and scrambled, and cannot be directly played.

And S4, the first ARM module extracts first target program information from the first TS, generates a first CI protocol stack and sends the first CI protocol stack to the first FPGA module.

It should be noted that the first TS stream includes multiple programs, but the system may only focus on a part of the multiple programs, not all of the multiple programs, and if all of the multiple programs are decrypted and descrambled, a large amount of system resources are consumed, and the signal processing efficiency of the system is reduced.

S5, the first FPGA module forwards the first CI protocol stack to at least one second target C _i The second target C _i Belonging to a first object C _i And (4) collecting.

It should be noted that, based on the routing information flexibly configured in step S2 and step S3, the first TS stream can be flexibly sent to multiple first targets C _i In the step (1)S5 can be further flexible from the first target C _i To select one or more second targets C _i To perform an operation of extracting target program information.

Step S6, the second target C _i And analyzing a target clear stream from the first TS stream based on the received first CI protocol stack, and sending the target clear stream to a first FPGA module, wherein the target clear stream is a data stream subjected to decryption and descrambling.

It will be appreciated that the second target C _i The target purge can be extracted based on the first CI protocol stack for one or more. It should be noted that all the existing ways of generating the first CI protocol stack fall within the scope of the present invention, and are not described herein again.

And S7, the first FPGA module sends the target clear stream to an upper first signal output module of the first ARM module for output.

As an embodiment, the first FPGA module is connected to the first ARM module through a TSI (TS immediate) Interface and a Serial Peripheral Interface (SPI for short), the TSI Interface is used for transmitting data between the first FPGA module and the first ARM module, and the SPI Interface is used for transmitting commands between the first FPGA module and the first ARM module. Based on this, in the step S2, the first ARM module sends the first target routing control command to the first FPGA module through the SPI interface. In step S3, the first FPGA module sends the first TS stream to the first ARM module through the TSI interface. In step S5, the first FPGA module forwards the first CI protocol stack to at least one second target C through the SPI interface _i . In the step S7, the first FPGA module sends the target clear stream to the first signal output module of the first ARM module through the TSI interface for output.

As an embodiment, in step S2, the generating, by the first ARM module, the first target route control command based on the obtained first route configuration information includes:

s21, the first ARM module acquires a first pathThe first routing configuration information includes at least one first data flow direction path information, the first data flow direction path information includes a first data sending module and a first data receiving module, and the first data sending module is the preprocessing module or C _i The first data receiving module is C _i Or a first ARM module.

Wherein the first data stream path information may be directly input by a user through the display interface based on the display interface.

And step S22, generating the first target route control command based on the first data flow direction path information.

As an embodiment, the first TS stream includes N Program information, a PAT (Program Association Table) Table and N PMT (Program Map Table) tables, the PAT Table is a Program Association Table, the PMT Table is a Program information Table, each Program information corresponds to one PMT Table, the Program information includes Program ID, video data and audio data corresponding to each Program information, each video data corresponds to one video PID, each audio data corresponds to one audio PID, and both ID and PID are identification information, and the step S4 includes:

step S41, a first target program information extraction instruction is obtained, wherein the first target program information extraction instruction comprises a first target program ID.

The first target program ID may also be directly input by the user through the display interface based on the display interface, or may be set by the system.

And step S42, acquiring all first target associated program IDs and corresponding first target PMT table IDs from the PAT table based on the first target program IDs.

And S43, acquiring the video PID and the audio PID corresponding to the first target associated program ID from the corresponding PMT table based on the first target PMT table ID.

And step S44, generating the first CI protocol stack based on the first target PMT table ID, the first target associated program ID and the corresponding video PID and audio PID.

It should be noted that the CI protocol stack includes a target PMT table ID data segment, a target associated program ID data segment, a video PID data segment, and an audio PID data segment, and the first target PMT table ID, the first target associated program ID, and the corresponding video PID and audio PID are filled into the data segment corresponding to the CI protocol stack, so that the first CI protocol stack can be generated.

As an embodiment, the preprocessing module includes a tuner, a tuning chip and a demodulation chip connected in sequence, the demodulation chip is connected to the first FPGA module, and the step S1 includes:

and S11, the tuner acquires satellite signals to be processed and sends the satellite signals to the tuning chip.

And S12, the tuning chip tunes the satellite signal to be processed and then sends the satellite signal to the demodulation chip.

And S13, demodulating the tuned satellite signal to be processed by the demodulation chip to generate the first TS, wherein the first TS is a stream which can be identified by the first FPGA module.

It should be noted that the tuning and demodulation techniques involved in steps S11 to S12 can be implemented by directly using the existing tuning and demodulation techniques, and are not described herein again.

In the prior art, the preprocessing module and the decryption and descrambling module are initialized by initializing an I2C bus, but the transmission speed of the I2C bus is limited to 100K to 400K, which results in a slow initialization process of the preprocessing module and the decryption and descrambling module, and the initialization of the decryption and descrambling module can even reach 1 minute, in this application, the I2C bus is further connected between the first FPGA module and the first ARM module, and when the computer program is executed by the processor, the following steps are further implemented:

and S0, initializing the preprocessing module and the decryption and descrambling module by controlling GPIO and simulating the behavior of the I2C bus in a corresponding delay mode.

In the step S0, the behavior of the I2C bus is simulated through the GPIO and the corresponding time delay, the initialization preprocessing module and the decryption descrambling module do not occupy chip resources, the initialization efficiency is improved, and compared with the step S0, the initialization process of the decryption descrambling module only uses 20S, so that the initialization process is greatly improved in comparison with the original 1 minute.

The CAM card and the CA card are used for completing decryption and descrambling of the first TS in a matched mode, a corresponding CAM card slot is formed in the FPGA, the CAM card of the Ci is connected to the CAM card slot in an inserted mode, the CAM card and the CA card are communicated through an ISO7816 protocol, and the CAM card and the first FPGA module are communicated through an EN50221 protocol. The CAM card is a digital video conditional access module, is a device for connecting a television and an external signal source, and is used for converting a compressed digital signal into television content. The CAM card and the smart card (i.e. the CA card) are used together, and the ISO7816 protocol and the EN50221 protocol are existing communication protocols and are not described herein again.

As an embodiment, the first signal output module includes a demultiplexing module and a decoding module, the demultiplexing module is configured to extract the first target program information from the clear stream, and demultiplex video data and audio data of the first target program information; the decoding module is used for respectively decoding the video data and the audio data of the first target program information and then sending the decoded video data and the decoded audio data to the corresponding target receiving system. The decoding module can specifically adopt an MPEG2 decoding mode for decoding, and the target receiving system can directly play decoded video data and audio data

The first embodiment is based on an architecture in which the FPGA and the ARM are matched, routing information is flexibly configured, and target clear stream information is extracted from the TS stream by combining a CI protocol stack, so that the satellite signal processing efficiency and flexibility are improved, and the satellite signal processing cost is reduced.

In the first embodiment, the first FPGA module and the first ARM module can communicate with each other by using the existing SPI communication protocol, and in order to further improve the flexibility and efficiency of communication between the first FPGA module and the first ARM module, the second embodiment is further provided in the present application.

Example II,

An embodiment two provides an SPI-based communication system, as shown in fig. 2, including a first FPGA module, a first ARM module, a processing module installed on the FPGA, a memory (shown in fig. 2) storing a computer program, and a processor (shown in fig. 2), where the first FPGA module includes an FPGA register. The FPGA register is a register arranged in the FPGA module and can be used for unloading commands, unloading data and the like.

The FPGA module and the ARM module are connected through a TSI interface and an SPI interface, the TSI interface is used for transmitting data between the FPGA module and the ARM module, the SPI interface is used for transmitting control commands between the FPGA module and the ARM module, and the control commands are generated based on the preset SPI data structure.

The preset SPI data structure comprises a read-write identification data segment, a read-write target data segment, a read-write type data segment, a target address data segment and a target information data segment, wherein the read-write identification data segment is used for storing read-write identification, the read-write target data segment is used for storing read-write target identification, and the read-write target comprises an FPGA register or a processing module arranged on an FPGA; the read-write type comprises a processing module general storage read-write identifier, a processing module attribute storage read-write identifier, a processing module IO read-write identifier and an empty identifier; the target address data segment is used for storing target address information, and the target information data segment is used for storing target information. The preset SPI data structure can also be provided with a reserved data section for expanding the preset SPI data structure. As an embodiment, the SPI interface may be set to a bus standard mode of CPOL =0, cpha =0, data is transmitted when SPI _ CS is low, a 32-bit SPI data structure may be set, bit 31 is set to a read/write identification data segment, bit 30,29 is set to a read/write target data segment, bit 28,27 is set to a read/write type data segment, bit 26,12 is set to a target address data segment, [11,8] is set to a reserved data segment, and [7,0] is set to a target information data segment. It should be noted that the preset SPI data structure is not limited to 32 bits, and other values may be set according to application requirements.

and D1, the first ARM module generates a target control command based on the preset SPI data structure.

Taking the first embodiment as an example, when the routing information needs to be processed (corresponding to step S2 in the first embodiment), a first target routing control command is generated, that is, the target control command is the first target routing control command. When the CI protocol stack needs to be generated (corresponding to step S4 in the first embodiment), the target control command is the first CI protocol stack.

And D2, the first ARM module transmits the target control command to the FPGA register through the SPI interface.

It should be noted that all the control commands are sent to the FPGA register first, and the FPGA executes the corresponding operation by reading and analyzing the control commands in the FPGA register.

And D3, the first FPGA module analyzes the target control command from the FPGA register to obtain a read-write identifier, a read-write target, a read-write type, target address information and target information, if the read-write identifier is read, the step D4 is executed, and if the read-write identifier is write, the step D5 is executed.

And D4, the first FPGA module acquires corresponding target reading data from the target address information corresponding to the read-write target according to the read-write type, and returns the target reading data to the first ARM module through the TSI.

As an embodiment, the system comprises M processing modules { C) installed on FPGA ₁ ，C ₂ ，…,C _M }，C _i For the ith processing module, the value range of i is 1 to M, and the read-write target identifier is { C } ₁ ，C ₂ ，…,C _M The FPGA register system further comprises an input module and an output module, wherein the input module is arranged on the first FPGA module or the first ARM module, and the output module is arranged on the first FPGA module or the first ARM module.

As an embodiment, when the read-write target is an FPGA register, the target address data segment is set to one of X address identifiers, X =2 × m +6; the target information data segment is set as one of Y target information marks, and Y =2 × M +2. The X address is marked as { F ₁ ,F ₂ ,F ₃ ,F ₄ ,F ₅ ,F ₆ ,A ₁ ,A ₂ ，…,A _M ，B ₁ ,B ₂ ,…B _M }; the Y kinds of target information are marked as { G ₁ ,G ₂ ,…G _M ,H ₁ ,H ₂ ,…H _M ,H _M+1 ,H _M+2 }. Wherein, F ₁ The identification for reading and writing FPGA data. F ₂ The method is used for reading the identification of the FPGA attribute information. F ₃ To read the identification of the status of all processing modules. F ₄ To reset the identity of the processing module and with the address identity set to F ₄ When the target information flag is set to { G ₁ ，G ₂ ，…G _M One of them, if the target information mark is set to G _i Indicates a reset C _i 。F ₅ And the output module is used as the identification of the data stream receiving end. F ₆ The first ARM module is used as an identifier of a data stream receiving end. A. The _i Is C _i As the identification of the receiving end of the data stream, and the address identification is F ₅ ,F ₆ ,A ₁ ，A ₂ … or A _M When the target information flag is set to { H } ₁ ,H ₂ ,…H _M ,H _M+1 ,H _M+2 Any one of them. H _i To be C _i Is the identification of the sender of the data stream. H _M+1 The input module is used as the identification of the data stream sending end. H _M+2 The first ARM module is used as an identifier of a data stream sending terminal. B is _i To read C _i The identification of the data of (2). Through the structure, the flexible configuration of the SPI instruction can be realized, any one processing module and FPGA can be selected as a processing target, and the flexibility and the efficiency of communication between the first FPGA module and the first ARM module are improved.

Taking the structure of the first embodiment as an example, the input module is a signal pre-amplifierThe processing module is arranged on the first FPGA module and used for acquiring a satellite signal to be processed and converting the satellite signal to be processed into a first TS (transport stream), wherein the satellite signal to be processed is an encrypted and scrambled satellite signal; the processing module is a decryption descrambling module and is used for analyzing a target clear stream from the first TS stream and sending the target clear stream to the output module. When step S2 in the first embodiment needs to be implemented, the step D1 is specifically implemented as: step D11, the first ARM module sets a read-write identification data segment in a preset SPI data structure as a write identification based on the acquired first routing configuration information, sets a read-write target data segment as an FPGA register identification, sets a read-write type data segment as null, and sets a target address data segment as F ₅ 、F ₆ Or A _i The target information data segment is set to H _M+1 Generating a first target route control command;

the step D2 is specifically realized as follows: step D21, the first ARM module transmits the first target routing control command to the first FPGA module through the SPI interface;

the step D3 is specifically realized as: and D31, the first FPGA module analyzes the first target routing control command from the FPGA register, determines a writing identifier, an FPGA register identifier, an identifier of a data stream sending end and an identifier of a data stream receiving end, and then executes the step D5.

The step D5 is specifically realized as follows: step D51, respectively sending the first TS streams to corresponding C streams based on the first target route control command _i The first ARM module or the output module.

When step S4 in the first embodiment needs to be implemented, the step D1 is specifically implemented as: step D12, the first ARM module extracts first target program information from the first TS stream, generates a first CI protocol stack, sets a read-write identification data segment in a preset SPI data structure as a write identification, and sets the read-write target data segment as a target C _i Identification, the read-write type data segment is set as the IO read-write identification of the processing module, the target address data segment is set as the target C _i Corresponding target address, target information data segment set toAnd the first CI protocol stack generates a target first CI protocol stack control command.

The step D2 is specifically realized as follows: and D22, the first ARM module transmits the target first CI protocol stack control command to the first FPGA module through the SPI interface.

The step D3 is specifically realized as: step D32, the first FPGA module analyzes the target first CI protocol stack control command from the FPGA register to determine a writing identifier and a target C _i Identification, object C _i Corresponding target address, target C _i And the first CI protocol stack, and then step D5 is performed.

The step D5 is specifically realized as follows: step D52, based on the target first CI protocol stack control command, passing through the target C _i The IO sends the first CI protocol stack to the target C _i The corresponding target address.

As an example, if it is desired to read C _i The data in the memory address AD of (2), performing the following steps:

step D10, the first ARM module sets the read-write identification data segment in the preset SPI data structure as a read identification, and sets the read-write target data segment as C _i Setting the read-write type data segment as a general storage read-write identifier, setting the target address data segment as AD, setting the target information as 'VALUE', and generating a first read C _i And (5) instructions.

Where "VALUE" means "VALUE" for acquiring and transmitting the target information.

Step D20, the first ARM module reads the first reading C _i And the command is transmitted to the FPGA register through the SPI interface.

Step D30, the first FPGA module analyzes a first reading C from the FPGA register _i An instruction based on the first read C _i Instruction slave C _i The target information is read from the AD, stored in the FPGA register, and recorded as 'VALUE'.

Step D40, the first ARM module sets the read-write identification data segment in the preset SPI data structure as a read identification,setting the read-write target data segment as FPGA register identification, setting the read-write type data segment as null, and setting the target address data segment as B _i The target information is set to "VALUE", and a second read C is generated _i And (5) instructions.

Step D50, the first ARM module reads the second reading C _i And transmitting the command to the FPGA register through the SPI interface.

Step D60, the first FPGA module analyzes a second reading C from the FPGA register _i Instructions based on the second read C _i And the instruction reads 'VALUE' from the FPGA register and is sent to the first ARM module through the TSI.

As an embodiment, the input module may also be configured on the first ARM module, and is configured to obtain a video signal to be processed, convert the video signal to be processed into a second TS stream, where the video signal to be processed is an unencrypted and unscrambled signal, and forward the second TS stream to the output module through the first FPGA module. The output module may be disposed on the first FPGA module, and configured to perform K-fold encoding on the obtained second TS stream or the target clear stream, where K is a preset encoding multiple, add a synchronization word, and perform parallel-to-serial conversion to obtain an ASI signal with a code rate maintained at a preset code rate value, and output the ASI signal, where a value of K and a number of bytes of the synchronization word are determined based on the preset code rate value and the code rate value of the second TS stream.

It should be noted that, commands such as reading the attribute information of the FPGA and the attribute information of any processing module may also be set, so that the FPGA executes corresponding operations, which are not listed here.

It should be noted that the SPI communication system described in the second embodiment is not only applicable to the first embodiment, but also applicable to other scenarios including an FPGA module and an ARM module, and setting SPI communication between the FPGA module and the ARM module.

According to the embodiment, the target control command is generated through a preset SPI data structure and sent to the FPGA register, the first FPGA module executes corresponding read-write operation through reading and analyzing the target control command received by the FPGA register, the corresponding target control command can be flexibly generated according to specific control requirements, and the communication efficiency between the first FPGA module and the first ARM module is improved.

Example III,

The third embodiment provides a satellite signal receiver, as shown in fig. 3, comprising a signal preprocessing module, M decryption descrambling modules { C } ₁ ，C ₂ ，…,C _M A signal preprocessing module, a first FPGA module, a first ARM module, an ASI output module, a memory (not shown in FIG. 3) storing a computer program, and a processor (not shown in FIG. 3), wherein the signal preprocessing module, C _i All connected with a first FPGA module, the first FPGA module is connected with a first ARM module, the ASI output module is arranged on the first ARM module, C _i For the ith decryption descrambling module, the value range of i is 1 to M.

and F1, acquiring a satellite signal to be processed through the signal preprocessing module, and preprocessing the satellite signal to be processed to generate a first TS (transport stream), wherein the satellite signal to be processed is an encrypted and scrambled satellite signal.

The TS stream refers to a TS stream file, and is a file format of a DVD.

And F2, the first ARM module generates a third target routing control command based on the acquired third routing configuration information, and sends the third target routing control command to the first FPGA module.

It should be noted that the system may include a display interface, and receive, through the display interface, third routing configuration information input by a user, where the third routing configuration information may be flexibly configured according to specific application requirements.

F3, the first FPGA module sends the first TS stream to at least one first target C based on the third target routing control command _i ASI output module, directly or through a first target C _i And sending the first TS stream to the first ARM module.

It should be noted that the first TS stream is sent to at least one first target C based on a third target routing control command _i ASI output module, directly or through a first target C _i The first TS stream is sent to the first ARM module, the first TS stream may be operated in the system first, but it can be understood that the first TS stream circulated in this stage is encrypted and scrambled, and may not be directly played, and it should be noted that the ASI output module is optional, that is, the first TS stream may be sent to the ASI output module, or may not be sent, and specifically configured in the corresponding routing information.

And F4, the first ARM module extracts first target program information from the first TS stream, generates a first CI protocol stack and sends the first CI protocol stack to the first FPGA module.

Step F5, the first FPGA module forwards the first CI protocol stack to at least one second target C _i The second target C _i Belonging to a first object C _i And (4) collecting.

It should be noted that, based on the routing information flexibly configured in step F2 and step F3, the first TS stream can be flexibly sent to multiple first targets C _i Step F5 may be further flexible from the first target C _i To select one or more second targets C _i To perform an operation of extracting target program information.

Step F6, the second target C _i And analyzing a target clear stream from the first TS stream based on the received first CI protocol stack, and sending the target clear stream to an ASI output module, wherein the target clear stream is a data stream for decryption and descrambling.

It will be appreciated that the second target C _i The target purge can be extracted based on the first CI protocol stack, for one or more. It should be noted that all the existing ways of generating the first CI protocol stack fall into this documentThe details of the invention are not repeated herein.

And F7, the ASI output module performs K-time coding on the target clear stream, wherein K is a preset coding multiple, synchronous words are added, then parallel-serial conversion is performed to obtain an ASI signal with the code rate maintained at a preset code rate value, and the value of K and the number of bytes of the synchronous words are determined based on the preset code rate value and the code rate value of the first TS stream.

The synchronous word is a byte, two bytes, or a number of multiple bytes, and is used for aligning data during data transmission and processing and judging whether the data is valid data. In the step F7, a specific chip is not required, and based on an architecture formed by the first FPGA module and the first ARM module, the target clear stream can be converted into an ASI signal through the logic of the step F7, so that the ASI signal generation efficiency is improved.

And F8, outputting the ASI signal through the ASI output module.

As an embodiment, in step F2, the generating, by the first ARM module, a third target routing control command based on the obtained third routing configuration information includes:

step F21, the first ARM module obtains third route configuration information, the third route configuration information comprises at least one piece of third data flow direction path information, the third data flow direction path information comprises a third data sending module and a third data receiving module, and the third data sending module is the preprocessing module or C _i The third data receiving module is C _i And the first ARM module or the ASI output module generates the third target routing control command based on the third data flow direction path information.

As an embodiment, the first TS stream includes a PAT table, N program information, and N PMT tables, the PAT table is a program association table, the PMT table is a program information table, each program information corresponds to one PMT table, the program information includes a program ID, video data, and audio data corresponding to each program information, each video data corresponds to one video PID, each audio data corresponds to one audio PID, and both the ID and the PID are identification information, where the step F4 includes:

step F41, a first target program information extraction instruction is obtained, wherein the first target program information extraction instruction comprises a first target program ID.

Step F42, based on the first target program ID, acquiring all first target associated program IDs and corresponding first target PMT table IDs from the PAT table.

And step F43, acquiring the video PID and the audio PID corresponding to the first target associated program ID from the corresponding PMT table based on the first target PMT table ID.

And F44, generating the first CI protocol stack based on the first target PMT table ID, the first target associated program ID and the corresponding video PID and audio PID.

Communication between first FPGA module and the first ARM module can be realized based on the SPI communication system in embodiment two, and specifically, as an embodiment, first FPGA module includes the FPGA register, be connected through TSI interface and SPI interface between first FPGA module and the first ARM module, the TSI interface is used for transmitting data between first FPGA module and the first ARM module, the SPI interface is used for transmitting control command between first FPGA module and the first ARM module, control command is based on preset SPI data structure generates. The second embodiment of the specific implementation details of the preset SPI data structure is described, and is not described herein again.

When the read-write target is an FPGA register, the target address data segment is set as one of X address identifiers, and X =2 + M +6; the target information data segment is set as one of Y target information marks, and Y =2 × M +2; specific details of the X address identifier and the Y destination information identifiers are described in the second embodiment, and are not described herein again.

Based on the SPI data structure and the SPI communication method defined in the second embodiment, the step F21 includes:

step F211, the first ARM module generates a third target route control command based on the acquired third route configuration information, sets a read-write identification data segment in a preset SPI data structure as a write identification based on the third target route control command, sets the read-write target data segment as an FPGA register identification, sets the read-write type data segment as null, and sets a target address data segment as F ₅ 、F ₆ Or A _i The target information data segment is set to H _M+1 And generating a third target route control command.

Step F212, the first ARM module transmits the third target routing control command to the first FPGA module through the SPI interface.

As an example, the step F3 further includes:

and F31, the first FPGA module analyzes the third target routing control command from the FPGA register and determines a writing identifier, an FPGA register identifier, an identifier of a data stream sending end and an identifier of a data stream receiving end.

Step F32, based on the third target route control command, respectively sending the first TS streams to at least one first target C _i ASI output module, directly or through a first target C _i And sending the first TS stream to the first ARM module.

Based on the SPI data structure and the SPI communication method defined in the second embodiment, the step F4 includes:

step F41, the first ARM module extracts first target program information from the first TS stream, generates a first CI protocol stack, sets a read-write identification data segment in a preset SPI data structure as a write identification, and sets the read-write target data segment as a target C _i Identification, setting the read-write type data segment as the processing module IO read-write markIdentification, target address data segment set to target C _i And setting the corresponding target address and the target information data segment as a first CI protocol stack to generate a target first CI protocol stack control command.

And step F42, the first ARM module transmits the target first CI protocol stack control command to the first FPGA module through the SPI interface.

As an embodiment, the step F5 further includes:

step F51, the first FPGA module analyzes the target first CI protocol stack control command from the FPGA register, and determines a writing identifier and a target C _i Identification, object C _i Corresponding target address, target C _i And a first CI protocol stack.

Step F52, based on the target first CI protocol stack control command, passing through the target C _i The IO sends the first CI protocol stack to a target C _i The corresponding target address.

It should be noted that other relevant technical details in the first embodiment and the second embodiment may also be applicable to this embodiment, or combined with this embodiment, for example, the first output module in the first embodiment may also be disposed in the system described in the third embodiment, and thus, description thereof is omitted.

In the third embodiment, based on the architecture in which the FPGA and the ARM are matched, a specific chip is not needed, routing information is flexibly configured, and a CI protocol stack is combined to extract target clear stream information from a TS stream, so that the satellite signal processing efficiency and flexibility are improved, and the processing cost of a satellite signal is reduced.

The ASI signal can be generated not only based on the system described in the third embodiment, but also based on an unencrypted unscrambled video signal, based on which the fourth embodiment is further proposed.

Example four,

An embodiment four proposes a video signal processing system, as shown in fig. 4, including a first ARM module, a first FPGA module, a video signal input module disposed on the first ARM module, an ASI output module disposed on the first FPGA module, a memory (not shown in fig. 4) storing a computer program, and a processor (not shown in fig. 4), where the first ARM module is connected to the first FPGA module, and when the computer program is executed by the processor, the following steps are implemented:

and step C1, acquiring a video signal to be processed through the video input module, and converting the video signal to be processed into a second TS (transport stream), wherein the video signal to be processed is an unencrypted and unscrambled signal.

It should be noted that the video signal to be processed may be a video signal that can be directly acquired through a network, and may specifically be acquired through a web page or a network interface. The conventional method for converting the video signal to be processed into the second TS stream falls within the scope of the present invention, and is not described herein again.

And step C2, sending the second TS stream to the first FPGA module.

And step C3, performing K-time coding on the second TS stream, wherein K is a preset coding multiple, adding a synchronous word, and then performing parallel-serial conversion to obtain an ASI signal with the code rate maintained at a preset code rate value, wherein the value of K and the number of bytes of the synchronous word are determined based on the preset code rate value and the code rate value of the second TS stream.

The synchronous word is a byte, two bytes, or a number of multiple bytes, and is used for aligning data during data transmission and processing and judging whether the data is valid data. In the step C3, a specific chip is not required, and based on an architecture formed by the first FPGA module and the first ARM module, the second TS stream can be converted into the ASI signal through the logic of the step C3, so that the ASI signal generation efficiency is improved.

And C4, outputting the ASI signal through the ASI output module.

As an embodiment, the first FPGA module and the first ARM module are connected through a TSI interface, the TSI interface is used for transmitting data between the first FPGA module and the first ARM module, and in the step C2, the second TS stream is sent to the first FPGA module through the TSI interface.

The fourth embodiment is based on the framework that the FPGA and the ARM are matched, the ASI signal can be generated by setting the ASI signal generation logic in the FPGA without a specific chip, and the second TS stream is converted into the ASI signal, so that the ASI signal generation efficiency is improved, and the ASI signal generation cost is reduced.

The system according to the third embodiment and/or the fourth embodiment may output multiple ASI signals, specifically, multiple sets of structures corresponding to the third embodiment and/or the fourth embodiment may be provided, or multiple corresponding ASI output modules may be provided, and an embodiment five further provides a processing technique for multiple ASI signals.

Examples V,

An embodiment five provides a multi-channel ASI signal processing system, which includes a QAM modulation module, a memory storing a computer program, and a processor, where when the processor executes the computer program, the QAM modulation module includes Q signal channels, and each signal channel is configured with a corresponding frequency band and a QAM modulation scheme.

When the processor executes the computer program to run the QAM modulation module, as shown in fig. 5, the following steps are implemented:

and E1, acquiring P ASI signals and placing the P ASI signals in the Q signal channels, wherein P is more than or equal to 2 and less than or equal to Q/2, each ASI signal occupies one signal channel, and at least one isolation signal channel exists between the signal channels where any two ASI signals are located.

Wherein the P ASI signals may be based on system outputs in a plurality of third and/or fourth embodiments. The frequency band configured for each signal channel is in the range of 45M to 960M, the QAM modulation mode configured for each signal channel is 16QAM, 32QAM, 128QAM or 256QAM, and the like, and can cover 45M-960M full frequency band, so that arbitrary modulation in full frequency band and arbitrary bandwidth is realized, and compared with the existing single frequency band modulation mode, the method is more flexible. Specifically, a channel isolation technology may be used to implement that at least one isolated signal channel exists between signal channels where any two ASI signals are located, which is not described herein again.

And E2, carrying out data coding, serial-parallel conversion and differential processing on the ASI signal in the Q-th signal channel to obtain a differential processing result of each channel, wherein the value range of Q is 1 to Q.

In step E2, data encoding, serial-to-parallel conversion, and differential processing are independently performed in parallel on the ASI signal in each q-th signal channel, so as to obtain a differential processing result for each channel.

And E3, performing inverse Fourier transform on the P ASI signals in the Q signal channels according to the frequency band corresponding to the Q signal channel and a QAM modulation mode, and acquiring a mapping value of each ASI signal in each frequency domain to obtain a Q-dimensional array, wherein each dimensional array corresponds to one signal channel.

It should be noted that step E3 may be specifically implemented by a constellation mapping manner, the constellation mapping in the prior art is implemented in a time domain, and the constellation mapping in step E3 is implemented in a frequency domain, in addition, in the prior art, constellation mapping may be performed only on an ASI signal of a single channel, then a filter is set for each channel to perform shaping filtering, and then a multiplier is set to perform combining, so that the processing efficiency is low, and the consumed resources are many. In the method, Q signal channels are arranged, each signal channel is configured with a corresponding frequency band and a corresponding QAM (quadrature amplitude modulation) modulation mode, and in the step E3, the Q signal channels are processed in a frequency domain in a unified manner to obtain a Q-dimensional array.

And E4, calculating a compensation value of each ASI signal channel based on the Q-dimensional array, and setting a value corresponding to the ASI signal channel not stored in the Q-dimensional array to be 0 through a preset filter.

It should be noted that all related algorithms for calculating the compensation value in the prior art fall within the scope of the present invention, and are not described herein again. In addition, theoretically, the value in the array corresponding to the channel without the ASI signal in the Q signal channels should be 0, but due to interference of other channels involved in the processing process, additional values may be generated for the channels that should be set to 0, so that the values may not be 0, and therefore, the value corresponding to the channel without the ASI signal in the Q dimensional array needs to be set to 0 through a preset filter.

And E5, compensating the signal value of the corresponding channel in the Q-dimensional array based on the compensation value of each channel with the ASI signal to obtain a compensated Q-dimensional array.

It should be noted that all the existing processing manners for performing compensation based on the compensation value fall within the protection scope of the present invention, and are not described herein again.

And E6, carrying out filtering interpolation and DA conversion processing on the compensated Q-dimensional array, generating an RF signal and outputting the RF signal.

It should be noted that DA conversion refers to converting a digital signal into an analog signal, and all the existing processing manners of filtering interpolation and DA conversion processing fall within the protection scope of the present invention, and are not described herein again. The DA output can be made smoother by filtering interpolation.

As an embodiment, in the step E2, the ASI signal in the q-th signal channel is data-encoded by using an RS encoding method. RS coding is a forward error correction channel coding that is effective on the polynomial generated by correcting the oversampled data.

As an embodiment, the system further includes a second FPGA module and a second ARM module, where the second FPGA module is provided with T ASI input channels, and may be in butt joint with multiple ASI signals output by the system according to the third embodiment and/or the fourth embodiment, where T is greater than or equal to P, the QAM modulation module is disposed on the second FPGA module, and the T ASI input channels are used to obtain P ASI signals; the second FPGA module and the second ARM module are connected through a TSI interface and an SPI interface, the TSI interface is used for transmitting data between the second FPGA module and the second ARM module, and the SPI interface is used for transmitting commands between the second FPGA module and the second ARM module.

As an embodiment, the step E1 includes that there may be conflicting information in a plurality of ASI signals, that is, some information with the same identification exists in different ASI signals, and therefore, an update adjustment is required to avoid information conflict, and includes:

and E11, the second ARM module generates a fourth target routing control command based on the acquired fourth routing configuration information, and sends the fourth target routing control command to the second FPGA module.

And E12, the second FPGA module sends U ASI signals in the T ASI input channels to the second ARM module based on the fourth target routing control command, wherein P is more than or equal to U and is less than or equal to T.

And E13, the second ARM module analyzes and updates the program description information in the U ASI signals and transmits the program description information back to the first FPGA module, and the FPGA updates the program description information in the corresponding U ASI signals.

And E14, the second ARM module extracts second target program information from the updated U ASI signals, generates a third CI protocol stack and sends the third CI protocol stack to the first FPGA module.

And E15, the second FPGA module extracts P ASI signals from the U ASI signals based on the third CI protocol stack and places the P ASI signals in Q preset signal channels.

As an embodiment, each ASI signal includes F (x) pieces of program information, a PAT table, and F (x) pieces of PMT tables, where the PAT table is a program association table, the F (x) is a quantity of the program information, corresponding F (x) values of different ASI signals may be different, the PMT table is a program information table, each piece of program information corresponds to one PMT table, the program information includes a program ID, video data, and audio data corresponding to each piece of program information, each piece of video data corresponds to one video PID, each piece of audio data corresponds to one audio PID, both the ID and the PID are identification information, and the program description information includes the program ID, the PMT table, and the PAT table. In step E11, the generating, by the second ARM module, a fourth target route control command based on the obtained fourth route configuration information includes:

step E111, the second ARM module obtains fourth routing configuration information, the fourth routing configuration information comprises at least one fourth data flow direction path information, the fourth data flow direction path information comprises a second data sending module and a second data receiving module, the second data sending module comprises at least two ASI input channels, and the second data receiving module is a second ARM module.

And step E112, generating the target routing control command based on the fourth data flow direction path information.

With reference to the preset SPI data structure described in the second embodiment, in this embodiment, the corresponding preset SPI data structure may specifically include a read-write identification data segment, a read-write target data segment, a read-write type data segment, a target address data segment, and a target information data segment, where the read-write identification data segment is used to store a read-write identification, the read-write target data segment is used to store a read-write target identification, and the read-write target includes an FPGA register or an ASI input channel; the read-write type comprises an ASI input channel general storage read-write identifier, an ASI input channel attribute storage read-write identifier, an ASI input channel IO read-write identifier and an empty identifier; the target address data field is used for storing target address information, and the target information data field is used for storing target information.

In the process of performing SPI communication, in this embodiment, the second FPGA module corresponds to the first FPGA module in the second embodiment, the second ARM module corresponds to the first ARM module in the second embodiment, and the T ASI input channels { ASI ₁ ，ASI ₂ ，…，ASI _T Corresponding to M processing modules, ASI, installed on the FPGA in the second embodiment _j For the jth ASI input channel, j ranges from 1 to T, and QAM modulo corresponds to the output module in embodiment two. The structure of the predetermined SPI data structure is not described in detail herein.

In this embodiment, based on the preset SPI data structure in the second embodiment, when the read-write target is an FPGA register, the target address data segment is set to be one of K address identifiers, K =2 × t +6; the target information data segment is set as one of L target information marks, and L =2 × T +1. The K address is marked as { FS ₁ ,FS ₂ ,FS ₃ ,FS ₄ ,FS ₅ ,FS ₆ ,AS ₁ ,AS ₂ ，…,AS _T BS ₁ ,BS ₂ ,…BS _T }; the L kinds of target informationIs marked as { GS ₁ ,GS ₂ ,…GS _T ,HS ₁ ,HS ₂ ,…HS _T ,HS _T+1 }. Wherein, FS ₁ The identification for reading and writing FPGA data. FS (file system) ₂ The identification of the FPGA attribute information is read. FS (file system) ₃ The identification of the channel state is input for reading all ASI. FS (file system) ₄ An identification of the input channel for ASI, and with the address identification set to FS ₄ When the target information flag is set to { GS ₁ ，GS ₂ ，…GS _T One of them, if the target information mark is set to GS _j Indicates resetting of the ASI _j 。FS ₅ And the QAM module is used as the identification of the data stream receiving end. FS (file system) ₆ And the second ARM module is used as an identifier of a data stream receiving end. AS _j Is ASI _j As the identification of the receiving end of the data stream, and the address identification is FS ₅ ,FS ₆ ,AS ₁ ，AS ₂ … or AS _T When the target information flag is set to { HS ₁ ,HS ₂ ,…HS _T ,HS _T+1 ,HS _T+2 Any one of them. HS _j To make ASI _j Is the identification of the sender of the data stream. HS _T+1 The second ARM module is used as an identifier of the data stream sending terminal. BS _j For reading ASI _j The identification of the data of (2). Through the structure, the flexible configuration of the SPI instruction can be realized, any ASI signal channel and FPGA can be selected as a processing target, and the flexibility and the efficiency of communication between the second FPGA module and the second ARM module are improved.

Based on the above structure, the step E112 includes:

step E1121, setting the read-write identification data segment in the preset SPI data structure as a write identification based on the fourth data flow direction path information, setting the read-write target data segment as an FPGA register identification, setting the read-write type data segment as null, and setting the target address data segment as HS _T+1 With the target information data segment set to HS _j And generating the fourth target route control command. As an embodiment, the step E13 includes:

and E131, the second ARM module analyzes program information, a PAT table and a PMT table corresponding to each of the U ASI signals, belongs to different ASI signals and has the same program ID, video PID, audio PID, PAT table ID and/or PMT table ID for updating, so that the program ID, the video PID, the audio PID, the PAT table ID and the PMT table ID of different ASI signals are different. It should be noted that the update process further updates the identification information, i.e. ID or PID, to avoid collision, but the original video data and audio data remain unchanged.

As an example, step E14 includes:

and E141, acquiring a second target program information extraction instruction, wherein the second target program information extraction instruction comprises a second target program ID.

And step E142, acquiring all second target associated program IDs and corresponding second target PMT table IDs from the PAT table based on the second target program IDs.

And E143, acquiring the video PID and the audio PID corresponding to the second target associated program ID from the corresponding PMT table based on the second target PMT table ID.

And E144, generating the third CI protocol stack based on the second target PMT table ID, the second target associated program ID and the corresponding video PID and audio PID.

The step E14 further includes:

step E145, setting the read-write identification data segment in the preset SPI data structure as a write identification, and setting the read-write target data segment as a target ASI _j Setting the read-write type data segment as the IO read-write identification of the processing module and the target address data segment as the target ASI _j And setting the corresponding target address and the target information data segment as a third CI protocol stack, generating a target third CI protocol stack control command, and sending the target third CI protocol stack control command to the first FPGA module.

The step E15 includes:

step E151, the second FPGA module analyzes a target third CI protocol stack control command from the FPGA register, and determines a write identifier and a target ASI _j Identification, target ASI _j Corresponding target address, target ASI _j The IO identifier and the third CI protocol stack;

step E152, based on the target third CI protocol stack control command, passing through the target ASI _j The IO sends the third CI protocol stack to a target ASI _j A corresponding target address;

step E153, target ASI _j And placing the corresponding ASI signals in the preset corresponding signal channels from the ASI signals based on the third CI protocol stack.

It should be noted that the relevant technical details in the first embodiment, the second embodiment, the third embodiment and the fourth embodiment can be applied to the present embodiment as well, and are not repeated herein. The fifth embodiment can implement QAM parallel modulation on multiple ASI signals in the frequency domain based on multiple signal channels, without depending on a specific chip, thereby improving the QAM modulation efficiency of the multiple ASI signals and reducing the modulation cost of the multiple ASI signals.

Examples six,

Based on the system described in the third embodiment, ASI signals are input to the T ASI input channels, and the system described in the fifth embodiment is used to process multiple ASI signals.

Example seven,

Based on the system described in the fourth embodiment, ASI signals are input to the T ASI input channels, and the system described in the fifth embodiment is used to process multiple ASI signals, and specific implementation details are described in the fourth embodiment and the fifth embodiment and are not described herein again.

It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but could have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An SPI-based communication system,

the FPGA-based touch screen comprises a first FPGA module, a first ARM module, a processing module arranged on an FPGA, a memory storing a computer program and a processor, wherein the first FPGA module comprises an FPGA register;

the first FPGA module and the first ARM module are connected through a TSI interface and an SPI interface, the TSI interface is used for transmitting data between the first FPGA module and the first ARM module, the SPI interface is used for transmitting control commands between the first FPGA module and the first ARM module, and the control commands are generated based on a preset SPI data structure;

the preset SPI data structure comprises a read-write identification data segment, a read-write target data segment, a read-write type data segment, a target address data segment and a target information data segment, wherein the read-write identification data segment is used for storing read-write identification, the read-write target data segment is used for storing read-write target identification, and the read-write target comprises an FPGA register or a processing module arranged on the FPGA; the read-write type comprises a processing module general storage read-write identifier, a processing module attribute storage read-write identifier, a processing module IO read-write identifier and an empty identifier; the target address data segment is used for storing target address information, and the target information data segment is used for storing target information;

2. The system of claim 1,

the system comprises M processing modules { C installed on the FPGA ₁ ，C ₂ ，…,C _M }，C _i For the ith processing module, the value range of i is 1 to M, and the read-write target identifier is { C ₁ ，C ₂ ，…,C _M The FPGA register system further comprises an input module and an output module, wherein the input module is arranged on the first FPGA module or the first ARM module, and the output module is arranged on the first FPGA module or the first ARM module.

3. The system of claim 2,

when the read-write target is an FPGA register, the target address data segment is set as one of X address identifiers, and X =2 + M +6; the target information data segment is set as one of Y target information marks, and Y =2 × M +2;

the X address is marked as { F ₁ ,F ₂ ,F ₃ ,F ₄ ,F ₅ ,F ₆ ,A ₁ ,A ₂ ，…,A _M ，B ₁ ,B ₂ ,…B _M }；

The Y kinds of target information are marked as { G ₁ ,G ₂ ,…G _M ,H ₁ ,H ₂ ,…H _M ,H _M+1 ,H _M+2 }；

Wherein, F ₁ The identification for reading and writing FPGA data; f ₂ Reading the identification of the FPGA attribute information; f ₃ Reading the identifiers of the states of all processing modules;

F ₄ to reset the identity of the processing module and with the address identity set to F ₄ When the target information flag is set to { G ₁ ，G ₂ ，…G _M One of them, if the target information mark is set to G _i Indicates a reset C _i ；

F ₅ Identification of the output module as the receiving end of the data stream, F ₆ A first ARM module as an identifier of a data stream receiving end, A _i Is C _i As the identification of the receiving end of the data stream, and the address identification is F ₅ ,F ₆ ,A ₁ ，A ₂ …, or A _M When the target information flag is set to { H } ₁ ,H ₂ ,…H _M ,H _M+1 ,H _M+2 Any one of them, H _i To be C _i For identification of the sender of the data stream, H _M+1 For identification of the input module as the sending end of the data stream, H _M+2 The first ARM module is used as an identifier of a data stream sending end; b is _i To read C _i The identification of the data of (2).

4. The system of claim 3,

the input module is a signal preprocessing module, is arranged on the first FPGA module and is used for acquiring satellite signals to be processed and converting the satellite signals into a first TS (transport stream), and the satellite signals to be processed are encrypted and scrambled satellite signals;

the processing module is a decryption descrambling module and is used for analyzing a target clear stream from the first TS stream and sending the target clear stream to the output module.

5. The system of claim 4,

the step D1 is specifically realized as follows:

step D11, the first ARM module sets a read-write identification data segment in a preset SPI data structure as a write identification based on the acquired first routing configuration information, sets a read-write target data segment as an FPGA register identification, sets a read-write type data segment as null, and sets a target address data segment as F ₅ 、F ₆ Or A _i The target information data segment is set to H _M+1 Generating a first target route control command;

the step D2 is specifically realized as follows:

step D21, the first ARM module transmits the first target routing control command to the first FPGA module through the SPI interface;

the step D3 is specifically realized as:

step D31, the first FPGA module analyzes the first target routing control command from the FPGA register, determines a writing identifier, an FPGA register identifier, an identifier of a data stream sending terminal and an identifier of a data stream receiving terminal, and then executes step D5;

the step D5 is specifically realized as follows:

step D51, respectively sending the first TS streams to corresponding C streams based on the first target route control command _i The first ARM module or the output module.

6. The system of claim 4,

the step D1 is specifically realized as follows:

step D12, the first ARM module extracts first target program information from the first TS stream, generates a first CI protocol stack, sets a read-write identification data segment in a preset SPI data structure as a write identification, and sets the read-write target data segment as a target C _i Setting the read-write type data segment as the read-write identification and target address of the processing module IOSetting data segment as target C _i Setting a corresponding target address and a target information data segment as a first CI protocol stack, and generating a target first CI protocol stack control command;

the step D2 is specifically realized as follows:

step D22, the first ARM module transmits the target first CI protocol stack control command to the first FPGA module through the SPI interface;

the step D3 is specifically realized as:

step D32, the first FPGA module analyzes the target first CI protocol stack control command from the FPGA register to determine a writing identifier and a target C _i Identification, object C _i Corresponding target address, target C _i And then executing step D5;

the step D5 is specifically realized as follows:

step D52, based on the target first CI protocol stack control command, passing through the target C _i The IO sends the first CI protocol stack to the target C _i The corresponding target address.

7. The system of claim 1,

if it is necessary to read C _i The data in the memory address AD of (2), performing the following steps:

step D10, the first ARM module sets the read-write identification data segment in the preset SPI data structure as a read identification, and sets the read-write target data segment as C _i Setting the read-write type data segment as a general storage read-write identifier, setting the target address data segment as AD, setting the target information as 'VALUE', and generating a first read C _i Instructions;

step D20, the first ARM module reads the first reading C _i The command is transmitted to the FPGA register through the SPI interface;

step D30, the first FPGA module analyzes a first reading C from the FPGA register _i Instructions based on the first read C _i Instruction slave C _i The AD reads the target information and stores the target information to the FPGA for registeringIn the container, and is recorded as "VALUE";

step D40, the first ARM module sets the read-write identification data segment in the preset SPI data structure as a read identification, sets the read-write target data segment as an FPGA register identification, sets the read-write type data segment as null, and sets the target address data segment as B _i The target information is set to "VALUE", and a second read C is generated _i Instructions;

step D50, the first ARM module reads the second reading C _i Transmitting the command to the FPGA register through the SPI interface;

8. The system of claim 2,

the input module is arranged on the first ARM module and used for acquiring a video signal to be processed and converting the video signal into a second TS, the video signal to be processed is an unencrypted and unscrambled signal, and the second TS is forwarded to the output module through the first FPGA module.