CN115694505A

CN115694505A - Digital-to-analog converter

Info

Publication number: CN115694505A
Application number: CN202211396846.2A
Authority: CN
Inventors: 周宇捷; 陈富涛; 姚国亮
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2022-11-09
Filing date: 2022-11-09
Publication date: 2023-02-03

Abstract

The application discloses digital-to-analog converter includes: the first digital-to-analog conversion module is used for carrying out coarse adjustment on the reference current according to the first control signal and the second control signal so as to output a coarse adjustment current and a current to be finely adjusted; the second digital-to-analog conversion module is used for finely adjusting the to-be-finely-adjusted current according to the third control signal and the fourth control signal so as to output a finely-adjusted current; the control module is used for generating a first control signal and a second control signal according to the first digital signal with M bits and generating a third control signal and a fourth control signal according to the second digital signal with N bits; the output end outputs the coarse regulation current and the fine regulation current; the first digital-to-analog conversion module comprises 2 ^M The first current switch unit selected by the first digital signal flows the reference current to the second output end to output the current to be finely adjusted, and the first current switch unit cascaded before flows the reference current to the first output end to output the coarsely adjusted current, so that high-precision current stepping can be realized.

Description

Digital-to-analog converter

Technical Field

The present application relates to the field of integrated circuit design and, more particularly, to a digital-to-analog converter.

Background

Digital-to-Analog converters (DACs) are widely used in electronic devices for converting data, mainly converting Digital signals into corresponding Analog signals, and providing the Analog signals to the electronic devices for related applications. The Current DAC (Current DAC) is a common high-speed DAC, and can directly drive a load without an additional amplifier, so that it is one of the best architectures for high-resolution and high-speed DACs.

Fig. 1a shows the basic structure of a current-mode digital-to-analog converter. Referring to fig. 1a, the current-mode dac includes a plurality of current switching units, each including a current source and a pair of switching units connected to each current source, only one of which is shown in fig. 1 for illustration. The input digital signal controls the on-off of the switch unit, so that the current of each current source flows to a specific output end, the currents from the current sources are added and summed at the specific output end, and the analog quantity output corresponding to the digital signal is the current analog quantity output by the specific output end. For example, in fig. 1a, the first ends of the first switch K1 and the second switch K2 are both connected to the current source I, the other end of the first switch K1 is connected to the first output end, the other end of the second switch K2 is connected to the second output end, the control signal controls the on/off of the switch unit, so as to control the current of the current source to flow to the first output end or the second output end, and finally, the current Iout output by the DAC is the sum of the total currents flowing to the first output end from each set of current sources.

Fig. 1b shows the basic structure of a linear weighted digital-to-analog converter in the prior art. Referring to fig. 1b, each current source unit includes a current source and a switch K, and the linear weighting control module controls the on and off of the switch K in the current source unit, so as to control the magnitude of the output current. The current of each current source is equal, but when the number of bits of the control signal is N, the number of current source units is 2 ^N And-1, although the stepping linearity and uniformity are good, the control switch and control signal are more and the structure is complex.

Fig. 1c shows the basic structure of a prior art digital-to-analog converter of the power-weighted type. Referring to fig. 1c, each current source unit includes a current source and a switch K, and the power weighting control module controls the on and off of the switch K in the current source unit, so as to control the magnitude of the output current. The current of each current source is multiplied, when the digit of the control signal is N, the number of the current sources and the number of the switches K are N, although the number of the control switches is small, the structure is simple, the stepping nonlinearity is poor, the size of the component corresponding to each unit is increased along with the increase of the current, and the requirement on layout is high.

Disclosure of Invention

Accordingly, the present invention provides a digital-to-analog converter, which performs coarse adjustment and fine adjustment on a reference current respectively to achieve high-precision current stepping, and simultaneously reduces the number of control signals.

According to a first aspect of the present invention, there is provided a digital to analogue converter comprising: the first digital-to-analog conversion module is used for carrying out coarse adjustment on the reference current according to the first control signal and the second control signal so as to output coarse adjustment current and current to be finely adjusted; the second digital-to-analog conversion module is connected with the first digital-to-analog conversion module and used for finely adjusting the current to be finely adjusted according to a third control signal and a fourth control signal so as to output a fine adjustment current; the control module is used for generating a first control signal and a second control signal according to the first digital signal with M bits, and generating a third control signal and a fourth control signal according to the second digital signal with N bits, wherein M and N are positive integers; the output end is connected with the first output end of the first digital-to-analog conversion module and the first output end of the second digital-to-analog conversion module and outputs the coarse adjustment current and the fine adjustment current; wherein the first digital-to-analog conversion module comprises 2 ^M The first current switch unit selected by the first digital signal enables the reference current to flow to the second output end to output the current to be finely adjusted, the first current switch unit cascaded in front of the selected first current switch unit enables the reference current to flow to the first output end to output the coarse adjustment current, and the first current switch unit cascaded behind the selected first current switch unit is closed.

Preferably, the second digital-to-analog conversion module comprises 2 ^N The second current switch unit selected by the second digital signal controls the magnitude of the output current of the selected second current switch unit through a pulse width modulation signal, the second current switch unit cascaded in front of the selected second current switch unit enables the current to be finely adjusted to flow to the first output end to output the finely adjusted current, and the second current switch unit cascaded behind the selected second current switch unit enables the current to be finely adjusted to flow to the second output end to form a redundant node.

Preferably, the control module comprises: a first decoder for decoding upper M1 bits in the first digital signal to output a plurality of first row control signals and decoding lower M2 bits in the first digital signal to output a plurality of first column control signals, wherein M = M1+ M2, and M1 and M2 are positive integers; the first cascade control units generate a plurality of first control signals and a plurality of second control signals according to the plurality of first row control signals and the plurality of first column control signals, and respectively control the current flow direction of corresponding first current switch units in the first digital-to-analog conversion module; a second decoder for decoding upper N1 bits of the second digital signal to output a plurality of second row control signals and decoding lower N2 bits of the second digital signal to output a plurality of second column control signals, wherein N = N1+ N2, and N1 and N2 are positive integers; the plurality of cascaded second control units generate a plurality of third control signals and a plurality of fourth control signals according to the plurality of second row control signals and the plurality of second column control signals, and respectively control the current flow direction of corresponding second current switching units in the second digital-to-analog conversion module; and controlling the magnitude of the output current of the selected second current switching unit according to the pulse width modulation signal.

Preferably, the plurality of first row control signals and the plurality of first column control signals form 2 ^M1 *2 ^M2 And the matrix controls the current flow direction of a corresponding first current switch unit in the first digital-to-analog conversion module through a first control signal and a second control signal generated by a corresponding first row control signal and a corresponding first column control signal.

Preferably, the first control unit includes a first input end, a second input end, a cascade input end, a first output end, a second output end, and a cascade output end, where the first input end and the second input end respectively receive a corresponding first row control signal and a corresponding first column control signal, the cascade input end receives a first cascade signal output by a previous stage first control unit, the first output end outputs the first control signal, the second output end outputs the second control signal, and the cascade output end outputs the first cascade signal.

Preferably, the cascade input end of the first control unit at the head end is at an inactive level, and the cascade output end of the first control unit at the tail end is floating.

Preferably, the first control unit includes a first not gate, a second not gate, a first nor gate, a second nor gate, and a third not gate; the input end of the first NOT gate receives a first row control signal, and the output end of the first NOT gate is connected with the first input end of the first NOR gate; the input end of the second NOT gate receives a first column control signal; the first input end of the first NOR gate is connected with the output end of the first NOR gate, the second input end of the first NOR gate is connected with the output end of the second NOR gate, and the output end of the first NOR gate outputs a first control signal; a first input end of the second NOR gate receives the first control signal, a second input end of the second NOR gate receives the first cascade signal output by the first control unit at the upper stage, and an output end of the second NOR gate outputs the second control signal; the input end of the third NOT gate receives the second control signal, and the output end of the third NOT gate outputs the first cascade signal.

Preferably, the plurality of second row control signals and the plurality of second column control signals form 2 ^N1 *2 ^N2 And the matrix controls the current flow direction of a corresponding second current switch unit in the second digital-to-analog conversion module through a third control signal and a fourth control signal generated by a corresponding second row control signal and a second column control signal.

Preferably, the second control unit includes a first input end, a second input end, a cascade input end, a first output end, a second output end, and a cascade output end, where the first input end and the second input end respectively receive a second row control signal and a second column control signal, the cascade input end receives a second cascade signal output by the second control unit in the previous stage, the first output end outputs a third control signal, the second output end outputs a fourth control signal, and the cascade output end outputs the second cascade signal.

Preferably, the cascade input end of the second control unit at the head end is at an inactive level, and the cascade output end of the second control unit at the tail end is floating.

Preferably, the second control unit includes a fourth not gate, a fifth not gate, a third not gate, a fourth not gate, a selector, a sixth not gate, a seventh not gate, and an eighth not gate; the input end of the fourth NOT gate receives a second row control signal; the input end of the fifth NOT gate receives a second column control signal; the first input end of the third NOR gate is connected with the output end of the fourth NOR gate, the second input end of the third NOR gate is connected with the output end of the fifth NOR gate, and the output end of the third NOR gate outputs a selection signal; the first input end of the fourth NOR gate is connected with the output end of the third NOR gate, and the second input end of the fourth NOR gate receives a second cascade signal output by the second control unit of the previous stage; the first input end of the selector is connected with the output end of the fourth NOR gate, the second input end of the selector receives the pulse width modulation signal, and the selection end of the selector is connected with the output end of the third NOR gate and receives the selection signal; the input end of the sixth NOT gate is connected with the output end of the selector, and the output end of the sixth NOT gate outputs a third control signal; the input end of the seventh NOT gate is connected with the output end of the sixth NOT gate, and the output end of the seventh NOT gate outputs a fourth control signal; the input end of the eighth not gate is connected with the output end of the fourth nor gate, and the output end of the eighth not gate outputs a second cascade signal.

Preferably, the digital-to-analog converter further includes: the first bias module is used for generating a first bias voltage according to the reference current; and the second bias module is connected with the second output end of the first digital-to-analog conversion module and generates a second bias voltage according to the current to be finely adjusted and the reference current.

Preferably, the first bias module includes first to third transistors and first and second reference current sources, wherein the first reference current source and the first transistor are connected in series between a power supply voltage and a ground terminal; the second reference current source, the second transistor and the third transistor are connected in series between a power supply voltage and a ground terminal; the control end of the first transistor is connected with the control end of the second transistor and is connected with the drain end of the first transistor; the control end of the third transistor is connected with the drain end of the second transistor and outputs a first bias voltage.

Preferably, the digital-to-analog converter further includes: the first bias module is further used for generating a third bias voltage according to the reference current and the reference voltage.

Preferably, the first bias module includes first to third transistors, ninth to thirteenth transistors, a first resistor, a first reference current source, a second reference current source, and a reference voltage source, wherein the first transistor is connected between the first reference current source and a ground terminal; the eleventh transistor, the tenth transistor, the second transistor, and the third transistor are connected in series between a power supply voltage and a ground terminal; the twelfth transistor, the thirteenth transistor and the reference voltage source are connected in series between the power supply voltage and the ground terminal; the first resistor, the ninth transistor and the first reference current source are connected in series between a power supply voltage and a ground terminal; the control end of the first transistor is connected with the control end of the second transistor and is connected with the drain end of the first transistor; the control end of the third transistor is connected with the drain end of the second transistor and outputs a first bias voltage; the control ends of the ninth transistor, the tenth transistor and the thirteenth transistor are connected with the drain end of the ninth transistor; control terminals of the eleventh transistor and the twelfth transistor are connected to a drain terminal of the thirteenth transistor, and the third bias voltage is output.

Preferably, the first to third transistors are NMOS transistors, and the ninth to thirteenth transistors are PMOS transistors.

Preferably, the digital-to-analog converter further includes: the third digital-to-analog conversion module is connected with the first bias module and used for carrying out coarse adjustment on the reference current according to a fifth control signal and a sixth control signal so as to output a coarse adjustment current and a current to be finely adjusted; a fourth digital-to-analog conversion module connected with the third digital-to-analog conversion module and used for receiving a seventh control signal and an eighth control signalFine-adjusting the current to be fine-adjusted to output a fine-adjusted current; the third bias module is connected with a second output end of the third digital-to-analog conversion module and generates a fourth bias voltage according to the current to be finely adjusted and the reference current; wherein the third D/A conversion module comprises 2 ^M The third current switch unit selected by the first digital signal flows the reference current to the second output end to output a current to be finely adjusted, the third current switch unit cascaded in front of the selected third current switch unit flows the reference current to the first output end to output a coarsely adjusted current, and the third current switch unit cascaded behind the selected third current switch unit is closed; the fourth D/A conversion module comprises 2 ^N The fourth current switch unit selected by the second digital signal controls the magnitude of the output current of the selected fourth current switch unit through a pulse width modulation signal, the fourth current switch unit cascaded before the selected fourth current switch unit enables the current to be finely adjusted to flow to the first output end to output the finely adjusted current, and the fourth current switch unit cascaded after the selected fourth current switch unit enables the current to be finely adjusted to flow to the second output end to form a redundant node.

Preferably, each of the first current switching units includes: a first current source unit that outputs the reference current according to the first bias voltage; the first output end is connected with the output end of the digital-to-analog converter; the second output end is connected with the second digital-to-analog conversion module; the fourth transistor is connected between the first current source unit and the first output end, and the control end of the fourth transistor receives the first control signal; and the fifth transistor is connected between the first current source unit and the second output end, and the control end of the fifth transistor receives the second control signal.

Preferably, the first current source unit includes a sixth transistor, a control terminal of which receives the first bias voltage, a source terminal of which is grounded, and a drain terminal of which is connected to source terminals of the fourth transistor and the fifth transistor.

Preferably, the second current switching unit includes: a second current source unit according to the secondThe bias voltage outputs an intermediate fine-tuning current, wherein the intermediate fine-tuning current is 1/2 of the current to be fine-tuned ^N (ii) a The first output end is connected with the output end of the digital-to-analog converter; a second output terminal; the first transmission gate is connected between the second current source unit and the first output end, the negative control end of the first transmission gate receives the third control signal, and the positive control end of the first transmission gate receives the fourth control signal; and the second transmission gate is connected between the second current source unit and the second output end, the negative control end of the second transmission gate receives the fourth control signal, and the positive control end of the second transmission gate receives the third control signal.

Preferably, the second current source unit includes a seventh transistor, a control terminal of which receives the second bias voltage, a source terminal of which receives the intermediate fine adjustment current, and a drain terminal of which is connected to the input terminals of the first transmission gate and the second transmission gate.

Preferably, each of the third current switching units includes: a third current source unit that outputs the reference current according to the third bias voltage; the first output end is connected with the output end of the digital-to-analog converter; the second output end is connected with the fourth digital-to-analog conversion module; a fourteenth transistor connected between the third current source unit and the first output terminal, a control terminal of which receives the fifth control signal; and a fifteenth transistor connected between the third current source unit and the second output terminal, a control terminal of which receives the sixth control signal.

Preferably, the third current source unit includes a sixteenth transistor having a control terminal receiving the third bias voltage, a source terminal connected to ground, and a drain terminal connected to source terminals of the fourteenth transistor and the fifteenth transistor.

Preferably, the fourth current switching unit includes: a fourth current source unit outputting an intermediate fine-tuning current according to the fourth bias voltage, wherein the intermediate fine-tuning current is 1/2 of the current to be fine-tuned ^N (ii) a The first output end is connected with the output end of the digital-to-analog converter; a second output terminal; the third transmission gate is connected between the second current source unit and the first output end, a negative control end of the third transmission gate receives the seventh control signal, and a positive control end of the third transmission gate receives the eighth control signal; a fourth transmission gate connected between the second current source unit and the second output terminalAnd the negative control end of the switch receives the eighth control signal, and the positive control end of the switch receives the seventh control signal.

Preferably, the fourth current source unit includes a seventeenth transistor having a control terminal receiving the fourth bias voltage, a source terminal receiving the intermediate fine adjustment current, and a drain terminal connected to the input terminals of the third transmission gate and the fourth transmission gate.

Preferably, the first digital-to-analog conversion module further includes a first operational amplifier and an eighth transistor, wherein a first input end of the first operational amplifier receives the reference current, a second input end of the first operational amplifier receives the coarse adjustment current, and an output end of the first operational amplifier is connected to a control end of the eighth transistor; and the source end of the eighth transistor is connected with the second input end of the first operational amplifier, and the drain end of the eighth transistor outputs coarse adjustment current.

Preferably, the second bias module includes a second operational amplifier, wherein a first input terminal of the second operational amplifier receives the reference current, a second input terminal of the second operational amplifier receives the current to be fine-tuned and is connected to source terminals of a plurality of seventh transistors in the plurality of second current source units, and an output terminal of the second operational amplifier is connected to a control terminal of the seventh transistor.

Preferably, the third digital-to-analog conversion module further includes a third operational amplifier and an eighteenth transistor, wherein a first input end of the third operational amplifier receives the reference current, a second input end of the third operational amplifier receives the coarse adjustment current, and an output end of the third operational amplifier is connected to a control end of the eighteenth transistor; and the source end of the eighteenth transistor is connected with the second input end of the third operational amplifier, and the drain end of the eighteenth transistor outputs the coarse tuning current.

Preferably, the third bias module includes a fourth operational amplifier, wherein a first input terminal of the fourth operational amplifier receives the reference current, a second input terminal of the fourth operational amplifier receives the current to be fine-tuned and is connected to source terminals of a plurality of seventeenth transistors in the plurality of fourth current source units, and an output terminal of the fourth operational amplifier is connected to a control terminal of the seventeenth transistor.

Preferably, the control module further comprises: a first decoder for decoding upper M1 bits in the first digital signal to output a plurality of first row control signals and decoding lower M2 bits in the first digital signal to output a plurality of first column control signals, wherein M = M1+ M2, and M1 and M2 are positive integers; the plurality of cascaded first control units generate a plurality of first control signals and a plurality of second control signals according to the enable signal, the plurality of first row control signals and the plurality of first column control signals, and respectively control the current flow direction of corresponding first current switch units in the first digital-to-analog conversion module; a second decoder for decoding upper N1 bits of the second digital signal to output a plurality of second row control signals and decoding lower N2 bits of the second digital signal to output a plurality of second column control signals, wherein M = N1+ N2, and M1 and M2 are positive integers; the plurality of cascaded second control units generate a plurality of third control signals and a plurality of fourth control signals according to the plurality of second row control signals, the plurality of second column control signals and the pulse width modulation signals, and respectively control the current flow direction of corresponding second current switching units in the second digital-to-analog conversion module; a plurality of cascaded third control units, which generate a plurality of fifth control signals and a plurality of sixth control signals according to the enable signal, the plurality of first row control signals and the plurality of first column control signals, and respectively control the current flow direction of corresponding third current switch units in the third digital-to-analog conversion module; the plurality of cascaded fourth control units generate a plurality of seventh control signals and a plurality of eighth control signals according to the enable signal, the plurality of second row control signals and the plurality of second column control signals, and respectively control the current flow direction of corresponding fourth current switch units in the fourth digital-to-analog conversion module; controlling the magnitude of the output current of the selected fourth current switch unit according to the pulse width modulation signal; when the enable signal is at an effective level, the first digital-to-analog conversion module and the second digital-to-analog conversion module work, and the third digital-to-analog conversion module and the fourth digital-to-analog conversion module do not work.

Preferably, the plurality of first row control signals and the plurality of first column control signals form 2 ^M1 *2 ^M2 The matrix controls the corresponding first current in the first digital-to-analog conversion module to be switched on by the first control signal and the second control signal generated by the corresponding first row control signal and first column control signal when the enable signal is at the effective levelThe current flow direction of the off cell; when the enable signal is at an inactive level, a fifth control signal and a sixth control signal generated by the corresponding first row control signal and the first column control signal control a current flow direction of a corresponding third current switching unit in the third digital-to-analog conversion module.

Preferably, the first control unit and the third control unit each include a first input terminal, a second input terminal, an enable input terminal, a cascade input terminal, a first output terminal, a second output terminal, and a cascade output terminal, where the first input terminal and the second input terminal respectively receive a corresponding first row control signal and a first column control signal, and the enable input terminal receives an enable signal; the cascade input end of the first control unit receives a first cascade signal output by a first control unit at the previous stage, the first output end outputs a first control signal, the second output end outputs a second control signal, and the cascade output end outputs the first cascade signal; the cascade input end receives a third cascade signal output by the upper-stage third control unit, the first output end outputs a fifth control signal, the second output end outputs a sixth control signal, and the cascade output end outputs the third cascade signal.

Preferably, the cascade input ends of the first control unit and the third control unit at the head end are at an invalid level, and the cascade output ends of the first control unit and the third control unit at the tail end are suspended.

Preferably, the first control unit and the third control unit each include a first not gate, a second not gate, a first nor gate, a second nor gate, and a third not gate; the input end of the first NOT gate receives a first row control signal, and the output end of the first NOT gate is connected with the first input end of the first NOR gate; the input end of the second NOT gate receives a first column control signal; the first input end of the first NOR gate is connected with the output end of the first NOR gate, the second input end of the first NOR gate is connected with the output end of the second NOR gate, the output end of the first control unit outputs a first control signal, and the output end of the third control unit outputs a third control signal; a first input end of a second NOR gate in the first control unit receives a first control signal, a second input end of the second NOR gate receives a first cascade signal output by a first control unit at the previous stage, and an output end of the second NOR gate outputs a second control signal; a first input end of a second NOR gate in the third control unit receives a fifth control signal, a second input end of the second NOR gate receives a third cascade signal output by a third control unit at the upper stage, and an output end of the second NOR gate outputs a sixth control signal; the input end of a third NOT gate in the first control unit receives the second control signal, and the output end outputs a first cascade signal; the input end of a third NOT gate in the third control unit receives a sixth control signal, and the output end of the third NOT gate outputs a third cascade signal; a third input end of a first NOR gate in the first control unit receives an enable signal; the third input terminal of the first nor gate in the third control unit receives a disable signal, wherein the disable signal is opposite to the enable signal in level.

Preferably, the plurality of second row control signals and the plurality of second column control signals form 2 ^N1 *2 ^N2 The matrix is used for controlling the current flow direction of a corresponding second current switch unit in the second digital-to-analog conversion module by a third control signal and a fourth control signal generated by a corresponding second row control signal and a second column control signal when the enable signal is at an effective level; and when the enable signal is at an invalid level, the seventh control signal and the eighth control signal generated by the corresponding second row control signal and second column control signal control the current flowing direction of the corresponding fourth current switch unit in the fourth digital-to-analog conversion module.

Preferably, the second control unit and the fourth control unit each include a first input end, a second input end, an enable input end, a cascade input end, a first output end, a second output end, and a cascade output end, where the first input end and the second input end respectively receive a corresponding second row control signal and a second column control signal, and the enable input end receives the enable signal; the cascade input end of the second control unit receives a second cascade signal output by the second control unit of the previous stage, the first output end outputs a third control signal, the second output end outputs a fourth control signal, and the cascade output end outputs a second cascade signal; the cascade input end of the fourth control unit receives the fourth cascade signal output by the fourth control unit of the previous stage, the first output end outputs the seventh control signal, the second output end outputs the eighth control signal, and the cascade output end outputs the fourth cascade signal.

Preferably, the cascade input ends of the second control unit and the fourth control unit at the head end are at an invalid level, and the cascade output ends of the second control unit and the fourth control unit at the tail end are floating.

Preferably, the second control unit and the fourth control unit each include a fourth not gate, a fifth not gate, a third not gate, a fourth not gate, a selector, a sixth not gate, a seventh not gate, and an eighth not gate; the input end of the fourth NOT gate receives a second row control signal; the input end of the fifth NOT gate receives a second column control signal; the first input end of the third NOR gate is connected with the output end of the fourth NOR gate, the second input end of the third NOR gate is connected with the output end of the fifth NOR gate, and the output end of the third NOR gate outputs a selection signal; a first input end of the fourth NOR gate is connected with an output end of the third NOR gate, a second input end of the second control unit receives a second cascade signal output by the second control unit of the previous stage, and a second input end of the fourth control unit receives a fourth cascade signal output by the fourth control unit of the previous stage; the first input end of the selector is connected with the output end of the fourth NOR gate, the second input end of the selector receives the pulse width modulation signal, and the selection end of the selector is connected with the output end of the third NOR gate and receives the selection signal; the input end of the sixth not gate is connected with the output end of the selector, the output end of the second control unit outputs a third control signal, and the output end of the second control unit outputs a seventh control signal; the input end of the seventh not gate is connected with the output end of the sixth not gate, the output end of the second control unit outputs a fourth control signal, and the output end of the fourth control unit outputs an eighth control signal; the input end of the eighth NOT gate is connected with the output end of the fourth NOR gate, the output end of the second control unit outputs a second cascade signal, and the output end of the fourth control unit outputs a fourth cascade signal; a third input end of a third NOR gate in the second control unit receives an enable signal; the third input terminal of the third nor gate in the fourth control unit receives a disable signal, wherein the disable signal is opposite to the enable signal in level.

Preferably, the digital-to-analog converter further includes: and the offset module is positioned between the output end of the digital-to-analog converter and the redundant node and is used for eliminating the offset voltage of an operational amplifier in the digital-to-analog converter.

Preferably, the offset module includes a fifth operational amplifier, a sixth operational amplifier and first to fourth switches, wherein a first input terminal of the fifth operational amplifier is connected with an output terminal of the digital-to-analog converter and is connected with a first input terminal of the sixth operational amplifier via the first switch; a second input terminal of the fifth operational amplifier is connected to the redundant node and to a second input terminal of the sixth operational amplifier via a second switch; the output end of the fifth operational amplifier is connected with the first input end of the sixth operational amplifier through a third switch and is connected with the second input end of the sixth operational amplifier through a fourth switch; and the output end of the sixth operational amplifier is connected with a redundant node.

According to the digital-to-analog converter provided by the embodiment of the invention, the first digital-to-analog conversion module is adopted to carry out coarse adjustment on the reference current so as to output the coarse adjustment current and the current to be finely adjusted, and the second digital-to-analog conversion module is adopted to carry out fine adjustment on the current to be finely adjusted so as to output the fine adjustment current, so that high-precision current stepping can be realized.

Furthermore, the first digital-to-analog conversion module and the second digital-to-analog conversion module are both matrix digital-to-analog conversion modules, that is, the high bits and the low bits in the digital signals are decoded respectively to generate a plurality of row control signals and a plurality of column control signals, so as to optimize the number of the control signals, that is, the least control signals are used to control as many current switch units as possible, thereby reducing parasitic effect and being suitable for medium-high speed digital-to-analog converters.

Furthermore, the control array of the row control signal and the column control signal in each digital-to-analog conversion module can be increased or decreased according to the needs, so that the flexibility of design is improved.

Furthermore, the pulse width modulation signal is adopted in the second digital-to-analog conversion module to control the flow direction of the selected second current switch unit, and the precision of the digital-to-analog converter can be improved by changing the duty ratio of the pulse width modulation signal.

Furthermore, a symmetrical digital-to-analog conversion structure is adopted, namely the first digital-to-analog conversion module and the third digital-to-analog conversion module are symmetrical, the second digital-to-analog conversion module and the fourth digital-to-analog conversion module are symmetrical, namely the first digital-to-analog conversion module and the second digital-to-analog conversion module adopt NMOS tubes, the third digital-to-analog conversion module and the fourth digital-to-analog conversion module adopt PMOS tubes, one side of the symmetrical structure is controlled to work according to an enabling signal, and therefore the current can be pulled up and pulled down.

Further, an offset circuit is arranged between the output end of the digital-to-analog converter and the redundant node, so that the influence of offset voltage of an operational amplifier in the digital-to-analog converter on output current can be eliminated.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing embodiments of the present invention with reference to the following drawings, in which:

fig. 1 a-1 c show the basic structures of a current-mode digital-to-analog converter, a linear weighted-mode digital-to-analog converter and a power-weighted-mode digital-to-analog converter, respectively;

fig. 2 shows a basic structure of a matrix type digital-to-analog converter;

FIG. 3 is a schematic diagram of a digital-to-analog converter according to an embodiment of the present invention;

fig. 4a and 4b show circuit diagrams of a first current switching unit and a second current switching unit, respectively, in an embodiment of the invention;

fig. 5a and 5b show a circuit diagram of a first control unit and a control signal array schematic diagram of the first control unit, respectively, according to an embodiment of the present invention;

fig. 6 and 7 respectively show a circuit diagram of a first control unit and a control signal array schematic diagram of the first control unit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a digital-to-analog converter according to another embodiment of the present invention;

fig. 9a and 9b show circuit diagrams of a third current switching unit and a fourth current switching unit, respectively, in another embodiment of the present invention;

fig. 10 shows circuit diagrams of first to fourth control units in another embodiment of the present invention;

fig. 11 is a circuit diagram of the offset module according to an embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, and procedures have not been described in detail so as not to obscure the present invention. The figures are not necessarily drawn to scale.

Fig. 2 shows the basic structure of a matrix-type digital-to-analog converter. Referring to fig. 2, the two-dimensional matrix dac adds a dimension to a linear weighted dac, and the control signal is a row control signal (D) ₄ D ₅ D ₆ ) And a column control signal (D) ₁ D ₂ D ₃ ) The control signal array is formed, the current magnitude of the current source in each unit is equal, when the digit of the control signal is N, the number of the current source and the gating switch is 2N, and the control signal array has the advantages of higher precision, low parasitic effect and suitability for high-speed application. The digital-to-analog conversion module in the present application is a matrix type digital-to-analog converter.

Fig. 3 shows a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present invention. As shown in fig. 3, the digital-to-analog converter includes a first digital-to-analog conversion module 110, a second digital-to-analog conversion module 120, and a control module 130.

The first digital-to-analog conversion module 110 is configured to perform coarse adjustment on the reference current according to the first control signal and the second control signal to output a coarse adjustment current and a current to be fine adjusted.

In this embodiment, the first digital-to-analog conversion module includes 2 ^M The first current switch unit selected by the first digital signal Data1 flows the reference current Iref to the second output end to output the current I2 to be finely adjusted, and the first current switch unit cascaded before the selected first current switch unit outputs the reference current Iref to the second output endThe quasi current flows to the first output end to output a coarse adjustment current I1, and the first current switch unit cascaded after the selected first current switch unit is closed.

The second digital-to-analog conversion module 120 is connected to the first digital-to-analog conversion module, and is configured to perform fine adjustment on the to-be-fine-adjusted signal according to a third control signal and a fourth control signal to output a fine-adjustment current.

In this embodiment, the second digital-to-analog conversion module includes 2 ^N The second current switch unit selected by the second digital signal controls the flow direction of the current to be finely adjusted through a pulse width modulation signal, the second current switch unit cascaded before the selected second current switch unit enables the current to be finely adjusted to flow to the first output end to output the finely adjusted current, and the second current switch unit cascaded after the selected second current switch unit enables the current to be finely adjusted to flow to the second output end to form a redundant node.

The control module 130 is configured to generate a first control signal S1 and a second control signal S2 according to the first digital signal Data1 with M bits, and generate a third control signal S3 and a fourth control signal S4 according to the second digital signal Data2 with N bits, where M and N are positive integers.

In this embodiment, the control module includes a first decoder 131, a plurality of cascaded first control units 132, a second decoder 133, and a plurality of cascaded second control units 134.

Wherein the first decoder 131 is used for decoding the high M1 bits in the first digital signal Data1 to output a plurality of first ROW control signals ROW1[1,2 ] ^M1 ]And decoding the low M2 bits of the first digital signal to output a plurality of first column control signals COL1[1,2 ^M2 ]Wherein M = M1+ M2, and M1 and M2 are both positive integers.

The plurality of cascaded first control units 132 are based on the plurality of first ROW control signals ROW1[1,2 [ ] ^M1 ]And a plurality of first column control signals COL1[1,2 ^M2 ]Generate a plurality of first control signals S1[1,2 ^M ]And a plurality of second control signals S2[1,2 ^M ]Respectively controlling the phases in the first D/A conversion moduleThe current flow direction of the corresponding first current switching unit.

In this embodiment, the plurality of first ROW control signals ROW1[1,2 ^M1 ]And a plurality of first column control signals COL1[1,2 ^M2 ]Formation 2 ^M1 *2 ^M2 The matrix, the first control signal and the second control signal generated by the corresponding first ROW control signal ROW1 and the first column control signal COL1 control the current flowing direction of the corresponding first current switch unit in the first digital-to-analog conversion module.

The bit number, the high M1 bit and the low M2 bit of the first digital signal Data1 can be adjusted according to the requirement. In the present embodiment, M =5, M1=3, and M2=2 are exemplified.

Referring to fig. 5b, when the first digital signal Data1 is 01011, the first decoder 131 outputs 8 ROW control signals ROW1 and 4 column control signals COL1, only the ROW control signal corresponding to 010 is active (e.g., high, indicated by "1"), and the remaining corresponding first ROW control signals are inactive (e.g., high, indicated by "0"); and 11, the corresponding first column control signal is at an active level, and the remaining corresponding first column control signals are at an inactive level. Therefore, the first current switch unit selected by the first digital signal is the 12 th first current switch unit, and the reference current Iref flows to the second output end to output the current I2 to be finely adjusted, i.e. I2= Iref; the first current switching unit before the selected first current switching unit flows the reference current Iref to the first output terminal to output the coarse adjustment current I1, i.e., I1=11Iref.

When the first digital signal Data1 is 00110, the coarse tuning current I1=6Iref, and the current to be fine tuned I2= Iref.

Referring to fig. 5a, the first control unit 132 includes a first input terminal, a second input terminal, a cascade input terminal, a first output terminal, a second output terminal, and a cascade output terminal, where the first input terminal and the second input terminal respectively receive a corresponding first ROW control signal ROW1 and a corresponding first column control signal COL1, the cascade input terminal receives a first cascade signal output by the first control unit 132 of the previous stage, the first output terminal outputs a first control signal S1, the second output terminal outputs a second control signal S2, and the cascade output terminal outputs a first cascade signal CS1.

For example, the cascade input of the first control unit 132 at the head end is at an inactive level, and the cascade output of the first control unit 132 at the tail end is floating.

The first ROW control signal ROW1 and the first column control signal COL1 form a control signal array, respectively corresponding to the input signal and the output signal of the corresponding first control unit. For example, the input signals of the first control unit 132 are A1_ [1,j ], B1_ [1,j ], CS1_ [0,j-1], the output signals are S1_ [1,j ], S2_ [1,j ], CS1_ [1,j-1], A1_ [1,j ] are first row control signals in a control signal array, and B1_ [1,j ] are first column control signals in a control signal array, such as A1_1=0, B1_1=0; a1_11=1, B1_11=1.

Referring to fig. 5a, the first control unit includes a first NOT gate NOT1, a second NOT gate NOT2, a first NOR gate NOR1, a second NOR gate NOR1, and a third NOT gate NOT3; an input end of the first NOT gate NOT1 receives the first ROW control signal ROW1, and an output end of the first NOT gate NOT1 is connected with a first input end of the first NOR gate NOR 1; the input end of the second NOT gate NOT2 receives the first column control signal COL1; a first input end of the first NOR gate NOR1 is connected with an output end of the first NOR gate, a second input end of the first NOR gate NOR1 is connected with an output end of the second NOR gate, and an output end of the first NOR gate NOR1 outputs a first control signal S1; a first input end of the second NOR gate NOR2 receives the first control signal S1, a second input end of the second NOR gate NOR2 receives the first cascade signal CS1 output by the first control unit of the previous stage, and an output end of the second NOR gate NOR2 outputs the second control signal S2; the input end of the third NOT gate NOT3 receives the second control signal, and the output end outputs the first cascade signal CS1.

The second decoder 133 is configured to decode high N1 bits of the second digital signal to output a plurality of second row control signals, and decode low N2 bits of the second digital signal to output a plurality of second column control signals, where N = N1+ N2, and N1 and N2 are positive integers.

The plurality of cascaded second control units 134 generate a plurality of third control signals and a plurality of fourth control signals according to the plurality of second row control signals, the plurality of second column control signals and the pulse width modulation signal, and respectively control the current flowing direction of the corresponding second current switching units in the second digital-to-analog conversion module.

In the present embodiment, the plurality of second ROW control signals ROW2 and the plurality of second column control signals COL2 form 2 ^N1 *2 ^N2 And the third control signal S3 and the fourth control signal S4 generated by the corresponding second row control signal and second column control signal control the current flowing direction of the corresponding second current switch unit in the second digital-to-analog conversion module.

The bit number N, the high N1 bit, and the low N2 bit of the second digital signal Data2 can be adjusted according to the requirement. In the present embodiment, N =4, N1=2, and N2=2 are exemplified.

Referring to fig. 7, when the second digital signal Data2 is 0110, the second decoder 133 outputs 4 ROW control signals ROW2 and 4 column control signals COL2, where only 01 corresponding second ROW control signal ROW2 is at an active level (e.g., at a high level, indicated by "1"), and the remaining corresponding second ROW control signals ROW2 are at an inactive level (e.g., at a high level, indicated by "0"); and 11, the corresponding second column control signals COL2 are at active level, and the remaining corresponding second column control signals COL2 are at inactive level. Therefore, the second current switching unit selected by the second digital signal is the 7 th second current switching unit, and the current I2 to be finely adjusted flows to the first output end or the second output end according to the pulse width modulation signal PWM; and the second current switch unit before the selected second current switch unit flows the current I2 to be finely adjusted to the first output end to output a fine adjustment current I4, and the other second current switch units flow the current I2 to be finely adjusted to the second output end to form a redundant node REST. The current I2 to be finely adjusted output from the first digital-to-analog conversion module flows to a plurality of second current switch units, and the current I3= I2/2 in each second current switch unit ^N And (= I2/16). In general, the pulse width modulation signal PWM is always at an active level, and the duty ratio is 100%, then the fine adjustment current I4=7i3=7iref/16 output by the second digital-to-analog conversion module. When the second digital signal Data2 is 0101, the fine adjustment current I4= 6ij3 =6iref/16.

If the precision still does not meet the requirement, the pulse width modulation signal can be modifiedThe duty ratio D of the PWM signal improves the accuracy, and for example, when the duty ratio D =20%, the minimum resolution may be 1/16 × 20% × I _REF ＝0.0125×I _REF . Output current I at this time _DAC The control is also more complicated because the control is not a static current but an average value in a certain period, and under a general application scene, the PWM signal is connected with a high level.

Referring to fig. 6, the second control unit 134 includes a first input terminal, a second input terminal, a cascade input terminal, a first output terminal, a second output terminal, and a cascade output terminal, where the first input terminal and the second input terminal respectively receive a second ROW control signal ROW2 and a second column control signal COL2, the cascade input terminal receives a second cascade signal CS3 output by the second control unit of the previous stage, the first output terminal outputs a third control signal S3, the second output terminal outputs a fourth control signal S4, and the cascade output terminal outputs the second cascade signal CS3. The cascade input of the second control unit 134 at the head end is at an inactive level, and the cascade output of the second control unit 134 at the tail end is floating.

The second ROW control signal ROW2 and the second column control signal COL2 form a control signal array, respectively corresponding to the input signal and the output signal of the corresponding second control unit 134. For example, the input signals of the second control unit 134 are A2_ [1,j ], B2_ [1,j ], CS2_ [0,j-1], the output signals are S3_ [1,j ], S4_ [1,j ], CS2_ [1,j ], A2[1,j ] is a second row control signal in the control signal array, and B2[1,j ] is a second column control signal in the control signal array, such as A2_1=0, B2_1=0; a1_7=1, B1_7=1.

Referring to fig. 6, the second control unit 134 includes a fourth NOT gate NOT4, a fifth NOT gate NOT5, a third NOR gate NOR3, a fourth NOR gate NOR4, a selector MUX, a sixth NOT gate NOT6, a seventh NOT gate NOT7, and an eighth NOT gate NOT8. The input end of the fourth NOT gate NOT4 receives the second ROW control signal ROW2; an input end of the fifth NOT gate NOT5 receives the second column control signal COL2; a first input end of the fourth NOR gate NOR4 is connected with an output end of the fourth NOT gate NOT4, a second input end of the fourth NOR gate NOR4 is connected with an output end of the fifth NOT gate NOT5, and an output end of the fourth NOR gate NOR4 outputs a selection signal SEL; a first input end of the fifth NOR gate NOR5 is connected with an output end of the fourth NOR gate NOR4, and a second input end of the fifth NOR gate NOR5 receives a second cascade signal CS2 output by the second control unit of the previous stage; the first input end of the selector MUX is connected with the output end of the fifth NOR gate NOR5, the second input end of the selector MUX receives the pulse width modulation signal PWM, and the selection end of the selector MUX is connected with the output end of the fourth NOR gate NOR4 and receives the selection signal SEL; the input end of the sixth NOT gate NOT6 is connected with the output end of the selector, and the output end outputs a third control signal S3; the input end of the seventh NOT gate NOT7 is connected with the output end of the sixth NOT gate, and the output end outputs a fourth control signal S4; an input end of the eighth NOT gate NOT8 is connected to an output end of the fifth nor gate, and an output end of the eighth NOT gate NOT8 outputs the second cascade signal CS2.

And an output terminal connected to the first output terminal of the first digital-to-analog conversion module 110 and the first output terminal of the second digital-to-analog conversion module 120, and configured to output the coarse adjustment current I1 and the fine adjustment current I4. The output current IDAC = I1+ I4 at the output.

The digital to analog conversion module further comprises a first biasing module 140 and a second biasing module 150. The first bias module 140 is configured to generate a first bias voltage VB1 according to the reference current Iref. The second bias module 150 is connected to the second output terminal of the first digital-to-analog conversion module 110, and generates a second bias voltage VB2 according to the current I2 to be fine-tuned and the reference current Iref.

Specifically, the first bias module 140 includes first to third transistors M1 to M3, and first and second reference current sources Iref1 and Iref2, where the first and second reference current sources Iref1 and Iref2 have the same size and both output the reference current Iref.

The first reference current source Iref1 and the first transistor M1 are connected in series between a power supply voltage VDD and a ground terminal GND; the second reference current source Iref1, the second transistor M2 and the third transistor M3 are connected in series between the power supply voltage VDD and the ground terminal GND; the control end of the first transistor M1 is connected with the control end of the second transistor M2, and is connected with the drain end of the first transistor M1; a control terminal of the third transistor M3 is connected to the drain terminal of the second transistor M2 and outputs the first bias voltage VB1.

Referring to fig. 4a, each of the first current switching units includes a first current source unit, a first output terminal 1, a second output terminal 2, a fourth transistor M4, and a fifth transistor M5, wherein the first current source unit outputs the reference current Iref according to the first bias voltage VB1; the first output end 1 is connected with the output end of the digital-to-analog converter; the second output end 2 is connected with the second digital-to-analog conversion module 120; the fourth transistor M4 is connected between the first current source unit and the first output terminal, and a control terminal thereof receives the first control signal S1; the fifth transistor M5 is connected between the first current source unit and the second output terminal, and its control terminal receives the second control signal S2. The first current source unit includes a sixth transistor M6, a control terminal of which receives the first bias voltage VB1, a source terminal of which is grounded, and a drain terminal of which is connected to source terminals of the fourth transistor M4 and the fifth transistor M5.

Referring to fig. 4b, the second current switch unit includes a second current source unit, a first output terminal 1, a second output terminal 2, a first transmission gate T1 and a second transmission gate T2, wherein the second current source unit outputs an intermediate fine-tuning current I3 according to the second bias voltage VB2, wherein the intermediate fine-tuning current I3 is 1/2 of the current I2 to be fine-tuned ^N I.e. I3= I2/2 ^N . The first output end is connected with the output end of the digital-to-analog converter; the second output end is connected with the second output end corresponding to each second current switch unit in the second control unit; the first transmission gate T1 is connected between the second current source unit and the first output terminal 1, a negative control terminal thereof receives the third control signal S3, and a positive control terminal thereof receives the fourth control signal S4; the second transmission gate T2 is connected between the second current source unit and the second output terminal, and has a negative control terminal receiving the fourth control signal S4 and a positive control terminal receiving the third control signal S3. The second current source unit includes a seventh transistor M7 having a control terminal receiving the second bias voltage VB2, a source terminal receiving the intermediate fine adjustment current, and a drain terminal connected to the input terminals of the first transmission gate T1 and the second transmission gate T2.

The first digital-to-analog conversion module 110 further includes a first operational amplifier OP1 and an eighth transistor M8, wherein a first input end of the first operational amplifier OP1 receives the reference current Iref, a second input end receives the coarse tuning current I1, and an output end is connected to a control end of the eighth transistor M8; the source end of the eighth transistor M8 is connected to the second input end of the first operational amplifier OP1, and the drain end outputs the coarse adjustment current I1.

Specifically, the second bias module 150 includes a second operational amplifier OP1, wherein a first input terminal of the second operational amplifier OP2 receives the reference current Iref, a second input terminal of the second operational amplifier OP2 receives the current to be fine-tuned I2 and is connected to source terminals of a plurality of seventh transistors M7 in the plurality of second current source units, and an output terminal of the second operational amplifier OP2 is connected to a control terminal of the seventh transistor M7. In this embodiment, the first transistor M1 to the eighth transistor M8 are all NMOS transistors.

Fig. 8 is a schematic structural diagram of a digital-to-analog converter according to another embodiment of the present invention. Compared with the above embodiments, the third digital-to-analog conversion module 260 and the fourth digital-to-analog conversion module 270, which are symmetrically arranged with the first digital-to-analog conversion module 210 and the second digital-to-analog conversion module 220, are newly added in this embodiment.

The third digital-to-analog conversion module 260 and the first digital-to-analog conversion module 210 have the same structure, except that the third digital-to-analog conversion module 260 adopts a PMOS transistor and the first digital-to-analog conversion module 210 adopts an NMOS transistor. The fourth digital-to-analog conversion module 270 and the second digital-to-analog conversion module 220 have the same structure, except that the fourth digital-to-analog conversion module 270 employs a PMOS transistor, and the second digital-to-analog conversion module 220 employs an NMOS transistor.

Accordingly, the first bias module 240 is further configured to generate the third bias voltage VB3 according to the reference current Iref and the reference voltage Vref.

In this embodiment, the first bias module 240 includes first to third transistors M1 to M3, ninth to thirteenth transistors M9 to M13, a first resistor R1, a first reference current source Iref1, a second reference current source Iref2, and a reference voltage source Vref. The first transistor M1 is connected between the first reference current source Iref1 and a ground terminal; the eleventh transistor M11, the tenth transistor M10, the second transistor M2, and the third transistor M3 are connected in series between the power supply voltage VDD and the ground terminal; the twelfth transistor M12, the thirteenth transistor M13 and the reference voltage source Vref are connected in series between the power voltage VDD and the ground terminal; the first resistor R1, the ninth transistor M9 and the second reference current source Iref2 are connected in series between the power voltage VDD and the ground terminal; the control end of the first transistor M1 is connected with the control end of the second transistor M2, and is connected with the drain end of the first transistor M1; the control end of the third transistor M3 is connected to the drain end of the second transistor M2 and outputs a first bias voltage VB1; the control terminals of the ninth transistor M9, the tenth transistor M10 and the thirteenth transistor M13 are connected, and are connected to the drain terminal of the ninth transistor M9; the control terminals of the eleventh transistor M11 and the twelfth transistor M12 are connected and to the drain terminal of the thirteenth transistor M13, and the third bias voltage VB3 is output.

The third digital-to-analog conversion module 260 is connected to the first bias module 240, and is configured to perform coarse adjustment on the reference current Iref according to a fifth control signal S5 and a sixth control signal S6 to output a coarse adjustment current I1 and a current I2 to be fine adjusted.

The fourth digital-to-analog conversion module 270 is connected to the third digital-to-analog conversion module 260, and is configured to perform fine adjustment on the current to be fine-adjusted according to a seventh control signal S7 and an eighth control signal S8 to output a fine-adjustment current I4.

Wherein the third digital-to-analog conversion module 260 comprises 2 ^M And the third current switch unit selected by the first digital signal enables the reference current to flow to the second output end so as to output the current to be finely regulated, the third current switch unit cascaded before the selected third current switch unit enables the reference current to flow to the first output end so as to output the coarse regulation current, and the third current switch unit cascaded after the selected third current switch unit is closed.

The fourth digital-to-analog conversion module comprises 2 ^N The fourth current switch unit selected by the second digital signal controls the flow direction of the current to be finely adjusted through a pulse width modulation signal, the fourth current switch unit cascaded before the selected fourth current switch unit enables the current to be finely adjusted to flow to the first output end to output the fine adjustment current, and the fourth current switch unit cascaded after the selected fourth current switch unit enables the current to be finely adjusted to flow to the second output end to form a redundant node.

Referring to fig. 9a, each of the third current switching units includes a third current source unit, a first output terminal, a second output terminal, and fourteenth and fifteenth transistors M14 and M15; wherein the third current source unit outputs the reference current Iref according to the third bias voltage VB 3; the first output end is connected with the output end of the digital-to-analog converter; the second output end is connected with the fourth digital-to-analog conversion module; the fourteenth transistor M14 is connected between the third current source unit and the first output terminal, and its control terminal receives the fifth control signal S5; the fifteenth transistor M15 is connected between the third current source unit and the second output terminal, and its control terminal receives the sixth control signal S6. The third current source unit includes a sixteenth transistor M16 having a control terminal receiving the third bias voltage VB3, a source terminal connected to ground, and a drain terminal connected to source terminals of the fourteenth transistor M14 and the fifteenth transistor M15.

Referring to fig. 9b, the fourth current switching unit includes a fourth current source unit, a first output terminal, a second output terminal, and third and fourth transmission gates T3 and T4. The fourth current source unit outputs an intermediate fine-tuning current I3 according to the fourth bias voltage VB4, wherein the intermediate fine-tuning current is 1/2 of the current to be fine-tuned ^N (ii) a The first output end is connected with the output end of the digital-to-analog converter; a second output terminal; the third transmission gate T3 is connected between the second current source unit and the first output terminal, and a negative control terminal thereof receives the seventh control signal S7 and a positive control terminal thereof receives the eighth control signal S8; the fourth transmission gate T4 is connected between the second current source unit and the second output terminal, and a negative control terminal thereof receives the eighth control signal S8 and a positive control terminal thereof receives the seventh control signal S7. The fourth current source unit includes a seventeenth transistor M17 having a control terminal receiving the fourth bias voltage VB4, a source terminal receiving the intermediate fine adjustment current I3, and a drain terminal connected to the input terminals of the third transmission gate T3 and the fourth transmission gate T4.

The third digital-to-analog conversion module further comprises a third operational amplifier OP3 and an eighteenth transistor M18, wherein a first input end of the third operational amplifier OP3 receives the reference current Iref, a second input end receives the coarse tuning current I1, and an output end is connected with a control end of the eighteenth transistor M18; the source terminal of the eighteenth transistor M18 is connected to the second input terminal of the third operational amplifier OP3, and the drain terminal outputs the coarse adjustment current I1.

The second bias module 250 includes a second operational amplifier OP1 and a fourth operational amplifier OP4, wherein a first input terminal of the second operational amplifier OP2 receives the reference current Iref, a second input terminal receives the current to be fine-tuned I2 and is connected to source terminals of a plurality of seventh transistors M7 in a plurality of second current source units, and an output terminal is connected to a control terminal of the seventh transistor M7; a first input end of the fourth operational amplifier OP4 receives the reference current Iref, a second input end of the fourth operational amplifier OP4 receives the current I2 to be fine-tuned and is connected to source ends of a plurality of seventeenth transistors M17 in the plurality of fourth current source units, and an output end of the fourth operational amplifier OP4 is connected to a control end of the seventeenth transistor M17. In this embodiment, the first to eighth transistors M1 to M8 are all NMOS transistors, and the ninth to thirteenth transistors M9 to M13 and the sixteenth to eighteenth transistors M16 to M18 are PMOS transistors.

Referring to fig. 10, the control module 230 includes a plurality of cascaded first control units, a plurality of cascaded second control units, a plurality of cascaded third control units, and a plurality of cascaded fourth control units. The third control unit and the first control unit have the same structure, and are different in that the enable terminals thereof receive enable signals of opposite levels, for example, the enable input terminal of the first control unit receives an enable signal EN, and the enable input terminal of the third control unit receives a non-enable signal. Similarly, the fourth control unit and the second control unit have the same structure, and are different in that the enable terminals thereof receive enable signals of opposite levels, for example, the enable input terminal of the second control unit receives an enable signal EN, and the enable input terminal of the fourth control unit receives a non-enable signal. When the enable signal EN is at an active level, the first control unit and the second control unit operate, so that the first digital-to-analog conversion module 210 and the second digital-to-analog conversion module 220 operate, and at this time, the third digital-to-analog conversion module 260 and the fourth digital-to-analog conversion module 270 are turned off and do not operate; when the enable signal EN is at an inactive level, the third control unit and the fourth control unit operate, so that the third digital-to-analog conversion module 260 and the fourth digital-to-analog conversion module 270 operate, and at this time, the first digital-to-analog conversion module 210 and the second digital-to-analog conversion module 220 are turned off and do not operate.

In this embodiment, the first transistor M1 to the eighth transistor are NMOS transistors, and the ninth transistor to the eighteenth transistor are PMOS transistors.

In a preferred embodiment, an offset block 280 is provided between the output of the digital-to-analog converter and the redundancy node REST for removing the offset voltage of the operational amplifier in the digital-to-analog converter.

Referring to fig. 11, the offset module 280 includes a fifth operational amplifier OP5, a sixth operational amplifier OP6 and first to fourth switches K1 to K4, wherein a first input terminal of the fifth operational amplifier OP5 is connected to an output terminal of the digital-to-analog converter, and is connected to a first input terminal of the sixth operational amplifier via the first switch K1; a second input terminal of the fifth operational amplifier OP5 is connected to the redundant node REST and to a second input terminal of the sixth operational amplifier OP6 via a second switch K2; the output end of the fifth operational amplifier OP5 is connected to the first input end of the sixth operational amplifier OP6 via a third switch K3, and is connected to the second input end of the sixth operational amplifier OP6 via a fourth switch K4; the output terminal of the sixth operational amplifier OP6 is connected to a redundant node.

When the first switch K1 and the second switch K2 are closed and the third switch K3 and the fourth switch K4 are opened, the output end of the digital-to-analog converter and the redundant node REST clamp the voltage of the redundant node REST and the voltage of the output end of the digital-to-analog converter through a buffer structure formed by a sixth operational amplifier OP 6; when the first switch K1 and the second switch K2 are turned off and the third switch K3 and the fourth switch K4 are turned on, the input terminal of the sixth operational amplifier OP6 is short-circuited to remove an offset voltage, and simultaneously the input terminal of the fifth operational amplifier OP5 is connected to the output terminal of the digital-to-analog converter and the redundant node REST, respectively, and the output terminal of the fifth operational amplifier OP5 is used to determine a common mode level at this time.

The embodiment of the invention adopts a symmetrical digital-to-analog conversion structure, namely the first digital-to-analog conversion module and the third digital-to-analog conversion module are symmetrical, the second digital-to-analog conversion module and the fourth digital-to-analog conversion module are symmetrical, namely the first digital-to-analog conversion module and the second digital-to-analog conversion module adopt NMOS tubes, the third digital-to-analog conversion module and the fourth digital-to-analog conversion module adopt PMOS tubes, and one side of the symmetrical structure is controlled to work according to an enabling signal, so that the current can be pulled up and pulled down.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital-to-analog converter, comprising:

the first digital-to-analog conversion module is used for carrying out coarse adjustment on the reference current according to the first control signal and the second control signal so as to output a coarse adjustment current and a current to be finely adjusted;

the second digital-to-analog conversion module is connected with the first digital-to-analog conversion module and used for finely adjusting the current to be finely adjusted according to a third control signal and a fourth control signal so as to output a fine adjustment current;

the control module is used for generating a first control signal and a second control signal according to the first digital signal with M bits, and generating a third control signal and a fourth control signal according to the second digital signal with N bits, wherein M and N are positive integers;

the output end is connected with the first output end of the first digital-to-analog conversion module and the first output end of the second digital-to-analog conversion module and outputs the coarse adjustment current and the fine adjustment current;

wherein the first digital-to-analog conversion module comprises 2 ^M The first current switch unit selected by the first digital signal enables the reference current to flow to the second output end to output the current to be finely adjusted, the first current switch unit cascaded in front of the selected first current switch unit enables the reference current to flow to the first output end to output the coarse adjustment current, and the first current switch unit cascaded behind the selected first current switch unit is closed.

2. Digital-to-analog converter according to claim 1, characterized in that said second digital-to-analog conversion module comprises 2 ^N The second current switch unit selected by the second digital signal controls the output current of the selected second current switch unit by a pulse width modulation signal, and the second current switch unit cascaded before the selected second current switch unit flows the current to be finely adjusted to the first outputAnd the output end outputs fine adjustment current, and the second current switch unit cascaded behind the selected second current switch unit enables the current to be fine adjusted to flow to the second output end to form a redundant node.

3. The digital-to-analog converter according to claim 2, characterized in that said control module comprises:

a first decoder for decoding upper M1 bits in the first digital signal to output a plurality of first row control signals and decoding lower M2 bits in the first digital signal to output a plurality of first column control signals, wherein M = M1+ M2, and M1 and M2 are positive integers;

the first cascade control units generate a plurality of first control signals and a plurality of second control signals according to the plurality of first row control signals and the plurality of first column control signals, and respectively control the current flow direction of corresponding first current switch units in the first digital-to-analog conversion module;

a second decoder for decoding upper N1 bits of the second digital signal to output a plurality of second row control signals and decoding lower N2 bits of the second digital signal to output a plurality of second column control signals, wherein N = N1+ N2, and N1 and N2 are positive integers;

the plurality of cascaded second control units generate a plurality of third control signals and a plurality of fourth control signals according to the plurality of second row control signals and the plurality of second column control signals, and respectively control the current flow direction of corresponding second current switching units in the second digital-to-analog conversion module; and controlling the magnitude of the output current of the selected second current switch unit according to the pulse width modulation signal.

4. The DAC of claim 3 wherein the first row control signals and the first column control signals form 2 ^M1 *2 ^M2 And the matrix controls the current flowing direction of a corresponding first current switch unit in the first digital-to-analog conversion module by a first control signal and a second control signal generated by a corresponding first row control signal and a corresponding first column control signal.

5. The DAC as claimed in claim 4 wherein the first control unit comprises a first input terminal, a second input terminal, a cascade input terminal, a first output terminal, a second output terminal and a cascade output terminal, wherein the first input terminal and the second input terminal respectively receive the corresponding first row control signal and the first column control signal, the cascade input terminal receives the first cascade signal outputted from the first control unit of the previous stage, the first output terminal outputs the first control signal, the second output terminal outputs the second control signal, and the cascade output terminal outputs the first cascade signal.

6. The DAC as claimed in claim 5 wherein the cascade input of the first control unit at the head end is inactive and the cascade output of the first control unit at the tail end is floating.

7. The digital-to-analog converter according to claim 5, wherein the first control unit comprises a first not gate, a second not gate, a first nor gate, a second nor gate and a third not gate;

the input end of the first NOT gate receives a first row control signal, and the output end of the first NOT gate is connected with the first input end of the first NOR gate;

the input end of the second NOT gate receives a first column control signal;

the first input end of the first NOR gate is connected with the output end of the first NOR gate, the second input end of the first NOR gate is connected with the output end of the second NOR gate, and the output end of the first NOR gate outputs a first control signal;

a first input end of the second NOR gate receives the first control signal, a second input end of the second NOR gate receives the first cascade signal output by the first control unit at the upper stage, and an output end of the second NOR gate outputs the second control signal;

the input end of the third NOT gate receives the second control signal, and the output end of the third NOT gate outputs the first cascade signal.

8. The digital-to-analog converter according to claim 3,the plurality of second row control signals and the plurality of second column control signals form 2 ^N1 *2 ^N2 And the matrix controls the current flow direction of a corresponding second current switch unit in the second digital-to-analog conversion module through a third control signal and a fourth control signal generated by a corresponding second row control signal and a second column control signal.

9. The DAC as claimed in claim 3 wherein the second control unit comprises a first input terminal, a second input terminal, a cascade input terminal, a first output terminal, a second output terminal and a cascade output terminal, wherein the first input terminal and the second input terminal respectively receive the corresponding second row control signal and second column control signal, the cascade input terminal receives the second cascade signal outputted from the second control unit of the previous stage, the first output terminal outputs the third control signal, the second output terminal outputs the fourth control signal, and the cascade output terminal outputs the second cascade signal.

10. The dac of claim 9 wherein the cascade input of the first control unit is inactive and the cascade output of the second control unit is floating.

11. The digital-to-analog converter according to claim 9, wherein the second control unit comprises a fourth not gate, a fifth not gate, a third not gate, a fourth not gate, a selector, a sixth not gate, a seventh not gate, and an eighth not gate;

the input end of the fourth NOT gate receives a second row control signal;

the input end of the fifth NOT gate receives a second column control signal;

the first input end of the third NOR gate is connected with the output end of the fourth NOR gate, the second input end of the third NOR gate is connected with the output end of the fifth NOR gate, and the output end of the third NOR gate outputs a selection signal;

the first input end of the fourth NOR gate is connected with the output end of the third NOR gate, and the second input end of the fourth NOR gate receives a second cascade signal output by the second control unit of the previous stage;

the first input end of the selector is connected with the output end of the fourth NOR gate, the second input end of the selector receives the pulse width modulation signal, and the selection end of the selector is connected with the output end of the third NOR gate and receives the selection signal;

the input end of the sixth NOT gate is connected with the output end of the selector, and the output end of the sixth NOT gate outputs a third control signal;

the input end of the seventh NOT gate is connected with the output end of the sixth NOT gate, and the output end of the seventh NOT gate outputs a fourth control signal;

the input end of the eighth not gate is connected with the output end of the fourth nor gate, and the output end of the eighth not gate outputs a second cascade signal.

12. The digital-to-analog converter according to claim 2, further comprising:

the first bias module is used for generating a first bias voltage according to the reference current;

and the second bias module is connected with the second output end of the first digital-to-analog conversion module and generates a second bias voltage according to the current to be finely adjusted and the reference current.

13. The digital-to-analog converter according to claim 12, characterized in that the first biasing module comprises a first to a third transistor and a first and a second reference current source,

wherein the first reference current source and the first transistor are connected in series between a power supply voltage and a ground terminal;

the second reference current source, the second transistor and the third transistor are connected in series between a power supply voltage and a ground terminal;

the control end of the first transistor is connected with the control end of the second transistor and is connected with the drain end of the first transistor;

the control end of the third transistor is connected with the drain end of the second transistor and outputs a first bias voltage.

14. The digital-to-analog converter according to claim 12, further comprising:

the first bias module is further used for generating a third bias voltage according to the reference current and the reference voltage.

15. The digital-to-analog converter according to claim 14, wherein the first bias module comprises first to third transistors, ninth to thirteenth transistors, a first resistor, a first reference current source, a second reference current source, and a reference voltage source,

the first transistor is connected between the first reference current source and the grounding end;

the eleventh transistor, the tenth transistor, the second transistor, and the third transistor are connected in series between a power supply voltage and a ground terminal;

the twelfth transistor, the thirteenth transistor and the reference voltage source are connected in series between the power supply voltage and the ground terminal;

the first resistor, the ninth transistor and the first reference current source are connected in series between a power supply voltage and a ground terminal;

the control end of the third transistor is connected with the drain end of the second transistor and outputs a first bias voltage;

the control ends of the ninth transistor, the tenth transistor and the thirteenth transistor are connected with the drain end of the ninth transistor;

control terminals of the eleventh transistor and the twelfth transistor are connected, and a drain terminal of the thirteenth transistor is connected, and the third bias voltage is output.

16. The dac of claim 15 wherein the first through third transistors are NMOS transistors and the ninth through thirteenth transistors are PMOS transistors.

17. The digital-to-analog converter according to claim 14, further comprising:

the third digital-to-analog conversion module is connected with the first bias module and used for carrying out coarse adjustment on the reference current according to a fifth control signal and a sixth control signal so as to output a coarse adjustment current and a current to be finely adjusted;

the fourth digital-to-analog conversion module is connected with the third digital-to-analog conversion module and used for finely adjusting the current to be finely adjusted according to a seventh control signal and an eighth control signal so as to output a fine adjustment current;

the second bias module is also connected with a second output end of the third digital-to-analog conversion module and generates a fourth bias voltage according to the current to be finely adjusted and the reference current;

wherein the third D/A conversion module comprises 2 ^M The third current switch unit selected by the first digital signal flows the reference current to the second output end to output a current to be finely adjusted, the third current switch unit cascaded in front of the selected third current switch unit flows the reference current to the first output end to output a coarsely adjusted current, and the third current switch unit cascaded behind the selected third current switch unit is closed;

the fourth digital-to-analog conversion module comprises 2 ^N The fourth current switch unit selected by the second digital signal controls the magnitude of the output current of the selected fourth current switch unit through a pulse width modulation signal, the fourth current switch unit cascaded before the selected fourth current switch unit enables the current to be finely adjusted to flow to the first output end to output the finely adjusted current, and the fourth current switch unit cascaded after the selected fourth current switch unit enables the current to be finely adjusted to flow to the second output end to form a redundant node.

18. Digital-to-analog converter according to claim 12 or 17, characterized in that each of said first current switching cells comprises:

a first current source unit that outputs the reference current according to the first bias voltage;

the first output end is connected with the output end of the digital-to-analog converter;

the second output end is connected with the second digital-to-analog conversion module;

the fourth transistor is connected between the first current source unit and the first output end, and the control end of the fourth transistor receives the first control signal;

and the fifth transistor is connected between the first current source unit and the second output end, and the control end of the fifth transistor receives the second control signal.

19. The dac of claim 18 wherein the first current source unit comprises a sixth transistor having a control terminal receiving the first bias voltage, a source terminal connected to ground, and a drain terminal connected to the source terminals of the fourth and fifth transistors.

20. The digital-to-analog converter according to claim 18, wherein the second current switching unit comprises:

a second current source unit for outputting an intermediate fine-tuning current according to the second bias voltage, wherein the intermediate fine-tuning current is 1/2 of the current to be fine-tuned ^N ；

a second output terminal;

the first transmission gate is connected between the second current source unit and the first output end, the negative control end of the first transmission gate receives the third control signal, and the positive control end of the first transmission gate receives the fourth control signal;

and the second transmission gate is connected between the second current source unit and the second output end, the negative control end of the second transmission gate receives the fourth control signal, and the positive control end of the second transmission gate receives the third control signal.

21. The digital-to-analog converter according to claim 20, wherein the second current source unit comprises a seventh transistor having a control terminal receiving the second bias voltage, a source terminal receiving the intermediate fine tuning current, and a drain terminal connected to the input terminals of the first transmission gate and the second transmission gate.

22. The digital-to-analog converter according to claim 17, wherein each of the third current switching units comprises:

a third current source unit that outputs the reference current according to the third bias voltage;

the second output end is connected with the fourth digital-to-analog conversion module;

a fourteenth transistor connected between the third current source unit and the first output terminal, a control terminal of which receives the fifth control signal;

and a fifteenth transistor connected between the third current source unit and the second output terminal, a control terminal of which receives the sixth control signal.

23. The dac of claim 22 wherein the third current source unit comprises a sixteenth transistor having a control terminal receiving the third bias voltage, a source terminal connected to ground, and a drain terminal connected to source terminals of the fourteenth and fifteenth transistors.

24. The digital-to-analog converter according to claim 17, wherein the fourth current switching unit comprises:

a fourth current source unit outputting an intermediate fine-tuning current according to the fourth bias voltage, wherein the intermediate fine-tuning current is 1/2 of the current to be fine-tuned ^N ；

a second output terminal;

the third transmission gate is connected between the second current source unit and the first output end, the negative control end of the third transmission gate receives the seventh control signal, and the positive control end of the third transmission gate receives the eighth control signal;

and the fourth transmission gate is connected between the second current source unit and the second output end, the negative control end of the fourth transmission gate receives the eighth control signal, and the positive control end of the fourth transmission gate receives the seventh control signal.

25. The dac of claim 24 wherein the fourth current source unit comprises a seventeenth transistor having a control terminal receiving the fourth bias voltage, a source terminal receiving the intermediate fine tuning current, and a drain terminal connected to the input terminals of the third and fourth transmission gates.

26. The digital-to-analog converter according to claim 21 or 25, characterized in that said first digital-to-analog conversion module further comprises a first operational amplifier and an eighth transistor,

the first input end of the first operational amplifier receives the reference current, the second input end of the first operational amplifier receives the rough adjusting current, and the output end of the first operational amplifier is connected with the control end of the eighth transistor;

and the source end of the eighth transistor is connected with the second input end of the first operational amplifier, and the drain end of the eighth transistor outputs the coarse tuning current.

27. The dac of claim 21 or 25 wherein the second bias block comprises a second operational amplifier, wherein the second operational amplifier has a first input terminal receiving the reference current, a second input terminal receiving the current to be fine-tuned and connected to source terminals of a plurality of seventh transistors of the plurality of second current source units, and an output terminal connected to a control terminal of the seventh transistor.

28. The digital-to-analog converter of claim 25, wherein the third digital-to-analog conversion module further comprises a third operational amplifier and an eighteenth transistor,

the first input end of the third operational amplifier receives the reference current, the second input end of the third operational amplifier receives the coarse tuning current, and the output end of the third operational amplifier is connected with the control end of the eighteenth transistor;

and the source end of the eighteenth transistor is connected with the second input end of the third operational amplifier, and the drain end of the eighteenth transistor outputs the coarse tuning current.

29. The dac of claim 25 wherein the third bias block comprises a second operational amplifier and a fourth operational amplifier, wherein the second operational amplifier has a first input terminal receiving the reference current, a second input terminal receiving the current to be fine-tuned and connected to source terminals of a plurality of seventh transistors of the plurality of second current source units, and an output terminal connected to a control terminal of the seventh transistor; the first input end of the fourth operational amplifier receives the reference current, the second input end of the fourth operational amplifier receives the current to be finely adjusted and is connected with the source ends of a plurality of seventeenth transistors in the plurality of fourth current source units, and the output end of the fourth operational amplifier is connected with the control ends of the seventeenth transistors.

30. The digital to analog converter according to claim 17, wherein the control module further comprises:

the plurality of cascaded first control units generate a plurality of first control signals and a plurality of second control signals according to the enable signal, the plurality of first row control signals and the plurality of first column control signals, and respectively control the current flow direction of corresponding first current switch units in the first digital-to-analog conversion module;

a second decoder for decoding upper N1 bits of the second digital signal to output a plurality of second row control signals and decoding lower N2 bits of the second digital signal to output a plurality of second column control signals, wherein M = N1+ N2, and M1 and M2 are positive integers;

the plurality of cascaded second control units generate a plurality of third control signals and a plurality of fourth control signals according to the plurality of second row control signals, the plurality of second column control signals and the pulse width modulation signals, and respectively control the current flow direction of corresponding second current switching units in the second digital-to-analog conversion module;

the plurality of cascaded third control units generate a plurality of fifth control signals and a plurality of sixth control signals according to the enable signal, the plurality of first row control signals and the plurality of first column control signals, and respectively control the current flow direction of corresponding third current switch units in the third digital-to-analog conversion module;

the plurality of cascaded fourth control units generate a plurality of seventh control signals and a plurality of eighth control signals according to the enable signal, the plurality of second row control signals and the plurality of second column control signals, and respectively control the current flow direction of corresponding fourth current switch units in the fourth digital-to-analog conversion module; controlling the magnitude of the output current of the selected fourth current switch unit according to the pulse width modulation signal;

when the enable signal is at an effective level, the first digital-to-analog conversion module and the second digital-to-analog conversion module work, and the third digital-to-analog conversion module and the fourth digital-to-analog conversion module do not work.

31. The dac of claim 30 wherein the first row control signals and the first column control signals form 2 ^M1 *2 ^M2 The matrix is used for controlling the current flow direction of a corresponding first current switch unit in the first digital-to-analog conversion module by a first control signal and a second control signal generated by a corresponding first row control signal and a corresponding first column control signal when the enable signal is at an effective level; when the enable signal is at an inactive level, a fifth control signal and a sixth control signal generated by the corresponding first row control signal and the first column control signal control the current flowing direction of a corresponding third current switch unit in the third digital-to-analog conversion module.

32. The dac of claim 30 wherein the first and third control units each comprise a first input, a second input, an enable input, a cascade input, a first output, a second output, and a cascade output, wherein the first and second inputs receive the corresponding first row control signal and first column control signal, respectively, and the enable input receives the enable signal;

the cascade input end of the first control unit receives a first cascade signal output by a first control unit at the previous stage, the first output end outputs a first control signal, the second output end outputs a second control signal, and the cascade output end outputs the first cascade signal;

the cascade input end receives a third cascade signal output by the upper-stage third control unit, the first output end outputs a fifth control signal, the second output end outputs a sixth control signal, and the cascade output end outputs the third cascade signal.

33. The dac of claim 32 wherein the cascade input terminals of the first and third control units at the head end are inactive and the cascade output terminals of the first and third control units at the tail end are floating.

34. The digital-to-analog converter according to claim 32, wherein the first control unit and the third control unit each comprise a first not gate, a second not gate, a first nor gate, a second nor gate, and a third not gate;

the input end of the second NOT gate receives a first column control signal;

the first input end of the first NOR gate is connected with the output end of the first NOR gate, the second input end of the first NOR gate is connected with the output end of the second NOR gate, the output end of the first control unit outputs a first control signal, and the output end of the third control unit outputs a third control signal;

a first input end of a second NOR gate in the first control unit receives a first control signal, a second input end of the second NOR gate receives a first cascade signal output by a first control unit at the previous stage, and an output end of the second NOR gate outputs a second control signal;

a first input end of a second NOR gate in the third control unit receives a fifth control signal, a second input end of the second NOR gate receives a third cascade signal output by the third control unit at the previous stage, and an output end of the second NOR gate outputs a sixth control signal;

the input end of a third NOT gate in the first control unit receives the second control signal, and the output end outputs a first cascade signal;

the input end of a third NOT gate in the third control unit receives a sixth control signal, and the output end of the third NOT gate outputs a third cascade signal;

a third input end of a first NOR gate in the first control unit receives an enable signal;

the third input terminal of the first nor gate in the third control unit receives a disable signal, wherein the disable signal is opposite to the enable signal in level.

35. The dac of claim 30 wherein the second plurality of row control signals and the second plurality of column control signals form 2 ^N1 *2 ^N2 The matrix is used for controlling the current flow direction of a corresponding second current switch unit in the second digital-to-analog conversion module by a third control signal and a fourth control signal generated by a corresponding second row control signal and a second column control signal when the enable signal is at an effective level; and when the enable signal is at an invalid level, the seventh control signal and the eighth control signal generated by the corresponding second row control signal and second column control signal control the current flowing direction of the corresponding fourth current switch unit in the fourth digital-to-analog conversion module.

36. The dac of claim 30 wherein the second and fourth control units each comprise a first input terminal, a second input terminal, an enable input terminal, a cascade input terminal, a first output terminal, a second output terminal, and a cascade output terminal, wherein the first and second input terminals respectively receive the corresponding second row control signal and second column control signal, and the enable input terminal receives the enable signal;

the cascade input end of the second control unit receives the second cascade signal output by the second control unit of the previous stage, the first output end outputs a third control signal, the second output end outputs a fourth control signal, and the cascade output end outputs the second cascade signal;

the cascade input end of the fourth control unit receives the fourth cascade signal output by the fourth control unit of the previous stage, the first output end outputs the seventh control signal, the second output end outputs the eighth control signal, and the cascade output end outputs the fourth cascade signal.

37. The dac of claim 36 wherein the cascade input terminals of the first and second control units are inactive and the cascade output terminals of the second and fourth control units are floating.

38. The dac of claim 36 wherein the second and fourth control units each comprise a fourth not gate, a fifth not gate, a third nor gate, a fourth nor gate, a selector, a sixth not gate, a seventh not gate, and an eighth not gate;

the input end of the fourth NOT gate receives a second row control signal;

the input end of the fifth NOT gate receives a second column control signal;

a first input end of the fourth NOR gate is connected with an output end of the third NOR gate, a second input end of the second control unit receives a second cascade signal output by the second control unit of the previous stage, and a second input end of the fourth control unit receives a fourth cascade signal output by the fourth control unit of the previous stage;

the input end of the sixth not gate is connected with the output end of the selector, the output end of the second control unit outputs a third control signal, and the output end of the second control unit outputs a seventh control signal;

the input end of the seventh not gate is connected with the output end of the sixth not gate, the output end of the second control unit outputs a fourth control signal, and the output end of the fourth control unit outputs an eighth control signal;

the input end of the eighth NOR gate is connected with the output end of the fourth NOR gate, the output end of the second control unit outputs a second cascade signal, and the output end of the fourth control unit outputs a fourth cascade signal;

a third input end of a third NOR gate in the second control unit receives an enable signal;

the third input terminal of the third nor gate in the fourth control unit receives a disable signal, wherein the disable signal is opposite to the enable signal in level.

39. The digital-to-analog converter according to claim 1 or 17, further comprising:

and the offset module is positioned between the output end of the digital-to-analog converter and the redundant node and is used for eliminating the offset voltage of an operational amplifier in the digital-to-analog converter.

40. The DAC of claim 39 wherein the offset module comprises a fifth operational amplifier, a sixth operational amplifier and first to fourth switches,

the first input end of the fifth operational amplifier is connected with the output end of the digital-to-analog converter, and is connected with the first input end of the sixth operational amplifier through a first switch;

a second input terminal of the fifth operational amplifier is connected to the redundant node and to a second input terminal of the sixth operational amplifier via a second switch;

the output end of the fifth operational amplifier is connected with the first input end of the sixth operational amplifier through a third switch and is connected with the second input end of the sixth operational amplifier through a fourth switch;

and the output end of the sixth operational amplifier is connected with a redundant node.