CN115694474A

CN115694474A - 1.5 frequency divider based on phase interpolator

Info

Publication number: CN115694474A
Application number: CN202110866194.3A
Authority: CN
Inventors: 李承哲; 陈泽; 钟英权
Original assignee: Jiyiwei Semiconductor Shanghai Co ltd
Current assignee: Jiyiwei Semiconductor Shanghai Co ltd
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2023-02-03

Abstract

The application relates to the technical field of integrated circuits, and discloses a 1.5 frequency divider based on a phase interpolator, which comprises: the frequency divider for dividing 1.5, the phase interpolator and the duty ratio adjusting module are connected in sequence. The divide-by-1.5 frequency divider outputs a pair of divided signals having a duty ratio of 1/3 of positive phase and negative phase and a division ratio of 1.5 according to a pair of positive phase and negative phase clock signals, and the phases of the pair of divided signals differ by 1/3 cycle. The phase interpolator slows down the signal edge of the pair of frequency division signals and outputs an interpolation signal to the duty ratio adjusting module, wherein the phase of the interpolation signal is an average value of the phases of the pair of frequency division signals. The duty ratio adjusting module adjusts the duty ratio of the interpolation signal to 1/2.

Description

1.5 frequency divider based on phase interpolator

Technical Field

The present invention relates generally to the field of integrated circuit technology, and more particularly to a 1.5 frequency divider based on a phase interpolator.

Background

Assuming that the frequency synthesizer is capable of generating a signal with a frequency range of twice, a voltage controlled oscillator with a frequency range of twice tuning needs to be designed, but a voltage controlled oscillator with a frequency range of twice tuning is generally difficult to implement because the noise of the voltage controlled oscillator and the tuning range in the voltage controlled oscillator often have a trade-off relationship. In practical design processes, two voltage controlled oscillators are generally needed to achieve twice the tuning frequency coverage, but this greatly increases the cycle time of the circuit design and the area occupied by the circuit. Assuming a divide-by-1.5 divider with an output duty cycle of 50%, the tuning range of the vco can be reduced by one third, which allows the design objective to be met by a single resonator. The following methods are currently available for implementing a 1.5 frequency divider:

1. the signal is divided into three parts by a logic circuit, and then 2 times of frequency of the signal is multiplied by a phase-locked loop structure based on a ring oscillator, so that the function of 1.5 frequency division is finally obtained. The ring oscillator has poor noise performance and is not suitable for use in high speed, high precision applications. In addition, the scheme based on the phase-locked loop technology needs to consider the problems of the tuning range of the ring oscillator, the stability of a phase-locked loop and the like, so that the design complexity of the system is greatly increased.

2. The signal is divided by three through a logic circuit, then the frequency division by 2 is realized through a sub-harmonic injection locking mode, and the function of frequency division by 1.5 can also be realized. However, this solution would require an extra resonant cavity, which greatly increases the loop area, and the injection locking technique would cause a large spurs, which greatly deteriorates the fixed jitter of the output signal, and it is difficult to achieve 50% duty cycle output.

3. The frequency mixing is carried out on the input clock signal and the signal with one third of the input clock frequency, then the low-pass filtering is carried out on the signal obtained by the frequency mixing, so that the signal with two thirds of the input clock frequency can be obtained, a 1.5 frequency divider based on a frequency mixer structure has redundant stray which is difficult to filter, the fixed jitter of the output signal is greatly deteriorated, meanwhile, the output signal is difficult to realize the output with 50 percent of duty ratio, and the defects limit the wide application of the scheme.

Disclosure of Invention

The invention aims to provide a 1.5 frequency divider based on a phase interpolator, which reduces the tuning range of a voltage-controlled oscillator.

The application discloses 1.5 frequency divider based on phase interpolator includes: the divide-by-1.5 frequency divider and the phase interpolator are connected in sequence; wherein, the first and the second end of the pipe are connected with each other,

the divide-by-1.5 frequency divider outputs a pair of divided signals having a duty ratio of 1/3 and a frequency dividing ratio of 1.5 in a pair of positive and negative phase clock signals, and the phases of the pair of divided signals differ by 1/3 period;

the phase interpolator slows down the signal edges of the pair of frequency division signals and outputs an interpolation signal, wherein the phase of the interpolation signal is an average value of the phases of the pair of frequency division signals.

In a preferred embodiment, the divide-by-1.5 frequency divider includes:

a divide-by-3 divider, the divide-by-3 divider comprising a first flip-flop, a second flip-flop, and a first nand logic, the pair of positive and negative clock signals each being coupled to the first flip-flop and the second flip-flop, an output of the first flip-flop outputting a first divided signal and being connected to a first input of the first nand logic, an output of the first nand logic outputting a second divided signal and being connected to an input of the second flip-flop, an output of the second flip-flop outputting a third divided signal and being connected to a second input of the first nand logic and an input of the first flip-flop;

the first frequency multiplier acquires the second path of frequency division signals and the third path of frequency division signals and outputs frequency division signals with the normal phase duty ratio of 1/3 and the frequency division ratio of 1.5;

and the second frequency multiplier acquires the first path of frequency division signal and the second path of frequency division signal and outputs a frequency division signal with a phase difference of 1/3 period with the normal-phase frequency division signal to the first phase inverter, wherein the frequency division signal has a frequency division ratio of 1.5, and the first phase inverter outputs a frequency division signal with an inverted duty ratio of 1/3 and a frequency division ratio of 1.5.

In a preferred embodiment, the first frequency multiplier includes a third flip-flop, a first latch, a first nor logic, a second nor logic, and a third nor logic, the pair of positive and negative clock signals are coupled to the third flip-flop and the first latch, an input terminal of the first latch is coupled to the second divided signal, an output terminal of the first latch and the positive clock signal are coupled to two input terminals of the second nor logic, an input terminal of the third flip-flop is coupled to the third divided signal, an output terminal of the third flip-flop and the negative clock signal are coupled to two input terminals of the first nor logic, an output terminal of the first nor logic and an output terminal of the second nor logic are coupled to two input terminals of the third nor logic, and the third nor logic outputs the divided signal with the positive duty cycle of 1/3 and the division ratio of 1.5.

In a preferred example, the first flip-flop, the second flip-flop, and the third flip-flop are D flip-flops.

In a preferred embodiment, the first frequency multiplier includes a fourth flip-flop, a second latch, a fourth nor logic, a fifth nor logic, and a sixth nor logic, the pair of positive-phase and inverted clock signals are coupled to the fourth flip-flop and the second latch, an input terminal of the second latch is coupled to the second divided signal, an output terminal of the second latch and the positive-phase clock signal are coupled to two input terminals of the fifth nor logic, an input terminal of the fourth flip-flop is coupled to the first divided signal, an output terminal of the fourth flip-flop and the inverted clock signal are coupled to two input terminals of the fourth nor logic, an output terminal of the fourth nor logic and an output terminal of the fifth nor logic are coupled to two input terminals of the sixth nor logic, and the sixth nor logic outputs a divided signal that differs from the positive-phase divided signal by a duty ratio of 2/3 and a duty ratio of 1.5 in phase.

In a preferred embodiment, the first flip-flop, the second flip-flop and the fourth flip-flop are D flip-flops.

In a preferred embodiment, the phase interpolator includes: the interpolation signal processing circuit comprises a second phase inverter, a third phase inverter, a first resistor, a second resistor, a first adjustable resistor and a second adjustable resistor, wherein the input end of the second phase inverter is coupled to the normal-phase frequency division signal, the output end of the second phase inverter is connected with one end of the first resistor and one end of the first adjustable resistor, the other end of the first adjustable resistor is grounded, the input end of the third phase inverter is coupled to the inverted-phase frequency division signal, the output end of the third phase inverter is connected with one end of the second resistor and one end of the second adjustable resistor, the other end of the second adjustable resistor is grounded, and the other end of the first resistor and the other end of the second resistor are connected and output the interpolation signal.

In a preferred embodiment, the method further comprises the following steps: a duty cycle adjustment module that receives the interpolated signal and adjusts a duty cycle of the interpolated signal to 1/2, the duty cycle adjustment module comprising: the interpolation circuit comprises a first capacitor, a second capacitor, a first adjustable phase inverter, a second adjustable phase inverter, a third resistor and a fourth resistor, wherein one end of the first capacitor is connected with the interpolation signal, the other end of the first capacitor is connected with the input end of the first adjustable phase inverter, the output end of the first adjustable phase inverter is connected with one end of the second capacitor, the other end of the second capacitor is connected with the input end of the second adjustable phase inverter, the third resistor is connected between the input end and the output end of the first adjustable phase inverter, and the fourth resistor is connected between the input end and the output end of the second adjustable phase inverter.

In a preferred embodiment, the ratio of the transistors of the first and/or second adjustable inverter is adjusted to adjust the threshold voltage of the first and/or second adjustable inverter.

In a preferred embodiment, the threshold voltages of the first adjustable inverter and the second adjustable inverter are adjusted in opposite directions.

Compared with the prior art, the 1.5 frequency divider based on the phase interpolator has the following beneficial effects:

1. the 1.5 frequency divider scheme based on the phase interpolator can be used in high-speed and high-precision applications, because the speed of the phase interpolator is basically close to that of the inverter, the 1.5 frequency divider of the phase interpolator can realize very high working frequency and very low power consumption.

2. An output signal with a duty cycle of 50% can be accurately realized by the phase interpolator and the duty cycle adjusting circuit.

3. Because the output signal is realized by a mode of obtaining the phase interpolation, and the phase interpolation only needs to adjust a small equivalent delay in high-speed application, the output jitter can be smaller.

4. The circuit can be realized by using a very simple analog circuit structure, even no operational amplifier is provided, and large-area passive capacitor and passive inductor are not needed, so that the area of the circuit is greatly reduced, the cost is saved, and meanwhile, the circuit is convenient for the migration of process nodes.

5. Because the phase interpolator is an open-loop structure, the problems of loop stability and the like do not need to be considered like a phase-locked loop structure, and the implementation of the phase interpolator in the scheme is simpler, the complexity of circuit design can be greatly reduced.

6. Because the scheme is realized based on the structure of the phase interpolator, the phase interpolation has good robustness compared with other open-loop calibration modes, and the scheme can be ensured to have good consistency under different process angles, power supply voltages and temperatures.

7. Differential signals can be implemented as input signals without the need for multi-phase clocks as input signals, thus greatly reducing the requirements on the input clock circuit.

8. The circuit can be generally used for reducing the tuning range of the voltage-controlled oscillator, so that the difficulty of compromise of various indexes in the circuit of the voltage-controlled oscillator can be reduced, and the occupied area of the voltage-controlled oscillator can be reduced.

A large number of technical features are described in the specification, and are distributed in various technical solutions, so that the specification is too long if all possible combinations of the technical features (namely, the technical solutions) in the application are listed. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present specification, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of the technical features is technically impossible. For example, in one example, feature a + B + C is disclosed, in another example, feature a + B + D + E is disclosed, and features C and D are equivalent technical means that serve the same purpose, technically only one feature is used, but not both, and feature E may be technically combined with feature C, then the solution of a + B + C + D should not be considered as already described because the technology is not feasible, and the solution of a + B + C + E should be considered as already described.

Drawings

Fig. 1 shows a schematic diagram of a phase interpolator based 1.5 divider in an embodiment of the present invention.

Fig. 2 shows a schematic diagram of a divide-by-1.5 divider in an embodiment of the invention.

Fig. 3 shows a divide-by-3 divider in an embodiment of the invention.

Fig. 4 shows a schematic diagram of a first frequency multiplier according to an embodiment of the invention.

Fig. 5 is a waveform diagram of a divide-by-1.5 frequency divider to form a normal phase divided signal according to an embodiment of the present invention.

Fig. 6 shows a schematic diagram of a phase interpolator in an embodiment of the invention.

Fig. 7 shows a waveform diagram of the phase interpolator according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of a duty cycle adjustment module in an embodiment of the invention.

Detailed Description

Various aspects and examples of the present application will now be described. The following description provides specific details for a thorough understanding and enabling description of these examples. However, it will be understood by those skilled in the art that the present application may be practiced without many of these details.

Additionally, some well-known structures or functions may not be shown or described in detail to facilitate brevity and avoid unnecessarily obscuring the relevant description.

The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific examples of the application. Certain terms may even be emphasized below, however, any term that is intended to be interpreted in any restricted manner will be explicitly and specifically defined in this detailed description section.

One embodiment of the present application provides a phase interpolator based 1.5 frequency divider, and fig. 1 shows a block diagram of a phase interpolator based 1.5 frequency divider 100. The 1.5 frequency divider 100 includes: divide by 1.5 frequency divider 110, phase interpolator 120, and duty cycle adjustment module 130.

The divide-by-1.5 frequency divider 110 outputs a pair of divided signals 1p5_out1,1p5 _uout 2 having a frequency dividing ratio of 1.5 with a duty ratio of 1/3 for the positive phase and the negative phase according to a pair of positive phase and negative phase clock signals clk, clkb, and the phases of the pair of divided signals 1p5 _uout 1,1p5 _uout 2 are different by 1/3 cycle.

The phase interpolator 120 slows down the signal edges of the pair of frequency-divided signals 1p5_out1,1p5_out2 and outputs an interpolated signal pi _ out, the phase of which is an average of the phases of the pair of frequency-divided signals 1p5_out1,1p5_out2, to the duty ratio adjustment module 130. The duty ratio adjusting module 130 adjusts the duty ratio of the interpolated signal pi _ out to 1/2.

In a preferred embodiment, fig. 2 shows a block diagram of a divide-by-1.5 frequency divider 110, the divide-by-1.5 frequency divider comprising: a divide-by-3 divider 111, a first frequency multiplier 112, a second frequency multiplier 113, and a first inverter 114. The divide-by-3 divider 111 couples a pair of positive and negative clock signals clk, clkb to produce three divided signals D1, D2, D3. The two paths D2 and D3 are coupled to the first frequency multiplier 112, and a pair of positive phase and inverted clock signals clk and clkb in the first frequency multiplier 112 perform logic operation on the two paths of frequency division signals D2 and D3 to form a frequency division signal 1p5_out1 with a positive phase duty ratio of 1/3 and a frequency division ratio of 1.5. The two paths of signals D1 and D2 are coupled to the second frequency multiplier 113, a pair of normal phase and inverted clock signals clk in the second frequency multiplier 113, clkb perform logic operation on the two paths of frequency division signals D1 and D2 to form frequency division signals with duty ratio of 1/3 and frequency division ratio of 1.5, and then the frequency division signals are inverted by the first inverter 114 to form the frequency division signals 1p5 u out2 with inverted duty ratio of 1/3 and frequency division ratio of 1.5.

In one embodiment, fig. 3 shows a schematic diagram of divide-by-3 divider 111. The divide-by-3 divider comprises a first flip-flop 1111, a second flip-flop 1112 and a first nand logic 1113, the pair of positive and negative clock signals clk, clkb are coupled to the first flip-flop 1111 and the second flip-flop 1112, an output of the first flip-flop 1111 outputs a first divided signal D1 and is connected to a first input of the first nand logic 1113, an output of the first nand logic 1113 outputs a second divided signal D2 and is connected to an input of the second flip-flop 1112, and an output of the second flip-flop 1113 outputs a third divided signal D3 and is connected to a second input of the first nand logic 1113 and an input of the first flip-flop 1111.

And the first frequency multiplier acquires the second path of frequency division signals and the third path of frequency division signals and outputs frequency division signals with the normal phase duty ratio of 1/3 and the frequency division ratio of 1.5. In one embodiment, fig. 4 shows a schematic diagram of the first frequency multiplier 112. The first frequency multiplier 112 includes a third flip-flop 1121, a first latch 1122, a first nor logic 1123, a second nor logic 1124, and a third nor logic 1125, the pair of positive and negative clock signals clk, clkb are coupled to the third flip-flop 1121 and the first latch 1122, an input terminal of the first latch 1122 is coupled to the second divided signal D2, an output terminal of the first latch 1122 and the positive clock signal clk are coupled to both input terminals of the second nor logic 1124, an input terminal of the third flip-flop 1121 is coupled to the third divided signal D3, an output terminal of the third flip-flop 1121 and the negative clock signal clkb are coupled to both input terminals of the first nor logic 1123, an output terminal of the first nor logic 1123 and an output terminal of the second nor logic 1124 are coupled to both input terminals of the third nor logic 1125, and the third nor logic 1125 outputs the positive clock signal with a duty ratio of 1/3 and a division ratio of 1.5 of the divided signal 1pu 1/ouu.

The second frequency multiplier acquires the first path of frequency division signal and the second path of frequency division signal and outputs a frequency division signal with a phase difference of 1/3 period with the normal phase frequency division signal to the first phase inverter, wherein the duty ratio of the frequency division signal is 2/3, the frequency division ratio of the frequency division signal is 1.5, and the first phase inverter outputs a frequency division signal with an inverted duty ratio of 1/3 and a frequency division ratio of 1.5. In one embodiment, the first frequency multiplier includes a fourth flip-flop, a second latch, a fourth nor logic, a fifth nor logic, and a sixth nor logic, the pair of positive and negative phase clock signals are coupled to the fourth flip-flop and the second latch, an input terminal of the second latch is coupled to the second divided signal, an output terminal of the second latch and the positive phase clock signal are coupled to two input terminals of the fifth nor logic, an input terminal of the fourth flip-flop is coupled to the first divided signal, an output terminal of the fourth flip-flop and the negative phase clock signal are coupled to two input terminals of the fourth nor logic, an output terminal of the fourth nor logic and an output terminal of the fifth nor logic are coupled to two input terminals of the sixth nor logic, and the sixth nor logic outputs a divided signal having a duty ratio of 2/3 and a ratio of 1.5 different from the phase of the positive phase divided signal by 1/3 cycle. The frequency-divided signal passes through the first inverter 114 to form a frequency-divided signal 1p5/u out2 having an inverted duty ratio of 1/3 and a frequency division ratio of 1.5.

In one embodiment, the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are D flip-flops.

In one embodiment, fig. 6 shows a schematic diagram of phase interpolator 120. The phase interpolator 120 includes: the circuit comprises a second inverter 121, a third inverter 122, a first resistor R1, a second resistor R2, a first adjustable resistor RX1 and a second adjustable resistor RX2. An input end of the second inverter 121 is coupled to the non-inverted frequency-divided signal 1p5_out1, an output end of the second inverter 121 is connected to one end of the first resistor R1 and one end of the first adjustable resistor RX1, the other end of the first adjustable resistor RX2 is connected to ground, an input end of the third inverter 122 is coupled to the inverted frequency-divided signal 1p5_out2, an output end of the third inverter 122 is connected to one end of the second resistor R2 and one end of the second adjustable resistor RX2, the other end of the second adjustable resistor RX2 is connected to ground, and the other end of the first resistor R1 and the other end of the second resistor R2 are connected to output the interpolated signal pi _ out. Fig. 7 shows a waveform diagram of the phase interpolator 120.

In one embodiment, fig. 8 shows a schematic diagram of the duty cycle adjustment module 130. The duty cycle adjusting module 130 includes: a first capacitor C1, a second capacitor C2, a first adjustable inverter 131, a second adjustable inverter 132, a third resistor R3 and a fourth resistor R4. One end of the first capacitor C1 is connected to the interpolation signal pi _ out, the other end of the first capacitor C1 is connected to the input end of the first adjustable inverter 131, the output end of the first adjustable inverter 131 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the input end of the second adjustable inverter 132, the third resistor R3 is connected between the input end and the output end of the first adjustable inverter 131, and the fourth resistor R4 is connected between the input end and the output end of the second adjustable inverter 132.

In one embodiment, the ratio of the transistors of the first tunable inverter 131 and/or the second tunable inverter 132 is adjusted to adjust the threshold voltage of the first tunable inverter 131 and/or the second tunable inverter 132. In one embodiment, the threshold voltages of the first tunable inverter 131 and the second tunable inverter 132 are tuned in opposite directions.

The operation of the 1.5 divider based on the phase interpolator of the present application is described below.

As shown in fig. 1, the phase interpolator based 1.5 frequency divider includes a frequency divider 110 with a division ratio of 1.5, a phase interpolator 120, and a duty cycle adjustment module 130.

A frequency divider with an output duty cycle of 1/3 and a division ratio of 1.5 is shown in fig. 2. The module consists of two parts: one part is a divide-by-3 divider and the other part is two multipliers. Wherein fig. 3 is a specific implementation of a divide-by-3 divider and fig. 4 is a specific implementation of a frequency multiplier. Firstly, a frequency divider 3 is used for generating a frequency divided signal 3, then two paths of retimed three-frequency-divided signals are respectively selected through a positive phase clock and a reverse phase clock, and the two paths of signals selected by the clock form a 1.5 frequency-divided output signal with the duty ratio of 1/3 through a NOR gate, which is equivalent to frequency multiplication of the frequency divided signal 3. The signal waveform of each node is 5, wherein T2, T4, T3 and T5 are signals of nodes in the frequency multiplier with output signal of 1p5_out1. It should be noted that the two frequency multipliers have the same structure, which is not described herein, and the phase difference between the output signals of the two frequency multipliers is 2/3 cycle due to the selection of different paths of the 3-frequency division signals, and after inversion, the phase difference between the frequency division signal 1p5_out2 and the frequency division signal 1p5 _out1is 1/3 cycle.

The invention provides only one embodiment of frequency division by 1.5, and it is of course possible to implement the function of frequency division by 1.5 by other logic circuits.

A specific implementation of the phase interpolator block is shown in fig. 6. The basic principle of the phase interpolator is to first slow the signal edges of the input 1p5_out1 and 1p5_out2 signals, which is advantageous for improving the linearity of the phase interpolation, so that the phase of the phase interpolator output signal pi _ out is substantially close to the result of the ideal phase interpolation, and the duty cycle of the phase interpolator output signal pi _ out is substantially 50%. The phase interpolation circuit is realized by two inverters coupled by an external resistor, the sizes of the two inverters are the same as the resistance value of the external resistor, so that the phase output by the phase interpolator is the average of the phases of signals 1p5_out1 and 1p5_out2, and the duty ratio of the output signal is calibrated to be 50%. The specific signal waveform of this module is shown in fig. 7.

It should be understood that a 1.5 divider implemented using another phase interpolator architecture is also possible. The same effect can be achieved, for example, using a current steering phase interpolator, instead of the implementation of fig. 6.

The circuit of the duty cycle adjusting module is shown in fig. 8. The duty cycle adjusting module is based on the structure of a blocking inverter with adjustable threshold voltage. The adjustment of the signal duty ratio is realized by combining two modes of DC blocking and threshold voltage adjustment. The threshold voltages of the two cascaded blocking inverters need to be adjusted in opposite directions, so that the adjustment is also beneficial to compensating the problems of circuit mismatch and the like by using the symmetry of the circuit. The threshold voltage is adjusted by adjusting the proportion of PMOS tube and NMOS tube in the inverter. The duty cycle adjustment module may not be necessary in some application scenarios.

In other embodiments of the present application, the duty cycle adjustment module may use a feedback loop pair to ensure an accurate 50% duty cycle output. It should be appreciated that the actual circuit implementation of the phase interpolator may not even require a duty cycle adjustment module in other embodiments of the present application, if the performance of the phase interpolator is good.

It should be noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.

The term "coupled to" and its derivatives may be used herein. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but yet still co-operate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled to each other.

This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiments; however, these embodiments are not mutually exclusive, unless indicated as mutually exclusive or as would be apparent to one of ordinary skill in the art. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly dictates otherwise.

All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of the present application so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.

Claims

1. A phase interpolator based 1.5 frequency divider, comprising: the divide-by-1.5 frequency divider and the phase interpolator are connected in sequence; wherein the content of the first and second substances,

the phase interpolator slows down the signal edge of the pair of frequency division signals and outputs an interpolation signal, and the phase of the interpolation signal is an average value of the phases of the pair of frequency division signals.

2. The phase interpolator based 1.5 frequency divider of claim 1, wherein the divide-by-1.5 frequency divider comprises:

3. The phase interpolator based 1.5 frequency divider of claim 2, wherein the first frequency multiplier comprises a third flip-flop, a first latch, a first nor logic, a second nor logic, and a third nor logic, the pair of positive and negative phase clock signals are coupled to the third flip-flop and the first latch, an input of the first latch is coupled to the second path of divided signals, an output of the first latch and the positive phase clock signal are coupled to two inputs of the second nor logic, an input of the third flip-flop is coupled to the third path of divided signals, an output of the third flip-flop and the negative phase clock signal are coupled to two inputs of the first nor logic, an output of the first nor logic and an output of the second nor logic are coupled to two inputs of the third nor logic, and the third nor logic outputs a divided signal having a duty cycle of the positive phase of 1/3 and a divided signal ratio of 1.5.

4. The phase interpolator based 1.5 frequency divider of claim 3, wherein the first flip-flop, the second flip-flop and the third flip-flop are D flip-flops.

5. The phase interpolator based 1.5 frequency divider of claim 2, wherein the first frequency multiplier comprises a fourth flip-flop, a second latch, a fourth nor logic, a fifth nor logic, and a sixth nor logic, the pair of positive and negative clock signals are coupled to the fourth flip-flop and the second latch, an input of the second latch is coupled to the second divided signal, an output of the second latch and the positive clock signal are coupled to two inputs of the fifth nor logic, an input of the fourth flip-flop is coupled to the first divided signal, an output of the fourth flip-flop and the negative clock signal are coupled to two inputs of the fourth nor logic, an output of the fourth nor logic and an output of the fifth nor logic are coupled to two inputs of the sixth nor logic, the sixth nor logic output differs from the positive divided signal by a duty cycle of 1/3 cycle in phase, and has a division ratio of 1.5.

6. The phase interpolator based 1.5 frequency divider of claim 5, wherein the first flip-flop, the second flip-flop, and the fourth flip-flop are D flip-flops.

7. The phase interpolator based 1.5 divider of claim 1, wherein the phase interpolator comprises: the interpolation signal processing circuit comprises a second phase inverter, a third phase inverter, a first resistor, a second resistor, a first adjustable resistor and a second adjustable resistor, wherein the input end of the second phase inverter is coupled to the normal-phase frequency division signal, the output end of the second phase inverter is connected with one end of the first resistor and one end of the first adjustable resistor, the other end of the first adjustable resistor is grounded, the input end of the third phase inverter is coupled to the inverted-phase frequency division signal, the output end of the third phase inverter is connected with one end of the second resistor and one end of the second adjustable resistor, the other end of the second adjustable resistor is grounded, and the other end of the first resistor and the other end of the second resistor are connected and output the interpolation signal.

8. The phase interpolator based 1.5 frequency divider of claim 1, further comprising: a duty cycle adjustment module that receives the interpolated signal and adjusts a duty cycle of the interpolated signal to 1/2, the duty cycle adjustment module comprising: the interpolation circuit comprises a first capacitor, a second capacitor, a first adjustable phase inverter, a second adjustable phase inverter, a third resistor and a fourth resistor, wherein one end of the first capacitor is connected with the interpolation signal, the other end of the first capacitor is connected with the input end of the first adjustable phase inverter, the output end of the first adjustable phase inverter is connected with one end of the second capacitor, the other end of the second capacitor is connected with the input end of the second adjustable phase inverter, the third resistor is connected between the input end and the output end of the first adjustable phase inverter, and the fourth resistor is connected between the input end and the output end of the second adjustable phase inverter.

9. The phase interpolator based 1.5 frequency divider of claim 8, wherein a ratio of transistors of the first adjustable inverter and/or the second adjustable inverter is adjusted to adjust a threshold voltage of the first adjustable inverter and/or the second adjustable inverter.

10. The phase interpolator based 1.5 frequency divider of claim 9, wherein the threshold voltages of the first adjustable inverter and the second adjustable inverter are adjusted in opposite directions.