US11184016B2 - Multiple-moduli ring-oscillator-based frequency divider - Google Patents
Multiple-moduli ring-oscillator-based frequency divider Download PDFInfo
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- US11184016B2 US11184016B2 US17/145,886 US202117145886A US11184016B2 US 11184016 B2 US11184016 B2 US 11184016B2 US 202117145886 A US202117145886 A US 202117145886A US 11184016 B2 US11184016 B2 US 11184016B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
- H03K3/0322—Ring oscillators with differential cells
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0997—Controlling the number of delay elements connected in series in the ring oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
Definitions
- This invention relates generally to electronic circuit design, and more specifically, to electronic frequency dividers with dynamically adjustable division ratios.
- Modern frequency synthesizers see an ever increasing demand for higher operation frequency and lower power consumption.
- implementations based on phase-locked loops (PLLs) typically generate the output frequency from a stable, low-frequency reference such as a crystal. Therefore, in the loop's feedback path, the output frequency of the voltage-controlled oscillator (VCO) needs to be divided down to the input frequency provided by the reference. This necessitates the use of a frequency divider.
- Frequency dividers may generate lower-frequency output signals from higher-frequency input signals, where the output frequency is equal to the input frequency divided by a positive integer, known as the division ratio or the modulus.
- An injection-locked frequency divider may be constructed from a tuned oscillator that is injection locked to a higher-frequency input signal over a range of input frequencies.
- another design consideration for the frequency divider is the configurability of different division ratios.
- frequency dividers suitable for use as a prescaler in the feedback path of a phase-locked loop (PLL)-based frequency synthesizer entail a number of design challenges, including low power consumption and the availability of multiple moduli that can be dynamically switched among during the divider's operation.
- PLL phase-locked loop
- FIG. 1 is a block diagram of an example phase-locked loop-based frequency synthesizer that embodies one or more techniques disclosed here, where the synthesizer includes an injection-locked multiple-moduli prescaler as the first frequency divider in the feedback path.
- FIG. 2A is a circuit schematic of an example injection-locked dual-modulus prescaler implemented using a single-ended inverter-chain ring oscillator capable of dividing by 1:2 and 1:3.
- FIG. 2B is a table showing an example of how to choose the stages that are to be injected into by the (e.g., quadrature) injections for the 1:2 division ratio.
- FIG. 2C is a table showing an example of how to choose the stages that are to be injected into by the (e.g., quadrature) injections for the 1:3 division ratio.
- FIG. 3 is a circuit schematic of an example implementation of an inverter that can be used to implement the example ring oscillator of FIG. 2A .
- FIG. 4 shows circuit schematics of two example implementations of the injection current source that can be used to inject into the example ring oscillator of FIG. 2A .
- FIG. 5A is a circuit schematic of an example injection-locked multiple-moduli prescaler implemented using a single-ended inverter-chain ring oscillator capable of dividing by eight ratios: 1:2, 1:3, 1:4, 1:5, 1:7, 1:11, 1:13, and 1:16.
- FIG. 5B and FIG. 5C respectively show a left and a right partial view of the example circuit of FIG. 5A in more detail.
- FIG. 5D is a table showing an example relationship between the number of stages and the division ratio of the circuit of FIG. 5A .
- FIG. 5E is a table showing an example of how to choose the stages that are to be injected into by the (e.g., quadrature) injections for all eight division ratios described with respect to the example circuit in FIG. 5A .
- FIG. 6A is a circuit schematic of an example injection-locked multiple-moduli prescaler implemented using a differential ring oscillator capable of dividing by four ratios: 1:2, 1:3, 1:4, and 1:5.
- FIG. 6B is a table showing an example relationship between the number of stages and the division ratio of the circuit of FIG. 6A .
- FIG. 6C is a table showing an example of how to choose the stages that are to be injected into by the (e.g., quadrature) injections for all four division ratios described with respect to the example circuit in FIG. 6A .
- FIG. 7 is a circuit schematic of an example implementation of a delay stage that can be used to implement the ring oscillator of FIG. 6A .
- FIG. 8 shows circuit schematics of two example implementations of the differential injection current source that can be used to inject into the differential ring oscillator of FIG. 6A .
- FIG. 9A is a circuit schematic of two example stages of a ring oscillator and their corresponding injections.
- FIG. 9B shows the time-domain waveforms of the oscillation voltages and the ideal injection currents for the example stages shown in FIG. 9A .
- Frequency dividers with multiple, dynamically programmable division ratios find applications in various areas of electronics.
- One application is the implementation of fractional-N phase-locked loops for high-frequency synthesis. More specifically, there are many types of frequency dividers.
- An injection-locked frequency divider may operate as a tuned oscillator that is injection locked to an input clock frequency divided by a positive integer N, known as the division ratio or modulus.
- An injection-locked frequency divider may operate over a range of input clock frequencies, known as the frequency divider's lock range.
- design footprint, power consumption, and the number of division ratios are an area where compromises are traditionally made in frequency synthesizer designs, and where improvements are desirable. It is recognized in the present disclosure as advantageous to have a prescaler design that can exhibit both low power consumption and the ability to divide by multiple moduli, and in the meantime with a design footprint that is as small as possible.
- conventional injection-locked frequency dividers typically face a number of issues when used as a prescaler. For one, they typically only have a limited range of operable frequencies, and it may be technically difficult to enhance their lock range. Further, conventional non-digital, oscillator-based prescalers are mostly designed to have only a single division ratio. Moreover, division by an even ratio is often accomplished through injection into the tail of an inductor-capacitor (LC) oscillator, the inductor in which requires a large amount of chip area, which can increase the fabrication cost of the circuit and overall design difficulty, especially when the circuit needs to be integrated with other circuits.
- LC inductor-capacitor
- the disclosed prescaler circuit can enable a circuit design (e.g., a PLL) that has dynamically changeable division ratios, reduced power consumption (e.g., as compared to conventional digital designs, especially when the division ratio is low, such as 2, 3, or 4), and a small footprint (e.g., as compared to other types of design, such as those that have inductor-capacitor (LC) oscillators).
- a circuit design e.g., a PLL
- reduced power consumption e.g., as compared to conventional digital designs, especially when the division ratio is low, such as 2, 3, or 4
- LC inductor-capacitor
- ring oscillators can be small and compact as compared to other oscillators (e.g., LC oscillators), can operate at high speeds with reasonable power consumption, and can be amenable to lock-range enhancement through a variety of techniques discussed here. Further, as discussed in more detail below, the disclosed techniques can be similarly applicable to create a circuit with any arbitrary number of integer-valued moduli; these techniques are not limited to those specific examples that are disclosed here.
- Coupled can be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” can be used to indicate that two or more elements are in direct contact with each other. Unless otherwise made apparent in the context, the term “coupled” can be used to indicate that two or more elements are in either direct or indirect (with other intervening elements between them) contact with each other, or that the two or more elements co-operate or interact with each other (e.g., as in a cause and effect relationship), or both.
- FIG. 1 is a block diagram of an example phase-locked loop-based frequency synthesizer 10 .
- the synthesizer 10 includes an injection-locked multiple-moduli prescaler 100 as the first frequency divider in the feedback path.
- the synthesizer 10 further includes a voltage-controlled oscillator (VCO) 110 , a digital divider 120 , a crystal reference 130 , and a phase/frequency detector 140 .
- VCO voltage-controlled oscillator
- the low-frequency (e.g., in the range of kilohertz to hundreds of megahertz) crystal reference oscillator 130 which can oscillate at a reference frequency f ref , is used to synthesize an output frequency f out .
- the output frequency f out can be thousands to millions of times larger than the reference frequency f ref .
- the loop operates by correcting phase errors between (1) the reference signal generated by the crystal reference 130 and (2) a frequency-divided version of the output signal generated by the voltage-controlled oscillator (VCO) 110 .
- the loop's forward path therefore uses the phase/frequency detector 140 to detect this phase error.
- the output of the phase/frequency detector 140 is received by a charge pump/loop filter block 150 , which is operable to produce a control voltage V CTRL .
- the control voltage V CTRL is in turn used to control and tune the VCO 110 in the loop.
- the embodiments described in the present disclosure have a quadrature VCO (i.e., one that is capable of generating four oscillation signals at quadrature phases).
- Quadrature VCOs are particularly useful in radio-frequency communication systems due to the usefulness of quadrature signals in such systems (e.g., because of their use in I/Q modulation and image rejection).
- the presently disclosed techniques are similarly applicable for those VCOs which generate less phases or more phases, and with any (including non-uniform) distribution of phases.
- the frequency synthesizer's loop has a feedback path that divides the output frequency f out down to the reference frequency f ref .
- This frequency division can be performed by the digital divider 120 .
- conventional digital dividers e.g., the digital divider 120
- the frequency synthesizer 10 includes another frequency divider in addition to the digital divider 120 .
- This additional frequency divider depicted in FIG. 1 as the prescaler 100 , can be implemented using an injection-locked oscillator.
- the prescaler 100 can be positioned between the output frequency f out and the digital divider 120 .
- this additional frequency divider (e.g., the prescaler 100 ) is to “prescale” the output frequency f out down to a frequency that can be feasibly handled (e.g., in terms of power consumption and/or thermal budget of the circuit) by the digital divider 120 . That is to again say, while the overall division ratio between f out and f ref needs to be in the thousands to millions, it is the “first few” divisions—the initial reduction of f out to f out /2,f out /3, or f out /4, for example—that experience the sharpest tradeoff between speed and power.
- the frequency divider 100 thus functions as a “prescaler” that handles these first few division ratios.
- a conventional prescaler may only feature a fixed division ratio N, where N is a positive integer.
- N is a positive integer.
- the tuning resolution of the frequency synthesizer is reduced by a factor of N.
- changing the division ratio of the digital divider 120 from M to (M+1), where M is a positive integer necessarily changes the output frequency f out from N ⁇ M ⁇ f ref to N ⁇ (M+1) ⁇ f ref .
- the two frequencies differ from each other by N ⁇ f ref instead of the reference frequency f ref (i.e., the original tuning resolution in the absence of the conventional, fixed division ratio prescaler).
- one conventional attempt to mitigate this problem is by having a prescaler design that features multiple division ratios (or moduli) which, in some designs, may be dynamically switched between during the operation of the frequency synthesizer.
- a typical dual-modulus prescaler which may feature two division ratios: N and (N+1).
- the digital divider 120 has a division ratio M If the dual-modulus prescaler spends (P/M) of the time at N and the remaining (1 ⁇ P/M) of the time at (N+1), where P is an integer between 0 and M, then the output frequency f out becomes (NM+P) ⁇ f ref on average.
- This technique is typically known as fractional-N frequency synthesis.
- the output frequency f out changes by ⁇ f ref , indicating a tuning resolution equal to the reference frequency f ref .
- ⁇ f ref a tuning resolution equal to the reference frequency f ref .
- the prescaler it is therefore desirable for the prescaler to exhibit both low power consumption and the ability to divide by multiple moduli, and yet as discussed above, conventional injection-locked frequency dividers, when used as a prescaler, often suffer from issues like limited operating ranges, inability to enhance the lock range, lack of availability in oscillator-based prescaler designs, and so on.
- the present disclosure includes techniques and a number of example designs that realize a multiple-moduli prescaler from an injection-locked ring-oscillator-based divider.
- An oscillator is a circuit that is capable of generating a periodic output signal on its own; the frequency of this signal is known as the oscillator's free-running frequency.
- the oscillator when an external periodic signal is injected into the oscillator (whose frequency is called the injection frequency), the oscillator is also capable of synchronizing to this external input signal (or to a frequency-divided version thereof), provided that the injection frequency is sufficiently close to (e.g., depending on the injection strength and type of oscillator, within a range as narrow as 10% or as wide as 25% on either side of) the oscillator's free-running frequency (or an integer multiple thereof).
- the range of frequencies over which this described synchronization can occur is known as the lock range.
- the injection frequency is an integer multiple of the frequency of the injection-locked oscillator's output
- the oscillator functions as an injection-locked frequency divider.
- a ring oscillator includes a plurality of delay stages connected in series to form a closed ring.
- Injection into a ring oscillator can be achieved by injecting into the input node of a particular stage of the ring oscillator.
- injecting “into a stage” is synonymous with injecting at the input node of that stage.
- the oscillation voltage “associated with” a stage means the oscillation voltage at the input node of that stage.
- an input available for injection into the prescaler includes multiple input signal components at different phases.
- the phase-locked loop's VCO 110 is a quadrature VCO that includes four input signal components, 90° phase apart from one another, available for injection into the prescaler 100 .
- the embodiments disclosed here are described as having quadrature input signal components, the techniques disclosed in the present disclosure is similarly applicable to any suitable number of input signal components with any suitable collection of phases.
- two example steps can be taken: (a) tune the ring oscillator's free-running frequency; and (b) switch the stages that receive the input signal components.
- the free-running frequency of the ring oscillator can be tuned such that two ranges including, (1) the range of input frequencies for which division by N 1 is possible and (2) the range of input frequencies for which division by N 2 is possible, have range overlap.
- the oscillator is so tuned that the two ranges have as much the overlap as possible. Put another way, in these embodiments, the overlap between the lock ranges at different division ratios (with respect to the input frequency, not to the oscillator's output frequency) is maximized.
- the single-ended inverter-chain ring oscillator includes an odd number of stages.
- the phase differences between different input signal components should, at least ideally, be equal to N times the phase differences between the oscillation voltages associated with the respective stages that those input signal components are injected into.
- the oscillation voltage associated with a stage is defined as the oscillation voltage at the input node of that stage. Therefore, an equivalent formulation of this condition is that the phase differences between different input signal components should, at least ideally, be N times the phase differences between the oscillation voltages at the respective nodes that those input signal components are injected into. Consequently, generally speaking, when N changes, so does the stage that should receive a particular input signal component.
- FIG. 9A shows a circuit schematic 900 of two example stages of a ring oscillator and their corresponding injections.
- the two stages are labeled “Stage m” ( 910 ) and “Stage n” ( 912 ), and they are injected into by injection currents 920 and 922 , respectively.
- FIG. 9B shows a first chart 902 that illustrates the time-domain waveforms of the oscillation voltages associated with these two stages 910 and 912 .
- a second chart 904 that illustrates the time-domain waveforms of the input signal components generated by the two injection currents 920 and 922 .
- FIG. 9B also shows the ideal phase difference between the input signal components injected into two stages of the ring oscillator of FIG. 9A .
- time difference ⁇ t mn ( 950 ) can be written as ⁇ mn / ⁇ osc ( 952 ), indicating a phase difference of ⁇ mn between the two stages' oscillation voltages, ⁇ osc,m (t) ( 930 ) and ⁇ osc,n (t) ( 932 ).
- the ideal phase difference which is implemented in a variety of embodiments disclosed here, follows from this relationship:
- phase difference between adjacent stages is given by ( ⁇ /K) radians. Therefore, the phase difference between a reference stage (i.e., stage 0) and another stage that is k stages away from the reference stage (i.e., stage k) is given by k ⁇ ( ⁇ /K) radians.
- stage 0 the phase difference between a reference stage
- stage k the phase difference between a reference stage and another stage that is k stages away from the reference stage (i.e., stage k) is given by k ⁇ ( ⁇ /K) radians.
- the ideal phase for an input signal component injected into stage k is N ⁇ k ⁇ ( ⁇ /K) radians for a division ratio of N. If this phase exceeds 2 ⁇ radians, the remainder after its division by 2 ⁇ (i.e., [N ⁇ k ⁇ ( ⁇ /K)]mod 2 ⁇ radians) can be taken, because phase is invariant to shifts by 2 ⁇ radians.
- phase difference between adjacent stages is given by ⁇ /K radians. Therefore, the phase difference between a reference stage (i.e., stage 0) and another stage that is k stages away from the reference stage (i.e., stage k) is given by ⁇ k ⁇ /K radians. Likewise, this indicates that the ideal phase for an input signal component injected into stage k is ⁇ N ⁇ k ⁇ /K radians for a division ratio of N. Again, this phase is mathematically equivalent to ( ⁇ N ⁇ k ⁇ /K) mod 2 ⁇ radians. Note that these two types of ring oscillators are described here only for illustrative purposes; the disclosed techniques can be applicable to another suitable ring oscillator type or topology in a similar manner.
- the closest matches between the ideal phases and the available phases of the input signal components can be determined. Note that, according to the present embodiments, one of the input signal components (a “reference” input signal component) should always be injected into one of the stages (a “reference” stage) during the circuit's normal operation, and both the reference input signal component and the reference stage can be chosen arbitrarily.
- An example process for handling the remaining input signal components (and the remaining stages) is provided as follows. Because there may be more stages than there are input signal components, if such is the case, the example process can include determining, for each input signal component, the stage whose ideal phase most closely matches the input signal component's phase, and in such case, the remaining stages which are not matched to an input signal component are left alone and not injected into the oscillator. If, on the other hand, there are more input signal components than the number of stages, then the example procedure can include determining, for each stage, the input signal component whose phase most closely matches the stage's ideal phase. Then, the remaining input signal components that are not matched to a stage are left alone and not used to inject into the oscillator.
- fractional ratios in between discrete ratios can further be realized by dithering the integer division ratios that can be achieved (e.g., using pulse-width modulation or delta-sigma modulation techniques).
- the fractional-N frequency synthesizers disclosed here are able to synthesize frequencies that are in between integer multiples of the PLL's reference frequency. Note that delta-sigma modulation, as compared to pulse-width modulation, generally tends to introduce less spurs into the output spectrum.
- the prescaler/divider disclosed here can be particularly useful in generating fractional ratios, at least because of the dynamic programmability of the division ratio (as discussed in further detail below). Accordingly, at least some embodiments of the present disclosure can be configured (e.g., through performing delta-sigma modulation in the division ratio control of the disclosed prescaler) to select an effective frequency division ratio by using a combination of the available frequency division ratios implemented in the frequency divider.
- FIG. 2A shows one embodiment, implemented using a single-ended inverter-chain ring oscillator 200 , that is capable of dividing by two division ratios: 1:2 and 1:3.
- Table 202 shows the example relationship between the number of stages and the division ratio.
- a switch S N closes (i.e., is electrically conducting) if and only if the chosen division ratio is N.
- switch S 2 closes if and only if the chosen division ratio is 2
- switch S 3 closes if and only if the chosen division ratio is 3.
- switches 220 and 222 can control whether the oscillator has five or seven stages, respectively, which in turn and in accordance with entries 240 and 242 , control the division ratio of the ring oscillator 200 .
- Also shown in FIG. 2A are four quadrature injection inputs, injections IP, IN, QP, and QN. Like discussed before, these inputs represent the input frequency but with a 90 degree phase shift from each other.
- tables 204 and 206 show, for the example circuit in FIG. 2A , how to choose which quadrature injections are to be injected into the inputs of which stages for the 1:2 and 1:3 division ratios, respectively (in accordance with the example procedure detailed above).
- Injection IP ( 210 ) is chosen as the reference and always gets injected into stage 0, as reflected by entries 250 and 260 .
- entries 252 , 254 , and 256 indicate respectively that injection QN ( 216 ) should pass through switch 232 and be injected into stage 1; injection IN ( 214 ) should be injected into stage 2, and injection QP ( 212 ) should pass through switch 230 and be injected into stage 4.
- entries 262 , 264 , and 266 indicate respectively that injection QP ( 212 ) should pass through switch 234 and be injected into stage 1, injection IN ( 214 ) should again be injected into stage 2, and injection QN ( 216 ) should pass through switch 236 and be injected into stage 6.
- entries 258 and 268 indicate that the second-to-last stage can also be chosen for the injection IN ( 214 ), because the ideal injected phase is as close to ⁇ as it is for stage 2 for both ratios. However, note that this choice necessitates switching between injecting into stage 3 when the division ratio is 1:2 and injecting into stage 5 when the division ratio is 1:3. It may be therefore, depending on the actual application, more convenient to choose to inject IN ( 214 ) into stage 2 for both ratios (entries 254 and 264 ). Another consideration should be taken, that is, more switches generally means more loading of the oscillator and the injection circuitry, which can degrade the circuit's performance. Lastly, once all of the available injections have been assigned stages to inject into, the ideal injected phases for the remaining stages become no longer relevant, as shown by the “Don't Care” value for entry 269 .
- FIG. 3 shows how a single inverter (or delay stage) 300 of the ring oscillator 200 of FIG. 2A may be implemented in some embodiments.
- the P-type field effect transistor (PFET) is made larger than the N-type FET (NFET) (e.g., with twice the total gate width) because electron holes have a lower mobility than electrons.
- PFET P-type field effect transistor
- NFET N-type FET
- a CMOS inverter 302 can feature an NFET with a larger gate area than the PFET (i.e., W N >W P ), so as to make the rise and fall times of the oscillation waveform uneven (by exacerbating the inverter's inherent asymmetry due to the electron's higher mobility).
- W N >W P PFET
- This can be done to widen the lock range when dividing by an even ratio, as division by an even ratio requires the presence of even harmonics in the oscillation waveform, and a perfectly symmetric oscillation waveform with equal rise and fall times contains only odd harmonics.
- This technique can preserve the ring oscillator's ability to divide by an odd ratio.
- FIG. 4 shows two example implementations of an injection current source 400 from an injection voltage: (1) in one embodiment, as an N-type MOS (NMOS) transistor current source 402 (whose amplitude is controlled by a direct-current (DC) current source I bias ), or (2) in another embodiment, as circuit 404 , with the buffered injection voltage driving a series resistor R inj (the Norton equivalent of which is a current source in parallel with said resistor).
- NMOS N-type MOS
- R inj the Norton equivalent of which is a current source in parallel with said resistor
- FIG. 5A shows another embodiment, implemented using a single-ended inverter-chain ring oscillator 500 , that is capable of dividing by eight ratios.
- the example injection-locked multiple-moduli prescaler implemented using a single-ended inverter-chain ring oscillator is capable of dividing by ratios including: 1:2, 1:3, 1:4, 1:5, 1:7, 1:11, 1:13, and 1:16.
- FIGS. 5B and 5C are each a partial view that together form a single, complete figure.
- the circuit in FIGS. 5B and 5C formed by connecting 502 and 503 , is therefore an example implementation of the circuit in FIG. 5A .
- the larger inverters in FIG. 5A represent multiple smaller inverters connected in series (as indicated by the plurality of stage numbers above them) and are shown as a single block for convenience; the details of these inverters can be seen more clearly in FIGS. 5B and 5C , with simultaneous reference to FIG. 5A .
- a switch S N is to close if and only if the chosen division ratio is N.
- the switches S N odd and S N even are to close if and only if the chosen division ratio is odd or even, respectively.
- FIG. 5D is a table 504 that shows an example relationship between the number of stages and the division ratio of the circuit of FIG. 5A .
- switches 520 - 527 can control whether the oscillator has five, seven, nine, eleven, fifteen, twenty-three, twenty-seven, or thirty-three stages, respectively. Each number of stages has a corresponding division ratio.
- FIG. 5E is a table 506 that shows an example of how to choose which quadrature injections are to be injected into the inputs of which stages, described with respect to the example circuit in FIG. 5A .
- Table 506 is applicable for all of the division ratios shown in table 504 (and, more generally, for this type of oscillator when the number of stages K is one more than twice the division ratio N).
- injection IP ( 510 ) is chosen as the reference and always gets injected into stage 0, as reflected by entry 550 .
- Entry 554 indicates that, regardless of the division ratio, injection IN ( 514 ) should be injected into stage 2.
- entry 552 indicates that injection QP ( 512 ) should pass through switch 538 and be injected into stage 1.
- entry 556 indicates that injection QN ( 516 ) should be injected into the very last stage (K ⁇ 1), thereby passing through switch 531 for a 1:3 division ratio, switch 533 for a 1:5 division ratio, switch 534 for a 1:7 division ratio, switch 535 for a 1:11 division ratio, or switch 536 for a 1:13 division ratio.
- entry 552 indicates that injection QN ( 516 ) should pass through switch 539 and be injected into stage 1.
- entry 556 indicates that injection QP ( 512 ) should be injected into the very last stage (K ⁇ 1), thereby passing through switch 530 for a 1:2 division ratio, switch 532 for a 1:4 division ratio, or switch 537 for a 1:16 division ratio.
- FIG. 6A shows yet another embodiment, implemented using a differential ring oscillator 600 , that is capable of dividing by four ratios. More specifically, FIG. 6A is an example injection-locked multiple-moduli prescaler implemented using a differential ring oscillator capable of dividing by ratios including: 1:2, 1:3, 1:4, and 1:5. Similar to the connotation used above, a switch S N is to close if and only if the chosen division ratio is N.
- FIG. 6B is a table 602 that provides an example relationship between the number of stages and the division ratio, for the ring oscillator 600 in the circuit of FIG. 6A .
- switches 620 and 621 can cause the oscillator 600 to have four stages.
- switches 622 and 623 can cause the oscillator 600 to have six stages.
- switches 624 and 625 can cause the oscillator 600 to have eight stages.
- switches 626 and 627 can cause the oscillator 600 to have ten stages.
- Table 602 also shows the division ratio that corresponds to each of said number of stages.
- FIG. 6C is a table 604 that shows an example of how to choose which quadrature injections are to be injected into the inputs of which stages for the example circuit in FIG. 6A .
- Table 604 is applicable for all of the division ratios shown in table 602 (and, more generally, for this type of oscillator when the number of stages K is double the division ratio N).
- Injection IP ( 610 ) is chosen as the reference and always gets injected into stage 0, as reflected by entry 640 .
- Entry 642 indicates that, regardless of the division ratio, injection QN ( 612 ) should be injected into stage 1.
- Entry 644 indicates that, regardless of the division ratio, injection IN ( 614 ) should be injected into stage 2.
- Entry 646 indicates that, regardless of the division ratio, injection QP ( 616 ) should be injected into stage 3. Rows for the rest of the stages are not shown because, similar to the examples of FIGS. 2 and 5 , those rows are not relevant because all four available injections have already been assigned stages to inject into. Note that, in this particular example, no switches are needed to change the stage that a particular injection gets injected into when the division ratio changes.
- FIG. 7 shows how a single delay stage (e.g., delay stage 700 ) of the ring oscillator 600 of FIG. 6A may be implemented in one embodiment: as a differential amplifier 702 with a differential capacitive load C. Note that the time constant between R and C can be used to control the delay and thereby tune the free-running frequency of the oscillator.
- FIG. 8 shows two example implementations of a differential injection current source 800 from a differential injection voltage: (1) in one embodiment, as an NMOS differential pair 802 (whose amplitude is controlled by a DC tail current source I bias ), or (2) in another embodiment, as circuit 804 , with the buffered injection voltages driving series resistors (the Norton equivalent of each is a current source in parallel with the resistor).
- NMOS differential pair 802 whose amplitude is controlled by a DC tail current source I bias
- circuit 804 the buffered injection voltages driving series resistors
- Norton equivalent of each is a current source in parallel with the resistor
- the disclosed frequency dividers can generate lower-frequency signals from higher-frequency signals, with the latter's frequency being an integer multiple of the former's frequency (without taking into account known modulation/dithering techniques, e.g., pulse swallowing, random jittering, delta-sigma modulation).
- the frequency dividers disclosed here can dynamically change their division ratio N during the divider's operation.
- the stages' input nodes in these embodiments are not to be shorted together even though they can accept injections from input signal components of the same phase.
- the same input phase can be generated by replicating that input signal component using a buffer.
- the purpose of (a), changing the number of stages, is to maximize the overlap between the ring oscillator's lock ranges (with respect to the input frequency) at different division ratios.
- the underlying physical reasoning is that the lock range is roughly centered around the ring oscillator's free-running oscillation frequency multiplied by N, and this free-running frequency is roughly inversely proportional to the number of stages.
- the number of input signal components M is often 2, for differential inputs, or 4, for quadrature inputs.
- M can be any positive integer, and the input signal components' phases need not be distributed uniformly.
- tail injections are often utilized in the superharmonic locking of LC oscillators
- modulating the tail/bias currents of an inverter-chain ring oscillator's stages can be a less effective means of injection locking the oscillator compared with injecting into the stages' input nodes (e.g., as in one or more embodiments described above).
- existing designs often entail injecting the same signal into the tails of multiple stages, which does not account for the phase delay between stages and can therefore result in unstable and unpredictable oscillation modes.
- conventional ring-oscillator-based dual-modulus prescalers that are designed with these existing techniques do not perform as reliably and satisfactorily as the disclosed embodiments, especially for frequency synthesizer applications.
- Embodiments of the present disclosure are illustrative and not limitative. Embodiments of the present invention are not limited by the number of division ratios, the values of the division ratios, the frequency of operation, the number of input signal components, the phases of the input signal components, the type or topology of the ring oscillator, and the implementation of the injection and switching circuitry. Embodiments of the present disclosure are not limited by the type of substrate in which various electrical components of the circuit are formed. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.
- circuits disclosed herein may be described using computer-aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and VHDL; formats supporting register-level description languages like RTL; formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES; and any other suitable format or language.
- Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic, or semiconductor storage media).
Abstract
Description
Claims (24)
ϕ(k)=[kN(π−π/K)]mod 2π,
ϕ(k)=(−kNπ/K)mod 2π,
f 2(N 2 /N 1),
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