CN115692479A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, comprising: a substrate having a plurality of channel layers thereon, the channel layers extending in a first direction; the inner side wall is positioned between two ends of the adjacent channel layers, and the side surface of the inner side wall and the end surface of the channel layer share a vertical surface; a gate trench located between adjacent channel layers; the grid structure is positioned on the substrate and in the grid groove, the grid structure surrounds the plurality of channel layers along a second direction, and the first direction is vertical to the second direction; the first side wall and the second side wall are positioned on the side wall of the grid structure, and the first side wall is positioned on the second side wall; source and drain openings located at two sides of the grid structure, wherein the source and drain openings expose the inner side wall; and the source and drain doped layers are positioned in the source and drain openings. And covering the side walls of the fin part structures through the bottom pseudo gate material layer. The generation of byproducts after the source-drain opening is formed can be reduced, so that the source-drain doping layer has a good growth environment, the appearance of the source-drain doping layer is improved, and the performance of the finally formed semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.

Background

A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor, the fin type field effect transistor has stronger short channel inhibition capability and stronger working current.

As semiconductor technology further advances, the size of integrated circuit devices becomes smaller, and the fabrication process of conventional fin field effect transistors is also challenged.

Therefore, the performance of the finfet in the prior art needs to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can effectively improve the performance of the finally formed semiconductor structure.

To solve the above problems, the present invention provides a semiconductor structure, comprising: the device comprises a substrate, a plurality of first electrodes and a plurality of second electrodes, wherein the substrate is provided with a plurality of channel layers, the channel layers are stacked along the normal direction of the surface of the substrate, and the channel layers extend along a first direction; the inner side wall is positioned between two ends of the adjacent channel layers, and the side surface of the inner side wall and the end surface of the channel layer share a vertical surface; a gate trench located between adjacent ones of the channel layers; the grid structure is positioned on the substrate and in the grid groove, the grid structure surrounds the channel layers along a second direction, and the first direction is vertical to the second direction; the first side wall and the second side wall are positioned on the side wall of the grid structure, and the first side wall is positioned on the second side wall; source and drain openings positioned on two sides of the grid structure, wherein the source and drain openings expose the inner side wall, and the bottom surface of the source and drain openings is lower than the top surface of the substrate; and the source and drain doping layer is positioned in the source and drain opening.

Optionally, the material of the inner side wall is the same as that of the second side wall.

Optionally, the material of the inner side wall includes silicon nitride; the material of the second side wall comprises silicon nitride.

Optionally, the method further includes: an isolation layer on the substrate, a top surface of the isolation layer being not higher than a top surface of the channel layer on a bottom layer.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a plurality of initial channel layers and a plurality of initial sacrificial layers, the initial channel layers and the initial sacrificial layers are stacked at intervals along the normal direction of the surface of the substrate, and the initial channel layers and the initial sacrificial layers extend along a first direction respectively; forming a pseudo gate material layer on the substrate, wherein the pseudo gate material layer covers the side walls and the top surfaces of the initial channel layers and the initial sacrificial layers; performing graphical processing on the pseudo gate material layer to form a pseudo gate structure, wherein the pseudo gate structure comprises a bottom pseudo gate material layer and a top pseudo gate structure located on the bottom pseudo gate material layer, the bottom pseudo gate material layer covers the side walls of a plurality of initial channel layers and a plurality of initial sacrificial layers and exposes the top surface of the initial channel layer located on the top layer, the top pseudo gate structure covers part of the top surface of the initial channel layer located on the top layer along a second direction, and the first direction is perpendicular to the second direction; forming a first side wall on the side wall of the top pseudo gate structure; etching a plurality of initial channel layers, a plurality of initial sacrificial layers and the bottom pseudo gate material layer by taking the top pseudo gate structure and the first side wall as masks to form a source drain opening, a plurality of channel layers, a plurality of sacrificial layers and an initial bottom pseudo gate structure; etching the exposed part of the sacrificial layer on the side wall of the source drain opening, and forming an isolation groove between the adjacent channel layers; forming an inner side wall in the isolation groove; and forming a source drain doping layer in the source drain opening.

Optionally, the method for forming the dummy gate structure by performing patterning on the dummy gate material layer includes: forming a patterning layer on the pseudo gate material layer, wherein the patterning layer exposes a part of the top surface of the pseudo gate material layer; and etching the pseudo gate material layer by taking the patterning layer as a mask until the top surface of the initial channel layer positioned on the top layer is exposed, so as to form the pseudo gate structure.

Optionally, the dummy gate structure includes a dummy gate layer.

Optionally, a material of the sacrificial layer is different from a material of the channel layer, and the material of the sacrificial layer is the same as the material of the dummy gate layer.

Optionally, the material of the sacrificial layer and the material of the dummy gate layer include silicon germanium; the material of the channel layer includes silicon.

Optionally, in the process of forming the isolation groove, the method further includes: and thinning the initial bottom pseudo gate structure to form a bottom pseudo gate structure, wherein the size of the bottom pseudo gate structure parallel to the first direction and the second direction is smaller than the size of the initial bottom pseudo gate structure parallel to the first direction and the second direction.

Optionally, in the process of forming the inner sidewall, the method further includes: and forming a second side wall on the side wall of the bottom pseudo gate structure.

Optionally, the method for forming the second sidewall and the inner sidewall includes: forming a first initial inner side wall in the isolation groove, on the side wall and the bottom surface of the source drain opening, on the side walls of the bottom pseudo gate structure and the top pseudo gate structure, and on the top surface of the top pseudo gate structure; etching the first initial inner side wall back until the bottom surface of the source drain opening and the top surface of the top pseudo gate structure are exposed to form a second initial inner side wall; and etching back the second initial inner side wall until the top pseudo gate structure, the bottom pseudo gate structure and the side wall of the channel layer are exposed, so as to form the second side wall and the inner side wall.

Optionally, the material of the inner sidewall includes silicon nitride; the material of the second side wall comprises silicon nitride.

Optionally, after the source-drain doping layer is formed, the method further includes: forming a dielectric layer on the substrate, wherein the dielectric layer covers the side walls of the top pseudo gate structure and the bottom pseudo gate structure; removing the top pseudo gate structure and the bottom pseudo gate structure, and forming a gate opening in the dielectric layer; removing the sacrificial layer, and forming a gate groove between the adjacent channel layers; and forming a gate structure in the gate opening and the gate groove, wherein the gate structure surrounds the channel layer.

Optionally, before forming the gate structure, the method further includes: and forming an isolation layer on the substrate, wherein the top surface of the isolation layer is not higher than the top surface of the channel layer at the bottom layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the forming method of the technical scheme, the bottom pseudo gate material layer covers the side wall of the fin portion structure, so that the first side wall is prevented from being formed on the side wall of the fin portion structure in the process of forming the first side wall on the side wall of the top pseudo gate structure. And then the generation of byproducts after the source and drain openings are formed is reduced, so that the source and drain doping layer has a good growth environment, the appearance of the source and drain doping layer is improved, and the performance of the finally formed semiconductor structure is improved.

On the other hand, the first side walls are not formed on the side walls of the plurality of initial channel layers and the plurality of initial sacrificial layers, so that the first side walls do not need to be etched back, the height of the top pseudo gate structure is prevented from being made to be very high, the process difficulty can be effectively reduced, and the appearance of the source and drain openings can be improved.

Further, the material of the sacrificial layer is the same as that of the dummy gate layer; in the process of forming the isolation groove, the method further comprises: and thinning the initial bottom pseudo gate layer. The steps of the manufacturing process can be effectively reduced, and the production efficiency is improved.

Further, the in-process of forming the inner side wall in the isolation groove further includes: and forming the second side wall. The manufacturing steps can be effectively reduced, and the production efficiency is improved.

Drawings

FIGS. 1 and 2 are schematic structural views of steps in a semiconductor structure formation process;

FIGS. 3-5 are schematic structural views of steps in another semiconductor structure formation process;

fig. 6 to 21 are schematic structural diagrams of steps of a semiconductor structure forming method according to an embodiment of the present invention.

Detailed Description

As mentioned in the background, the performance of the finfet in the prior art is desired to be improved. The following detailed description will be made in conjunction with the accompanying drawings.

Fig. 1 and 2 are schematic structural diagrams of steps in a semiconductor structure formation process.

Referring to fig. 1, a substrate 100 is provided, and a fin structure 101 is formed on the substrate 100; forming a dummy gate structure 102 on the substrate 100, wherein the dummy gate structure 102 spans over the fin structure 101, and the dummy gate structure 102 covers part of the sidewall and the top surface of the fin structure 101; forming a side wall material layer on the side wall and the top surface of the dummy gate structure 102, the side wall and the top surface of the fin structure 101 exposed; and etching back the side wall material layer until the top surfaces of the gate structure 102 and the fin structure 101 are exposed, thereby forming a side wall 103.

Referring to fig. 2, after the sidewalls 103 are formed, the fin structure 101 is etched by using the dummy gate structure 102 and the sidewalls 103 as masks, and source-drain openings 104 are formed in the fin structure 101.

In this embodiment, the sidewall material layer is also formed on the exposed sidewall of the fin structure 101. Therefore, after the back etching of the sidewall material layer, the sidewall 103 also remains on the sidewall of the fin structure 101. After the source/drain opening 104 is formed, the sidewall 103 on the sidewall of the fin structure 101 is not supported by the fin structure 101, and is easily collapsed to become a byproduct, which affects the growth of a source/drain doping layer formed subsequently, thereby deteriorating the morphology of the source/drain doping layer and reducing the performance of a finally formed semiconductor structure.

In order to solve the above problems, a method for forming a semiconductor structure is also proposed in the prior art. The following detailed description will be made in conjunction with the accompanying drawings.

Fig. 3-5 are schematic structural diagrams of steps in another semiconductor structure formation process.

Referring to fig. 3, a substrate 200 is provided, wherein the substrate 200 has a fin structure 201 thereon; forming an initial pseudo gate structure 202 on the substrate 200, wherein the initial pseudo gate structure 202 spans over the fin structure 201, and the initial pseudo gate structure 202 covers part of the sidewalls and the top surface of the fin structure 201; forming a side wall material layer on the side wall and the top surface of the initial pseudo gate structure 202, the side wall and the top surface of the fin structure 201 exposed; and etching back the side wall material layer until the top surfaces of the initial gate structure 202 and the fin structure 201 are exposed, thereby forming an initial side wall 203.

Referring to fig. 4, after the initial spacers 203 are formed, the fin structure 201 is etched by using the initial dummy gate structure 202 and the initial spacers 203 as masks, and source-drain openings 204 are formed in the fin structure 201.

Referring to fig. 5, after the source/drain openings 204 are formed, the initial sidewall spacers 203 are etched back until the top surface of the substrate 200 is exposed, so as to form sidewall spacers 206.

In this embodiment, although the initial sidewall remaining on the sidewall of the fin structure 201 can be removed by etching back the initial sidewall 203, the initial dummy gate structure 202 is also consumed by etching in the process of etching back the initial sidewall 203, so as to finally form the dummy gate structure 205. Therefore, in order to ensure that the final dummy gate structure 205 has a preset height, the initial dummy gate structure 202 needs to be made very high along the height of the surface normal of the substrate 200.

However, when the height of the initial dummy gate structure 202 is required to be too high, the process difficulty in the process of manufacturing the initial dummy gate structure 202 may be increased, so that the verticality of the sidewall of the initial dummy gate structure 202 is poor, and the topography of the source-drain opening 204 formed by using the initial dummy gate structure 202 as a mask is further affected. When the topography of the source/drain opening 204 is poor, a great difficulty may be caused to a subsequent manufacturing process.

On the basis, the invention provides a semiconductor structure and a forming method thereof, wherein the bottom pseudo gate material layer covers the side walls of a plurality of initial channel layers and a plurality of initial sacrificial layers, so that the first side walls are prevented from being formed on the side walls of the initial channel layers and the initial sacrificial layers in the process of forming the first side walls on the side walls of the top pseudo gate structure. And then the generation of byproducts after the source and drain openings are formed is reduced, so that the source and drain doping layer has a good growth environment, the appearance of the source and drain doping layer is improved, and the performance of the finally formed semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 6 to 21 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 6, a substrate 300 is provided, where the substrate 300 has a plurality of initial channel layers 301 and a plurality of initial sacrificial layers 302, the plurality of initial channel layers 301 and the plurality of initial sacrificial layers 302 are stacked at intervals along a normal direction of a surface of the substrate 300, and the plurality of initial channel layers 301 and the plurality of initial sacrificial layers 302 respectively extend along a first direction X.

In this embodiment, the material of the substrate 300 is silicon.

In this embodiment, the method of the substrate 300 and the plurality of initial channel layers 301 and the plurality of initial sacrificial layers 302 includes: providing an initial substrate (not shown); forming a plurality of channel material films overlapped along the normal direction of the surface of the initial substrate and sacrificial material films positioned in two adjacent layers of channel material films on the initial substrate; forming a patterned layer (not shown) on the channel material film at the top layer; and etching the initial substrate, the plurality of channel material films and the plurality of sacrificial material films by taking the patterning layer as a mask to form the substrate 300, the plurality of initial channel layers 301 and the plurality of initial sacrificial layers 302.

The material of the initial sacrificial layer 302 is different from the material of the initial channel layer 301. The purpose is to remove the formed sacrificial layer when a gate structure is formed subsequently, so that the damage to the channel layer in the process of removing the sacrificial layer is reduced by adopting the initial sacrificial layer 302 and the initial channel layer 301 which are made of different materials and having a larger etching selection ratio.

In this embodiment, the material of the initial sacrificial layer 302 is silicon germanium; the material of the initial channel layer 301 is silicon. In other embodiments, the material of the initial sacrificial layer may also be germanium; the initial channel layer is made of silicon germanium.

Referring to fig. 7, an isolation layer 303 is formed on the substrate 300.

In this embodiment, the method for forming the isolation layer 303 includes: forming a layer of isolation material (not shown) on the substrate 300, the layer of isolation material covering sidewalls of the number of initial channel layers and the number of initial sacrificial layers; and etching back the isolation material layer to form the isolation layer 303, wherein the top surface of the isolation layer 303 is not higher than the top surface of the initial channel layer 301 at the bottom layer.

The material of the isolation layer 303 includes silicon oxide or silicon nitride. In this embodiment, the isolation layer 203 is made of silicon nitride.

Referring to fig. 8, after forming the isolation layer 303, a dummy gate material layer 304 is formed on the substrate 300, the dummy gate material layer 304 covering sidewalls and top surfaces of the initial channel layers 301 and the initial sacrificial layers 302.

In this embodiment, the method for forming the dummy gate material layer 304 includes: forming a dummy gate material film (not shown) on the substrate; the dummy gate material film is planarized to form the dummy gate material layer 304.

In this embodiment, the formation process of the dummy gate material film employs a furnace deposition process.

In this embodiment, the planarization process employs a chemical mechanical polishing process.

Referring to fig. 9 and 10, fig. 9 isbase:Sub>A perspective view ofbase:Sub>A semiconductor structure, fig. 10 isbase:Sub>A schematic cross-sectional view taken along linebase:Sub>A-base:Sub>A in fig. 9,base:Sub>A dummy gate structure is formed by patterning the dummy gate material 304, the dummy gate structure includesbase:Sub>A bottom dummy gate material layer 305 andbase:Sub>A top dummy gate structure 306 located on the bottom dummy gate material layer 305, the bottom dummy gate material layer 305 covers sidewalls of the initial channel layers 301 and the initial sacrificial layers 302 and exposesbase:Sub>A top surface of the initial channel layer 301 located onbase:Sub>A top layer, the top dummy gate structure 306 coversbase:Sub>A portion of the top surface of the initial channel layer 301 located on the top layer alongbase:Sub>A second direction Y, and the first direction X is perpendicular to the second direction Y.

In this embodiment, the bottom dummy gate material layer 305 covers the sidewalls of the plurality of initial channel layers 301 and the plurality of initial sacrificial layers 302, so that the first sidewalls are prevented from being formed on the sidewalls of the plurality of initial channel layers 301 and the plurality of initial sacrificial layers 302 in a subsequent process of forming the first sidewalls on the sidewalls of the top dummy gate structure 306. And then the generation of byproducts after the source and drain openings are formed subsequently is reduced, so that the source and drain doping layer formed subsequently has a good growth environment, the appearance of the source and drain doping layer is improved, and the performance of the finally formed semiconductor structure is improved.

On the other hand, because the first side walls are not formed on the side walls of the plurality of initial channel layers 301 and the plurality of initial sacrificial layers 302, the first side walls do not need to be etched back, so that the height of the top dummy gate structure 304 is prevented from being made high, the process difficulty can be effectively reduced, and meanwhile, the appearance of a subsequently formed source drain opening can be improved.

In this embodiment, the method for forming the dummy gate structure by performing patterning on the dummy gate material layer 304 includes: forming a patterned layer (not shown) on the dummy gate material layer 304, the patterned layer exposing a portion of a top surface of the dummy gate material layer 304; and etching the dummy gate material layer 304 by using the patterning layer as a mask until the top surface of the initial channel layer 301 on the top layer is exposed, thereby forming the dummy gate structure.

In this embodiment, the gate structure includes a dummy gate layer, and the material of the dummy gate layer is the same as the material of the initial sacrificial layer 302.

Referring to fig. 11, the views of fig. 11 and fig. 10 are in the same direction, and a first sidewall 307 is formed on the sidewall of the top dummy gate structure 306.

In this embodiment, the method for forming the first sidewall 307 includes: forming a first sidewall material layer (not shown) on the top surface of the bottom dummy gate material layer 305 and the top surface of the top dummy gate structure 306, and the sidewall of the top dummy gate structure 306; the first sidewall material layer is etched back until the top dummy gate structure 306 and the top surface of the bottom dummy gate material layer 305 are exposed, so as to form the first sidewall 307.

In this embodiment, the first sidewall material layer is formed by an atomic layer deposition process.

In this embodiment, the first sidewall 307 is made of silicon nitride.

Referring to fig. 12 to 14, fig. 12 is a top view of a semiconductor structure, fig. 13 is a schematic cross-sectional view taken along line B-B in fig. 12, fig. 14 is a schematic cross-sectional view taken along line C-C in fig. 12, and a plurality of initial channel layers 301, a plurality of initial sacrificial layers 302, and a plurality of bottom dummy gate material layers 305 are etched by using the top dummy gate structure 306 and the first sidewall 307 as masks to form a source-drain opening 308, a plurality of channel layers 317, a plurality of sacrificial layers 318, and an initial bottom dummy gate structure 309.

In this embodiment, the source/drain opening 308 serves to provide a space for a source/drain doped layer to be formed later.

Referring to fig. 15 and 16, the directions of the views in fig. 15 and 13 are the same, and the directions of the views in fig. 16 and 14 are the same, after the source-drain openings 308 are formed, a portion of the sacrificial layer 318 exposed on the sidewalls of the source-drain openings 308 is etched, and an isolation groove 310 is formed between the adjacent channel layers 317.

In this embodiment, the isolation groove 310 is used to provide space for the inner sidewall to be formed later. The inner side wall can ensure the electrical isolation between the subsequently formed gate structure and the source-drain doped layer.

In this embodiment, in the process of forming the isolation groove 310, the method further includes: thinning the initial bottom pseudo gate structure 309 to form a bottom pseudo gate structure 311, wherein the size of the bottom pseudo gate structure 311 parallel to the first direction X and the second direction Y is smaller than the size of the initial bottom pseudo gate structure 309 parallel to the first direction X and the second direction Y. Since the material of the initial sacrificial layer 302 is the same as that of the gate layer, the sacrificial layer 318 formed by the initial sacrificial layer 302 and the gate layer are also the same, so that the initial bottom dummy gate structure 309 can be thinned by using the same etching process in the process of etching the sacrificial layer 318 to form the isolation groove 310, thereby effectively reducing the process steps and improving the production efficiency.

In this embodiment, the purpose of performing the thinning process on the initial bottom dummy gate structure 309 is to form a second sidewall on the sidewall of the bottom dummy gate structure 311 in the following step to provide a space.

Referring to fig. 17 and 18, after the isolation groove 310 is formed, an inner sidewall 312 is formed in the isolation groove 310.

In this embodiment, in the process of forming the inner sidewall 312, the method further includes: a second sidewall 313 is formed on the sidewall of the bottom dummy gate structure 311. The manufacturing steps can be effectively reduced, and the production efficiency is improved.

In this embodiment, the method for forming the second side wall 313 and the inner side wall 312 includes: forming a first initial inner sidewall (not shown) in the isolation groove 310, the sidewalls and the bottom surface of the source-drain opening 308, the sidewalls of the bottom dummy gate structure 311 and the top dummy gate structure 306, and the top surface of the top dummy gate structure 306; etching back the first initial inner side wall until the bottom surface of the source-drain opening 308 and the top surface of the top dummy gate structure 306 are exposed, so as to form a second initial inner side wall (not shown); and etching back the second initial inner side wall until the side walls of the top pseudo gate structure 306, the bottom pseudo gate structure 311 and the channel layer 317 are exposed, so as to form the second side wall 313 and the inner side wall 312.

In this embodiment, the inner sidewall spacers 312 are made of silicon nitride; the second side wall 313 is made of silicon nitride.

Referring to fig. 19, the directions of the views in fig. 19 and fig. 17 are the same, and after the inner sidewall 312 is formed, a source-drain doping layer 314 is formed in the source-drain opening 308.

In this embodiment, the source/drain doped layer 314 has source/drain ions therein.

When the semiconductor structure is a P-type device, the source-drain doping layer 314 is made of the following materials: silicon, germanium, or silicon germanium; the source/drain ions are P-type ions and comprise boron ions and BF ^2- Ions or indium ions; when the semiconductor structure is an N-type device, the source-drain doping layer 314 is made of materials including: silicon, gallium arsenide, or indium gallium arsenide; the source and drain ions are N-type ions and comprise phosphorus ions or arsenic ions.

In this embodiment, the semiconductor structure is an N-type device, the source-drain doping layer 314 is made of silicon, and the source-drain ions are phosphorus ions.

Referring to fig. 20, after forming the source-drain doping layer 314, a dielectric layer 315 is formed on the substrate 300, and the dielectric layer 315 covers sidewalls of the top dummy gate structure 306 and the bottom dummy gate structure 311.

In this embodiment, the method for forming the dielectric layer 315 includes: forming an initial dielectric layer (not shown) on the source-drain doping layer 314 and the dummy gate structure, wherein the initial dielectric layer covers the top surface and the side wall surface of the dummy gate structure; and flattening the initial dielectric layer until the surface of the protective layer at the top of the pseudo gate structure is exposed to form the dielectric layer 315.

In this embodiment, the material of the dielectric layer 315 is silicon oxide.

Referring to fig. 21, after the dielectric layer 315 is formed, the top dummy gate structure 306 and the bottom dummy gate structure 311 are removed, and a gate opening is formed in the dielectric layer 315; removing the sacrificial layer 302, and forming a gate groove between the adjacent channel layers 317; a gate structure 316 is formed within the gate opening and the gate trench, the gate structure 316 surrounding the channel layer 317.

In the present embodiment, the gate structure 316 includes a gate layer.

The material of the gate layer is metal, and the metal material comprises one or more of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum. In this embodiment, the material of the gate layer is tungsten.

Accordingly, an embodiment of the present invention further provides a semiconductor structure, with reference to fig. 21, including: a substrate 300, wherein the substrate 300 has a plurality of channel layers 317, the plurality of channel layers 317 are stacked along a normal direction of a surface of the substrate 300, and the channel layers 317 extend along a first direction X; the inner side wall 312 is positioned between two ends of the adjacent channel layer 317, and the side surface of the inner side wall 312 and the end surface of the channel layer 317 share a vertical surface; a gate trench between adjacent channel layers 317 or between the channel layers 317 and the substrate 300; a gate structure 316 located on the substrate 300 and in the gate trench, the gate structure 316 surrounding the plurality of channel layers 317 along a second direction Y, the first direction X being perpendicular to the second direction Y; a first sidewall 307 and a second sidewall 313 located on the sidewalls of the gate structure 316, wherein the first sidewall 307 is located on the second sidewall 313; the source and drain openings 308 are located on two sides of the gate structure 316, the inner side wall 312 is exposed out of the source and drain openings 308, and the bottom surfaces of the source and drain openings 308 are lower than the top surface of the substrate 300; a source drain doped layer 314 within the source drain opening 308.

In this embodiment, the material of the inner sidewall 312 is the same as the material of the second sidewall 313.

In this embodiment, the inner sidewall 312 is made of silicon nitride; the second side wall 313 is made of silicon nitride.

In this embodiment, the method further includes: an isolation layer 303 on the substrate 300, a top surface of the isolation layer 303 being not higher than a top surface of the channel layer 317 on a bottom layer.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A semiconductor structure, comprising:

the device comprises a substrate, a plurality of first electrodes and a plurality of second electrodes, wherein the substrate is provided with a plurality of channel layers, the channel layers are stacked along the normal direction of the surface of the substrate, and the channel layers extend along a first direction;

the inner side wall is positioned between two ends of the adjacent channel layer, and the side surface of the inner side wall and the end surface of the channel layer share a vertical surface;

a gate trench located between adjacent ones of the channel layers;

the grid structure is positioned on the substrate and in the grid groove, the grid structure surrounds the channel layers along a second direction, and the first direction is vertical to the second direction;

the first side wall and the second side wall are positioned on the side wall of the grid structure, and the first side wall is positioned on the second side wall;

source and drain openings are positioned on two sides of the grid structure, the source and drain openings expose the inner side wall, and the bottom surface of the source and drain openings is lower than the top surface of the substrate;

and the source and drain doping layer is positioned in the source and drain opening.

2. The semiconductor structure of claim 1, wherein a material of the inner sidewall spacers is the same as a material of the second sidewall spacers.

3. The semiconductor structure of claim 1, wherein the material of the inner sidewall spacers comprises silicon nitride; the material of the second side wall comprises silicon nitride.

4. The semiconductor structure of claim 1, further comprising: an isolation layer on the substrate, a top surface of the isolation layer being not higher than a top surface of the channel layer at an underlying layer.

5. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate is provided with a plurality of initial channel layers and a plurality of initial sacrificial layers, the initial channel layers and the initial sacrificial layers are stacked at intervals along the normal direction of the surface of the substrate, and the initial channel layers and the initial sacrificial layers extend along a first direction respectively;

forming a pseudo gate material layer on the substrate, wherein the pseudo gate material layer covers the side walls and the top surfaces of the initial channel layers and the initial sacrificial layers;

carrying out imaging processing on the pseudo gate material layer to form a pseudo gate structure, wherein the pseudo gate structure comprises a bottom pseudo gate material layer and a top pseudo gate structure positioned on the bottom pseudo gate material layer, the bottom pseudo gate material layer covers the side walls of a plurality of initial channel layers and a plurality of initial sacrificial layers and exposes the top surface of the initial channel layer positioned on the top layer, the top pseudo gate structure covers part of the top surface of the initial channel layer positioned on the top layer along a second direction, and the first direction is vertical to the second direction;

forming a first side wall on the side wall of the top pseudo gate structure;

etching a plurality of initial channel layers, a plurality of initial sacrificial layers and the bottom pseudo gate material layer by taking the top pseudo gate structure and the first side walls as masks to form a source drain opening, a plurality of channel layers, a plurality of sacrificial layers and an initial bottom pseudo gate structure;

etching the exposed part of the sacrificial layer on the side wall of the source drain opening, and forming an isolation groove between the adjacent channel layers;

forming an inner side wall in the isolation groove;

and forming a source drain doping layer in the source drain opening.

6. The method for forming a semiconductor structure according to claim 5, wherein the step of patterning the dummy gate material layer to form a dummy gate structure comprises: forming a patterning layer on the pseudo gate material layer, wherein the patterning layer exposes a part of the top surface of the pseudo gate material layer; and etching the pseudo gate material layer by taking the patterning layer as a mask until the top surface of the initial channel layer positioned on the top layer is exposed, so as to form the pseudo gate structure.

7. The method of forming a semiconductor structure of claim 5, wherein the dummy gate structure comprises a dummy gate layer.

8. The method of forming a semiconductor structure according to claim 5, wherein a material of the sacrificial layer and a material of the channel layer are different, and a material of the sacrificial layer is the same as a material of the dummy gate layer.

9. The method of forming a semiconductor structure of claim 8, wherein a material of the sacrificial layer and a material of the dummy gate layer comprise silicon germanium; the material of the channel layer includes silicon.

10. The method of forming a semiconductor structure of claim 8, further comprising, during the forming of the isolation recess: and thinning the initial bottom pseudo gate structure to form a bottom pseudo gate structure, wherein the size of the bottom pseudo gate structure parallel to the first direction and the second direction is smaller than the size of the initial bottom pseudo gate structure parallel to the first direction and the second direction.

11. The method for forming a semiconductor structure according to claim 10, wherein in the process of forming the inner sidewall spacers, the method further comprises: and forming a second side wall on the side wall of the bottom pseudo gate structure.

12. The method for forming the semiconductor structure according to claim 11, wherein the method for forming the second sidewall spacers and the inner sidewall spacers comprises: forming a first initial inner side wall in the isolation groove, on the side wall and the bottom surface of the source drain opening, on the side walls of the bottom pseudo gate structure and the top pseudo gate structure, and on the top surface of the top pseudo gate structure; etching the first initial inner side wall back until the bottom surface of the source drain opening and the top surface of the top pseudo gate structure are exposed to form a second initial inner side wall; and etching back the second initial inner side wall until the top pseudo gate structure, the bottom pseudo gate structure and the side wall of the channel layer are exposed, and forming the second side wall and the inner side wall.

13. The method of forming a semiconductor structure according to claim 10, wherein the material of the inner sidewall spacers comprises silicon nitride; the material of the second side wall comprises silicon nitride.

14. The method for forming a semiconductor structure according to claim 10, further comprising, after forming the source-drain doping layer: forming a dielectric layer on the substrate, wherein the dielectric layer covers the side walls of the top pseudo gate structure and the bottom pseudo gate structure; removing the top pseudo gate structure and the bottom pseudo gate structure, and forming a gate opening in the dielectric layer; removing the sacrificial layer, and forming a gate groove between the adjacent channel layers; and forming a gate structure in the gate opening and the gate groove, wherein the gate structure surrounds the channel layer.

15. The method of forming a semiconductor structure of claim 5, further comprising, prior to forming the gate structure: and forming an isolation layer on the substrate, wherein the top surface of the isolation layer is not higher than the top surface of the channel layer at the bottom layer.

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