CN115688653B - Software automatic generation process method of affair server based on software and hardware co-simulation - Google Patents
Software automatic generation process method of affair server based on software and hardware co-simulation Download PDFInfo
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- CN115688653B CN115688653B CN202310000592.6A CN202310000592A CN115688653B CN 115688653 B CN115688653 B CN 115688653B CN 202310000592 A CN202310000592 A CN 202310000592A CN 115688653 B CN115688653 B CN 115688653B
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004088 simulation Methods 0.000 title claims abstract description 24
- 238000013461 design Methods 0.000 claims abstract description 24
- 239000013598 vector Substances 0.000 claims abstract description 11
- 238000003780 insertion Methods 0.000 claims abstract description 5
- 230000037431 insertion Effects 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims abstract 2
- 238000012360 testing method Methods 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000003786 synthesis reaction Methods 0.000 claims description 6
- 230000002194 synthesizing effect Effects 0.000 abstract 1
- 238000012795 verification Methods 0.000 description 10
- 238000004891 communication Methods 0.000 description 3
- 238000013467 fragmentation Methods 0.000 description 3
- 238000006062 fragmentation reaction Methods 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 238000005192 partition Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005094 computer simulation Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
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Abstract
The invention relates to the technical field of software and hardware co-simulation, in particular to a software automatic production event server flow method based on software and hardware co-simulation, which comprises the following steps: creating a project in the compiled software; configuring the environment of the design to be tested and the server; generating a transactor. Edf by compiling software; analyzing the design to be tested, and generating a design level file to be tested; synthesizing the design to be tested in netlist analysis software to generate dut.edf; generating an interface file with the schemi information by using a script and netlist analysis software based on the files obtained in the third step to the fifth step; generating a dut _ with _ science.edf by using netlist analysis software, and combining the dut _ with _ science.edf to generate a dut _ aggregated _ vectors.edf; completing the transactor insertion into the flow framework. The invention can improve the design confidentiality and generate the process frameworks of all the servers.
Description
Technical Field
The invention relates to the technical field of software and hardware co-simulation, in particular to a software automatic generation process method of a server based on software and hardware co-simulation.
Background
Along with the continuous expansion of the scale of an integrated circuit, the time occupation of chip verification is expanded more and more, currently, except for a traditional simulator, the simulator based on a software and hardware collaborative mode is more and more popular to use, and the verification efficiency is improved through the software and hardware collaborative simulation verification mode.
The transaction server (Transactor) is used for receiving and finishing transactions on the hardware side when realizing software and hardware collaborative simulation based on a TLM communication mode, realizing that non-time sequence transactions are converted into time sequence excitation signals to be communicated with a DUT (device under test), or arranging time sequence multi-period signals into non-time sequence transactions to be sent to the software side, thereby accelerating the communication speed of software and hardware and reducing the communication time.
After an EDA tool Transactor based on software and hardware collaborative simulation verification is integrated, a set of generation flow scheme of a transaction server is urgently needed, so that the portability and configurability of a user when the user uses the Transactor to transmit and communicate with a Device Under Test (DUT) are improved, and in large-scale SOC verification, a Transactor can be inserted into any layer inside the DUT to realize instantiation.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a software automation generation server flow design method based on software and hardware collaborative simulation.
In order to achieve the technical purpose, the invention provides a software automation generation Tansor flow frame design based on software and hardware collaborative simulation verification, the required Transactor IP can be automatically generated through parameter configuration of a user on the software side, and the problem that the required Transactor cannot be automatically configured based on an emulator and can be successfully inserted into any layer in a DUT (device under test) in the software and hardware collaborative simulation verification mode process can be solved. The method comprises the following specific steps:
the software automatic generation server process design method based on software and hardware collaborative simulation comprises the following specific steps:
step one, establishing a project in compiling software;
step two, configuring the environments of the design dut to be tested and the transactor;
generating a transactor.
Analyzing the design to be tested dut through rtl analysis software, and generating a hierarchical path file hierarchy.
Selecting a bottom Up mode in the netlist analysis software to synthesize the design to be tested dut in parallel, and generating a dut.
Sixthly, generating an interface file hs _ pull _ scimi _ to _ top.json with scimi information by using a script and netlist analysis software based on the files obtained in the third step, the fourth step and the fifth step;
step seven, generating a dut _ with _ supervisor.edf netlist file by using netlist analysis software based on the hs _ pull _ supervisor _ to _ top.json netlist file and the dut.edf netlist file, and then combining the dut _ with _ supervisor.edf netlist file and the responder.edf netlist file to generate a dut _ aggregated _ vectors.edf file;
and step eight, completing the transactor insertion process frame.
Specifically, the second step at least comprises setting an engineering type, a top-level module, a comprehensive tool, a dut file path, an instantiated transactor type and a name, and obtaining a transactor name.
Further, the third step is specifically: inputting a command name in compiling software, and generating a xactor _ src folder under a project file, wherein the xactor _ src folder contains a command name.
Further, the fourth step is specifically: and inputting command analyze (), and generating a hierarchy path file of hierarchy.
Further, the fifth step is specifically: setting a synthesis mode as bottom Up, inputting a transformer _ name _ stub.v file and a design source file to be tested dut.v, generating a dut.edf netlist file, and merging all netlist files after synthesis is finished.
Further, the sixth step specifically comprises: generating a test _ src folder by using a script and netlist analysis software according to a dut.edf netlist file, a hierarchy.txt hierarchical path file and a xactor _ src folder, wherein the test _ src folder at least comprises a needed transactor information file and an interface file hs _ pull _ sci _ to _ top.json with scimi information generated by the script;
further, the test _ src folder includes an hs _ xactors.f list file, and the required transactor information file is included in the hs _ xactors.f list file.
Further, the third step obtains a transaction.
Further, when the transaction
From the above description, it can be seen that the present invention has the following advantages:
1. transactors can be inserted into any layer in the DUT at the EDIF level, and the design confidentiality is better improved.
2. All the Transactor flow frames can be generated, and the required IP can be automatically generated from the lib library under the installation catalog by transmitting the name and the configuration information of the Transactor.
3. The automatic generation flow frame of the Transactor can be suitable for multi-chip verification after Partition fragmentation of the FPGA.
Drawings
FIG. 1 is a flow chart of the present invention.
Detailed Description
With reference to fig. 1, a specific embodiment of the present invention is described in detail, but the present invention is not limited in any way by the claims.
As shown in fig. 1, the software automation generation process method based on software and hardware co-simulation specifically includes the following steps:
the software automatic generation affair server flow design method based on software and hardware co-simulation includes the following steps:
step one, creating a project test in compiling software (Vivado, synplify and other compiling software can be adopted);
step two, configuring the environment of the design to be tested dut and the transactor, including setting an engineering type, a top layer module, a comprehensive tool, a dut file path, an instantiated transactor type and name and the like, to obtain a transactor name, and instantiating a plurality of transactor types and names, namely obtaining a plurality of transactor names;
step three, generating a transactor. Edf netlist file of each transactor name through compiling software, and specifically comprising the following steps:
inputting command name in compiling software, and generating a factor _ src folder under a project file, where the factor _ src folder contains a factor name.edf file, a factor name _ stub.v file, and a configuration file config.txt, and when there are multiple factor names, the factor _ src folder contains multiple folders, each folder corresponds to a factor name, and contains a factor name.edf file, a factor name _ stub.v file, and a configuration file config.txt file, and the file structures are as follows:
test
|——xactor_src
|——name1
txt (information describing user settings)
I-name 1_ stub.v (Transactor Port information only. V File)
| name1.Edf (Transactor netlist file)
|——name2
|——config.txt
|——name2_stub.v
|——name2.edf
Analyzing the design to be tested dut through rtl analysis software, and generating a hierarchy path file hierarchy.
Inputting command analyze (), and generating a hierarchy path file;
fifthly, selecting a bottom Up mode in netlist analysis software (such as veridic software) to synthesize the design to be tested in parallel to generate a dut.
Setting a synthesis mode as bottom Up, inputting a transformer _ name _ stub.v file and a design source file to be tested dut.v, generating a dut.edf netlist file, and merging all netlist files after synthesis is finished;
step six, generating an interface file hs _ pull _ science _ to _ top.json with science information by using a script and netlist analysis software based on the files obtained in the step three, the step four and the step five; the method comprises the following specific steps:
according to the dual.edf netlist file, the hierarchy path file and the xactor _ src folder, a script (such as python) and netlist analysis software are used to generate a test _ src folder, the test _ src folder at least comprises an hs _ xactor.f list file and an interface file hs _ pull _ scheme _ to _ top.jjson generated by the script and provided with scheme (standard collaborative simulation modeling interface) information, a needed transactor information file is contained in the hs _ xactor.f list file, and the file structure is as follows:
test
|——test.src
i-hs _ vectors.f. (containing the list of vectors files required)
Json (interface file containing science information)
|——xactor_src
|——name
|——config.txt
|——name_stub.v
|——name.edf
Step seven, generating a du _ with _ score.edf netlist file by using netlist analysis software based on the hs _ pull _ score _ to _ top.json netlist file and the du.edf netlist file, then merging the du _ with _ score.edf netlist file and the transactor.edf netlist file to generate a du _ aggregated _ vectors.edf file, wherein the file structure is as follows:
test
|——test.backend
|——edf
| -dut _ merged _ vectors.edf (complete netlist file of completed dut insert vector)
|——test.src
|——hs_xactors.f
|——hs_pull_scemi_to_top.json
|——xactor_src
|——name
|——config.txt
|——name_stub.v
|——name.edf
And step eight, completing the transactor insertion process frame.
When the invention is implemented, when the obtained netlist file is the transaction.
Based on the FLOW method, it can be seen that:
1. when analyzing the DUT layer information, hierarchy files of all layers can be generated, so that a user can select to insert a transformer at any layer, namely, the effect of inserting a transformer at any layer in a DUT (device under test) at an EDIF (netlist level file) level can be realized, and the design confidentiality is better improved;
2. after the configuration step of the transactors is completed, each Transactor name generates an independent folder which can contain the needed Transactor file and is beneficial to multiplexing and instantiating of the subsequent steps, so that flow frames of all the transactors can be generated, and the needed IP can be automatically generated from the installation catalog by transmitting the name and configuration information of the Transactor;
3. the automatic generation flow frame of the Transactor can be suitable for multi-chip verification after Partition fragmentation of the FPGA.
Therefore, in summary, the invention has the following advantages:
1. transactors can be inserted into any layer in the DUT at the EDIF level, and the design confidentiality is better improved.
2. All the Transactor flow frames can be generated, and the required IP can be automatically generated from the lib library under the installation catalog by transmitting the name and the configuration information of the Transactor.
3. The automatic generation flow frame of the Transactor can be suitable for multi-chip verification after Partition fragmentation of the FPGA.
It should be understood that the detailed description of the invention is merely illustrative of the invention and is not intended to limit the invention to the specific embodiments described. It will be appreciated by those skilled in the art that the present invention may be modified or substituted equally as well to achieve the same technical result; as long as the use requirements are met, the method is within the protection scope of the invention.
Claims (9)
1. The software automatic generation process method based on software and hardware collaborative simulation comprises the following specific steps:
step one, establishing a project in compiling software;
step two, configuring the environments of the design dut to be tested and the transactor;
step three, generating a transactor.
Analyzing the design to be tested dut through rtl analysis software, and generating a hierarchical path file hierarchy.
Selecting a bottom Up mode in the netlist analysis software to synthesize the design to be tested dut in parallel, and generating a dut.
Sixthly, generating an interface file hs _ pull _ scimi _ to _ top.json with scimi information by using a script and netlist analysis software based on the files obtained in the third step, the fourth step and the fifth step;
step seven, generating a dut _ with _ supervisor.edf netlist file by using netlist analysis software based on the hs _ pull _ supervisor _ to _ top.json netlist file and the dut.edf netlist file, and then combining the dut _ with _ supervisor.edf netlist file and the responder.edf netlist file to generate a dut _ aggregated _ vectors.edf file;
and step eight, completing the transactor insertion process frame.
2. The software automation generation process of the event server based on software and hardware co-simulation as claimed in claim 1, wherein: and the second step at least comprises setting the project type, the top layer module, the comprehensive tool, the dut file path, the instantiated transactor type and the name, and obtaining the transactor name.
3. The software automation generation process of the event server based on software and hardware co-simulation as claimed in claim 2, wherein: the third step is specifically as follows: a command _ vector name is input in compiling software, and a vector _ src folder is generated under a project file and contains a vector name.
4. The software automation generation process of the event server based on software and hardware co-simulation as claimed in claim 3, wherein: the fourth step is specifically as follows: and inputting command any (), and generating a hierarchy path file.
5. The software automation generation process of the event server based on software and hardware co-simulation as claimed in claim 4, wherein: the fifth step is specifically as follows: setting a synthesis mode as bottom Up, inputting a reflector _ name _ stub.v file and a design source file to be tested dut.v, generating a dut.edf netlist file, and merging all netlist files after synthesis is finished.
6. The method for automatically generating the process of the event server based on the software and hardware co-simulation as claimed in claim 5, wherein: the sixth step is specifically as follows: and generating a test _ src folder by using a script and netlist analysis software according to the dut.edf netlist file, the hierarchy.txt hierarchical path file and the xactor _ src folder, wherein the test _ src folder at least comprises a needed transactor information file and an interface file hs _ pull _ sci _ to _ top.json with scimi information generated by the script.
7. The software automation generation process of a facture server based on software and hardware co-simulation of claim 6, wherein: the test _ src folder includes an hs _ xactors.f list file, and the needed transactor information file is included in the hs _ xactors.f list file.
8. The software automation production process of an event server based on software and hardware co-simulation of claim 1, wherein: and step three, obtaining a transaction.
9. The software automation generation process of a facture server based on software and hardware co-simulation as claimed in claim 8, wherein: and when obtaining the transaction netlist files of the transactions of the multiple transactions in the third step, repeatedly executing the fourth step to the eighth step, and completing the insertion of the transaction of each transaction into the process frame.
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| CN111400169B (en) * | 2020-02-25 | 2023-04-18 | 中科亿海微电子科技（苏州）有限公司 | Method and system for automatically generating netlist file for testing software and hardware |
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