CN115687241A - Interrupt controller, system on chip, intelligent device and interrupt processing method - Google Patents

Abstract

The application provides an interrupt controller, a system on chip, an intelligent device and an interrupt processing method. The interrupt controller is controlled by the management control processor and includes: an input port configured to receive an interrupt request from external hardware; an interrupt routing module configured to bypass output of the interrupt request or route and convert the interrupt request into an interrupt instruction; and an output port configured to output an interrupt instruction to one or more of the plurality of functional application subsystems that are isolated from each other.

Description

Interrupt controller, system on chip, intelligent device and interrupt processing method

Technical Field

The present invention relates to the field of computer systems, and more particularly, to an interrupt controller, a system on a chip, an intelligent device, and an interrupt processing method.

Background

In a large trend of integration of system functions, functions of a plurality of subsystems are integrated by a SOC (system on chip), which is particularly useful for a multifunctional system such as an automobile. For example, an on-board system platform usually includes a plurality of functional application subsystems, such as a cockpit system, a vehicle control system, a driving assistance system (e.g., ADAS/ADS system), etc., which respectively correspond to human-computer interaction, vehicle control, and automatic driving assistance functions. For security reasons, isolation is made between a plurality of functional systems, preferably between hardware entities, and the necessary controlled communication between the systems is possible.

In the conventional interrupt controller, the interrupt instruction arbitrated and output by the interrupt controller is directly sent to the CPU, so that the control of the interrupt controller and the application of the interrupt instruction are integrated, and the management function requirements of classification and role separation cannot be satisfied. In addition, for hardware platforms of a plurality of mutually isolated functional application subsystems, it is also difficult to configure and process interrupt information according to the requirements of actual functional subsystems, and further difficult to implement an overall system structure for flexibly configuring the SOC.

Disclosure of Invention

The application provides an interrupt controller, a system on chip, an intelligent device and an interrupt processing method.

A first aspect of the present application relates to an interrupt controller, which is controlled by a management control processor, and includes: an input port configured to receive an interrupt request from external hardware; an interrupt routing module configured to bypass output of the interrupt request or route and convert the interrupt request into an interrupt instruction; and an output port configured to output the interrupt instruction to one or more of the plurality of functional application subsystems that are isolated from each other.

In one embodiment, the input port includes an input signal line and a message input channel; wherein the input port is configured to: receiving an interrupt signal as the interrupt request from one signal line or from a plurality of signal lines in parallel; and/or serially receiving an interrupt message as the interrupt request from the message input channel.

In one embodiment, the output port includes an output signal line and a message output channel; wherein the output port is configured to output a signal instruction as the interrupt instruction to a specified one or more of the functional application subsystems through the output signal line and/or output a message instruction as the interrupt instruction to a specified one or more of the functional application subsystems through the message output channel.

In one embodiment, the interrupt routing module is configured to, in a case where the interrupt signal is received, bypass the interrupt signal without converting into an interrupt instruction when a disable bypass instruction from the management control processor is not received, and route and convert the interrupt signal into the interrupt instruction when a disable bypass instruction from the management control processor is received; in case the interrupt message is received, the interrupt message is routed and converted into the interrupt instruction.

In an embodiment, the interrupt routing module is further configured to set an enable state and a parameter of the input signal line, an enable state and a parameter of the output signal line, enable states of the message input channel and the message output channel, and a trigger mode of the interrupt controller based on control of the management control processor.

In one embodiment, the interrupt controller further comprises a cache module included in the message output channel; and according to the control of the management control processor, the message instruction is put into a cache module in a plurality of message output channels with assigned priority order and is sequentially output to a plurality of function application subsystems according to the priority order.

In an embodiment, the interrupt controller further includes a statistics module, which serves as an interface with the functional application subsystem, and is configured to perform statistics on the interrupt request and the interrupt instruction.

A second aspect of the present application relates to a system on chip comprising: the interrupt controller according to the above embodiment; the management control processor is configured to control the interrupt controller; and the plurality of mutually isolated functional application subsystems are configured to receive the interrupt instruction according to the priority order of the interrupt instruction so as to realize the function of terminal application.

In an embodiment, the system on chip comprises a plurality of said interrupt controllers cascaded to each other, said interrupt request being routed and translated into said interrupt instruction via a plurality of said interrupt controllers.

A third aspect of the application relates to a smart device comprising a system on chip according to the above embodiments.

A fourth aspect of the present application relates to an interrupt processing method applied to an interrupt controller, including executing the following steps based on control of a management control processor: receiving an interrupt request from external hardware; bypassing the interrupt request for output, or routing and converting the interrupt request into an interrupt instruction; and outputting the interrupt instruction to one or more of the plurality of functional application subsystems isolated from each other.

According to the interrupt controller, the system on chip, the intelligent device and the interrupt processing method, the interrupt instruction output by the interrupt controller is directly connected with the plurality of mutually isolated functional application subsystems through hardware, so that the control and the use of the interrupt can be separated from each other, and the classification and role separation management of the system can be realized. In addition, the interrupt controller is compatible with signal-based and message-based input and output, can be compatible with current mainstream signal-based interrupt, and can simultaneously realize message-based interrupt, thereby realizing personalized and customized dynamic configuration of the system according to the actual requirements of the functional application subsystem, and improving the adaptability and safety of the whole system.

Drawings

FIG. 1 is a block diagram of an overall architecture of an interrupt controller according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an exemplary application of an interrupt controller according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an exemplary application of an interrupt controller according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a system on a chip according to an embodiment of the present application;

fig. 5 is a flowchart illustrating the overall operation of a system on chip according to an embodiment of the present application.

FIG. 6 is a schematic diagram of a system on chip according to an embodiment of the present application;

fig. 7 is a flowchart of an interrupt processing method according to an embodiment of the present application.

Detailed Description

The current SOC system mainly includes: CPU (e.g., ARMv9, ARMv8, ARMv7, RISC-V, etc.), memory (e.g., SRAM, DDR, etc.), bus (e.g., AXI, AHB, APB, etc.), communication unit (e.g., uart, can/Canfd, GMAC/XGMAC, USB, PCIe, etc.), external storage unit (Norflash, nandflash, EMMC, UFS, etc.). The SOC with a plurality of function application subsystems and configurable functions also comprises the following core units: the system comprises an address mapping unit, an address reverse mapping unit, an interrupt signal routing control unit, a multi-channel interface unit supporting a plurality of functional application subsystems, a platform system management control unit and the like.

For a signal transmission control unit in a core unit, a GIC series interrupt controller is generally adopted in an ARM architecture at present, but the requirement of management of classification and role separation of an SOC cannot be met. The present application thus provides a signaling control unit for controlling and using interrupt controllers separated from each other, while being adapted to a configurable hardware platform supporting a plurality of functional application subsystems.

The interrupt controller according to the present application may also be referred to as a "signal routing unit," i.e., an interrupt router unit (hereinafter, referred to as an IRU in the present application). The IRU is controlled by the management control processor and interacts with the plurality of functional application subsystems to output interrupt instructions to the functional application subsystems. In the present application, the management control processor may also be referred to as a "management control unit," namely, a ManageControlUnit (hereinafter, referred to as MCU in the present application). The multiple functional application subsystems are physically separated in hardware, and necessary intersystem controlled communication can be performed between the multiple functional application subsystems. For example, in the vehicle SOC, the plurality of functional application subsystems may be a cabin system, a vehicle control system, a driving assistance system, and the like, and the cabin system and the driving assistance system may share relevant parameters of the current vehicle operation state. In the present application, the functional application subsystem may also be referred to as an application processing system (hereinafter referred to as APS in the present application). The APS and the MCU are mutually independent, and the APS and the MCU are physically separated on hardware, even in a heterogeneous CPU system. Further, the APSs each include a processor as a core member thereof as long as the APSs can implement a specific function. The IRU interacts with the MCU and the APS respectively, and particularly, the IRU processes an interrupt request under the control of the MCU and outputs and applies an interrupt instruction to the APS.

Referring to fig. 1, a general block diagram of an IRU 100 according to an embodiment of the present application is shown. The IRU 100 includes an input port 110, an interrupt routing module 130, and an output port 150. The input port 110 may be connected to external hardware and configured to receive interrupt requests from the external hardware. It should be understood that the input port 110 may be connected directly to external hardware, or may be connected to external hardware through an intermediate element. For example, in the cascade mode described later, the input port 110 may be connected to external hardware via another IRU. The external hardware is an interrupt source that generates an interrupt, and the IRU 100 receives an interrupt request from the external hardware through the input port 110. When the IRU 100, the MCU 200 and the APS are all integrated on the same SOC, the external hardware may be a hardware module that is integrated on the SOC but physically separated from the above modules, or may be a device other than the SOC. In particular, the external hardware may also be another IRU, for example, in the case of a cascade of a plurality of IRUs (to be described in detail later), an interrupt instruction output from one IRU may serve as an interrupt request input to another IRU.

The interrupt routing module 130 is a core module of the interrupt controller IRU 100 of the present application, and is configured to bypass output or route and convert interrupt requests into interrupt instructions by a bypass unit 132 included therein. For example, interrupt requests may be bypassed out through bypass port 160. The output port 150 may be connected to a plurality of APS isolated from each other and configured to output an interrupt instruction to one or more APSs. In the present application, the plurality of APS isolated from each other means that the plurality of APS are isolated from each other by hardware, but the plurality of APS systems may be controlled to communicate with each other. It should be understood that the output port 150 may be connected directly to the APS, or may be connected to the APS through an intermediate element, for example, in a cascade mode described later, the output port 150 may be connected to the APS via another IRU. The interrupt instruction may be provided with a priority order, and the output port 150 outputs to the APS according to the priority order. The IRU 100 may output an interrupt instruction to each of the plurality of APSs to which it is connected through the output port 150, or may output an interrupt instruction to a part of the plurality of APSs to which it is connected. The input port 110, the interrupt routing module 130, and the output port 150 are communicatively connected.

According to the above configuration, the input port 110, the interrupt routing module 130 and the output port 150 in the IRU 100 are controlled by the MCU, and perform corresponding processes based on the configuration of the MCU. The output port directly interfaces with a corresponding interface in the APS through hardware, so that the interrupt instruction is directly applied to the APS, which is beneficial to dynamically and flexibly configuring the IRU 100 according to the specific application requirements of the APS. In this way, the control of the interrupt (by the MCU) and the use (by the APS) can be separated from each other, and since the MCU and the APS are separated in both hardware and operation control, hierarchical and role separation management of the system can be easily achieved.

An exemplary application schematic diagram of the IRU 100 according to an embodiment of the present application will be described below with reference to fig. 2.

In an embodiment, the input port 110 may include an input signal line and a message input channel. The input signal lines and the message input channels may have a plurality of sets, respectively, for inputting interrupt requests from external hardware to the IRU 100. The interrupt request may include an interrupt signal and an interrupt message. The interrupt signal is a signal (signal) that exists in different trigger types, such as edge triggered and level triggered, where edge triggered includes rising edge triggered and falling edge triggered, and level triggered includes high level triggered and low level triggered. The type of triggering of the interrupt signal is well known to those skilled in the art and will not be described further herein. An interrupt message is an encoded message that may include the specific content to be signaled. After receiving the interrupt message, the IRU 100 decodes the encoding definition of the interrupt message to obtain the input signal line ID. The input signal line ID refers to the number of the input signal line, which is used to indicate from which input signal line the interrupt request is, and thus can indicate from which interrupt source the interrupt request is. Illustratively, the input signal line ID is defined encoded into the interrupt message, i.e., there is a correspondence between a particular encoding in the interrupt message and the input signal line ID. For example, the interrupt message includes an interrupt message ID value, and there is a correspondence relationship between the interrupt message ID value and the input signal line ID. Taking the case where there are 8 input signal lines, the signal line IDs are line0, line1, and line2 \8230 \ 8230and line8, respectively, and the corresponding interrupt message ID values are, for example, 0, 1, 2 \8230 \ 8230and 8. The corresponding input signal line ID can be obtained by decoding the encoded definition of the interrupt message, and thus from which external hardware the interrupt message originated can be obtained.

When the interrupt request received by the IRU includes an interrupt signal, the interrupt signal is input to the IRU 100, specifically, to the interrupt routing module 130 through the input signal line, and the IRU 100 is triggered to operate by the interrupt signal. There may be a plurality of parallel input signal lines through which a plurality of interrupt signals are input to the IRU 100 in parallel. In other words, the input port 110 is configured to receive an interrupt signal as an interrupt request from one signal line or from a plurality of signal lines in parallel. The input based on the signal line is preferentially selected, and the IRU is triggered to work based on the input interrupt signal, so that the IRU is more easily butted with the current mainstream interrupt signal. In the example of fig. 2, an example is described in which the interrupt request input to the IRU 100 is an interrupt signal.

When the interrupt request received by the IRU includes an interrupt message, the interrupt message is input to the IRU 100, specifically, to the interrupt routing module 130 through the message input channel, and the IRU 100 is triggered to operate through the message. Interrupt messages are input to the IRU 110 through the message input channel in a serial mode, in other words, the input port 110 is configured to serially receive interrupt messages as interrupt requests from the message input channel. The case where the interrupt request received by the IRU is an interrupt message is common to the concatenation of the IRU 110, and the concatenation of the IRU 110 will be described in detail later.

In an embodiment, output port 150 may include an output signal line and a message output channel. The output signal line and the message output channel may have a plurality of groups, respectively, for outputting an interrupt instruction obtained by processing and converting an interrupt request via the IRU 100 to the APS. The interrupt instruction obtained by converting the interrupt request by the IRU 100 includes a signal instruction and a message instruction. The signal instruction is a signal (signal) which has different trigger types, such as edge trigger and level trigger, wherein the edge trigger comprises rising edge trigger and falling edge trigger, and the level trigger comprises high level trigger and low level trigger. The type of triggering of the interrupt signal is well known to those skilled in the art and will not be described in detail herein. The message instruction is an encoded message (message) which may include the specific content to be conveyed, and the output signal line ID may be obtained by decoding. The output signal line ID refers to the number of the output signal line for indicating from which output signal line the interrupt instruction to be output is to be output to the corresponding APS. Illustratively, the output signal line ID is defined by a code into the message instruction, i.e., there is a correspondence between a specific code in the message instruction and the output signal line ID. For example, the message instruction includes a message instruction ID value, and there is a correspondence between the message instruction ID value and the output signal line ID. Taking 8 output signal lines as an example, the output signal lines ID are line0, line1, line2 \8230; line8, and the corresponding message command ID values are, for example, 0, 1, 2 \8230; 8. The corresponding output signal line ID can be obtained by decoding the encoding definition of the message instruction, and therefore the message instruction to be output to a specific APS can be obtained.

When the interrupt instruction includes a signal instruction, the output port 150 of the IRU 100 may be configured to output the signal instruction as the interrupt instruction to one or more APSs through the output signal line, the functional operation of the APSs being triggered by the signal instruction. In this case, each APS receiving a signal instruction is connected to the IRU 100 through at least one signal line. When there are a plurality of output signal lines, the plurality of output signal lines may be provided with priorities and output signal instructions to the APS in accordance with the priorities of the signal lines.

When the interrupt instruction includes a message instruction, the output port 150 of the IRU 100 may be configured to output the message instruction as the interrupt instruction to one or more APSs through the message output channel, and trigger a functional operation of the APSs through the message instruction. In this case, each APS receiving the message instruction is connected to the IRU through at least one message output channel. Illustratively, for each APS receiving an interrupt instruction, for which an interrupt is to be performed using a signal instruction or a message instruction accordingly, is connected to the IRU 100 through one of the output signal line and the message output channel. In the example shown in fig. 2, the first APS and the second APS are connected to the IRU 100 through a message output channel and accordingly receive a message instruction output from the IRU 100, and the third APS is connected to the IRU 100 through an output signal line and accordingly receives a signal instruction output from the IRU 100.

It should be understood that, among the plurality of APS isolated from each other, a part of the APS may be connected to the IRU 100 through an output signal line, and the rest of the APS may be connected to the IRU 100 through a message output channel; in other embodiments, all of the plurality of APS isolated from each other may be connected to the IRU 100 through a message output channel.

In one embodiment, the interrupt routing module 130 is configured to bypass the interrupt signal by default without converting to the interrupt instruction when the disable bypass instruction is not received from the MCU 200 in the event that the interrupt signal is received. In other words, the default processing of the received interrupt signal by the interrupt routing module 130 is to bypass (bypass) the interrupt signal by the bypass unit 132, i.e., to abandon the routing processing of the interrupt signal, i.e., the interrupt signal input into the IRU 100 is not processed by the route conversion unit 134, which will be described later, and is not routed to the APS. When receiving the disable bypass instruction from the MCU 200, the interrupt signal is passed to the route conversion unit 134 for subsequent processing, specifically, routing and converting the interrupt signal into an interrupt instruction. That is, only when the MCU 200 transmits an instruction to the IRU 100 to disable the bypass of the interrupt signal, the input interrupt signal is not bypassed and is passed to the route conversion unit 134 for subsequent processing. The route conversion unit 134 routes and converts the input interrupt signal or interrupt message according to the set route conversion rule to generate an interrupt instruction and route the interrupt instruction to the corresponding output port. The route conversion unit 134 converts the input interrupt request into target content and routes to an output signal line of a destination or a message output channel. The rules and destinations of the conversion are set by MCU 200 for IRU 100.

In the above-described embodiment, the bypass processing is applied only to the case where the input interrupt request is an interrupt signal. In case the IRU 100 receives an interrupt message, the interrupt message is not bypassed but must be passed on to the route conversion unit 134 for subsequent processing, in particular routing and conversion of the interrupt message into an interrupt instruction.

In an embodiment, the interrupt routing module 130 is further configured to set the enable state and parameters of the input signal lines, the enable state and parameters of the output signal lines, the enable states of the message input channel and the output message channel, and the trigger mode of the IRU 100 based on the control of the MCU 200. Each input signal line is assigned a specific ID, i.e., an input signal line ID (signalID). The enable state (enable) of an input signal line refers to whether the input signal line is activated for receiving an interrupt signal, and the input signal line can receive the interrupt signal only when the enable state of the input signal line is in the activated state. The parameters of the input signal line include a trigger type (TriggerType) and a trigger level (TriggerLevel). The trigger type is for example level triggered or edge triggered, the trigger level being for example high or low. The interrupt signal can be input into the interrupt routing module 130 through the input signal line only when the enable state of the input signal line is in the active state and the trigger type and trigger level of the interrupt signal input through the signal line are identical to the corresponding parameters set by the interrupt routing module 130.

Each output signal line is also assigned a specific output signal line ID. The enable state (enable) of the output signal line refers to whether the output signal line is activated for outputting the interrupt signal, and the output signal line can be used for outputting the interrupt signal only when the enable state of the output signal line is in the activated state. The parameters of the output signal line include a trigger type (TriggerType) and a trigger level (TriggerLevel). The type of trigger is, for example, level-triggered or edge-triggered, and the trigger level is, for example, high or low. When the enable state of the output signal line is in an active state, a signal command in accordance with the parameter configuration of the output signal line is output to the APS through the output signal line.

The enable state of the message input channel and the enable state of the message output channel refer to whether the message input channel and the message output channel are activated for inputting an interrupt message or outputting an interrupt instruction, respectively. A corresponding channel can only be used for entering/inputting messages when the channel is active.

The trigger mode of the IRU 100 refers to whether the IRU 100 triggers its own operation by responding to an input of an interrupt message or triggers its own operation by responding to an input of an interrupt signal, and accordingly includes a message trigger and a signal trigger. In practical applications, the IRU 100 may begin operation in response to receiving one or both of an interrupt message and an interrupt signal. Illustratively, this is accomplished by enabling the input signal line, setting the input signal line.

It should be noted that although the configuration of the enable states and parameters of the input ports, the output ports, and the trigger mode of the interrupt controller is implemented by the interrupt routing module 130 of the IRU 100 in the above description, the interrupt routing module 130 actually provides an interface with the MCU 200, through which the MCU 200 implements the configuration of the above-described setting of the interrupt routing module 130. That is, the MCU 200 controls the interrupt routing module 130, so that the interrupt routing module 130 controls the input of the IRU 100, the enable state of the output port, parameters, and trigger mode.

On the other hand, the MCU 200 also implements rule configuration for route conversion. The MCU 200 configures a route conversion rule of the route conversion unit 134. The conversion unit 134 routes and converts the interrupt signal into an interrupt instruction based on the route conversion rule. For example, a rule that the IRU 100 outputs an input interrupt request as an interrupt instruction is set by control of the MCU 200, including a corresponding path setting from an input port to an output port and a corresponding conversion setting (e.g., converting an interrupt signal into a message instruction, converting an interrupt message into a signal instruction, converting an interrupt signal into a signal instruction, or converting an interrupt message into a message instruction). So that the IRU 100 can perform accurate conversion and routing via the route conversion unit when there is an interrupt message or an interrupt signal. Illustratively, the MCU 200 may set a source port (SrcPort, an input port representing an interrupt signal, e.g., an input signal line ID), a destination port (DestPort, an output port representing a signal instruction, e.g., an output signal line ID), a source ID (SrcID, an input port representing an interrupt message, e.g., an interrupt message ID value of an interrupt message), a destination ID (DestID, an output port representing a message instruction, e.g., a message instruction ID value of a message instruction), and a routing relationship therebetween and a priority order of outputting the interrupt instructions. Depending on the configuration of the MCU 200, the IRU 100 specifies to which functional application subsystem an interrupt instruction is to be output. The MCU 200 also sets configuration of parameters including a route conversion rule to the route conversion unit 134 in the interrupt routing module 130 through an interface with the interrupt routing module 130. That is, in short, the setting of the input ports, the routing and conversion processes, and the setting of the output ports of the IRU 100 are all configured in advance by the MCU 200.

In an embodiment, the IRU 100 further includes a statistics module 170, and the statistics module 170 may be implemented as an APS-oriented interface configured to perform statistics on interrupt requests and interrupt instructions. Referring to the shaded arrows in fig. 2, the APS may interact with the statistics module 170 of the IRU 100, and the statistics of the interrupt request and the interrupt instruction includes recording the status and statistical information of the interrupt request and the interrupt instruction, which may be read, cleared, reset, cleared, and the like by the APS 300. The accessible area of the APS 300 to the IRU 100 is set by the MCU.

In the example of fig. 2, three transfer paths of the input interrupt signal, i.e., a bypass output, a message instruction output through a message output channel, and a signal instruction output through an output signal line, are shown. The specific process is as follows: the interrupt signal is input to the interrupt routing module 130 of the IRU 100 through an input signal line and is bypassed and output by the bypass unit 132; on the other hand, the signal that is not bypassed is first preprocessed based on the parameter configuration in the route conversion unit 134 and then routed and converted based on the predetermined route conversion rule configuration, a message instruction and/or a signal instruction is generated, and accordingly output to each APS through the message output channel and the output signal line.

According to the embodiment of the application, the interrupt instruction is directly connected to the APS through hardware, so that the control and the use of the interrupt can be separated from each other, and the classification and the role separation management of the system can be realized. In practical applications, the output normal interrupt instruction is usually mainly a message instruction and is output to the APS through a message output channel. Therefore, the APS is interrupted through the message, so that the dynamic configuration of function personalization and customization of the system according to actual requirements can be realized, and the adaptability and the safety of the whole system are improved.

Although the input interrupt signal, the output message instruction, and the signal instruction are illustrated in fig. 2 as examples, it should be understood that according to the IRU 100 of the present application, either or both of the interrupt signal and the interrupt message may be input, and either or both of the output message instruction and the signal instruction may be output after being routed and converted by a predetermined routing conversion rule configuration. For example, the IRU 100 may receive interrupt messages and output signal instructions after conversion and processing.

With further reference to fig. 3, in an embodiment, the IRU 100 further includes a caching module 190. The buffer module 190 may be included in the message output channel as a component in the message output channel. According to the control of the MCU 200, the message instructions are put into the respective buffer modules 190 in the plurality of message output channels that can be assigned with a priority order, and are sequentially output to the plurality of functional application subsystems according to the priority order. In this way, the message commands are sequentially output to the APS according to the priority order and processed.

In the example of fig. 3, the caching module 190 includes a plurality of message memories. The message memory is for example a FIFO memory. For example, each message output channel is integrated with a FIFO memory. Each FIFO memory stores a queue of messages, the number of message units in the queue being adjustable to be greater than 1, without any particular limitation. The priority order of the message queues to be output to the APS is configured by a weight, which is set by the MCU 200, and the priority order is determined according to the sequence number of the message output channel in a default mode without special setting.

FIG. 4 is a schematic diagram of a system-on-chip SOC according to the present application. Integrated on this SOC are an IRU 100, an MCU 200 and a plurality of APS 300 isolated from each other according to the above described embodiments, wherein IRU 100 interacts with MCU 200 and APS 300, respectively, and is controlled by MCU 200. The interaction and control between the IRU 100 and the MCU 200 and the APS 300 are as described in the above embodiments and will not be described herein. The APS 300 may be configured to receive an interrupt instruction from the IRU 100 according to a priority order of the interrupt instruction to implement a function of a terminal application. For example, when the APS 300 is a cabin system in a vehicle, if an interrupt request requiring the cabin system to adjust the seat state is generated by external hardware, the IRU 100 directly outputs an interrupt instruction to the cabin system under the control of the MCU 200, so that the cabin system can achieve adjustment of the seat state in response to the interrupt instruction. APS 300 may also interact with MCU 200 to read, clear, reset, etc. status and statistics of interrupt requests and interrupt instructions.

The overall operation flow of the SOC is described with reference to fig. 5. In S501, the SOC is powered on and started, and the SOC starts to operate. In S502, the MCU 200 starts and loads the configuration parameter file of the IRU 100 accordingly. The configuration parameter file of the IRU is a file for configuring the IRU 100. The configuration implemented by the IRU 100 based on the file includes, for example: enable states and parameters of input signal lines, enable states and parameters of output signal lines, enable states of message input channels and message output channels, trigger patterns of the IRU, route switching rules, precedence setting rules, areas of the IRU accessible by APS 300 when interacting with IRU 100, and the like. These specific configurations are described in detail in the above embodiments, and are not described herein again.

In S503, the MCU 200 configures the IRU 100 based on the configuration parameter file, and the IRU 100 completes the corresponding configuration operation. Accordingly, the IRU 100 accomplishes one or more of the following configurations: an enable state and parameter of an input signal line, an enable state and parameter of an output signal line, enable states of a message input channel and a message output channel, a trigger mode of the IRU, a route switching rule, a priority setting rule, an area of the IRU accessible when the APS 300 interacts with the IRU 100, and the like. These specific configurations are described in detail in the above embodiments, and are not described herein again. The control of the IRU 100 by the MCU 200 may be embodied as the configuration of the IRU 100 by the MCU 200 based on the configuration parameter file.

In S504, the MCU 200 transmits a disable bypass instruction to the IRU 100. Only when the IRU 100 receives the disable bypass instruction from the MCU 200, the interrupt signal is processed by the route conversion unit in the IRU 100, i.e., converted into an interrupt instruction according to a predetermined rule and routed to the corresponding output port. In an embodiment, only when the interrupt request input into the IRU 100 includes an interrupt signal, the IRU 100 needs to determine whether to bypass the interrupt signal according to whether a disable bypass instruction is received from the MCU 200; when the interrupt request input to the IRU 100 is an interrupt message, the interrupt message is not bypassed but is necessarily passed to the route conversion unit 134 for the subsequent route conversion processing.

In S505, IRU 100 outputs an interrupt instruction to APS 300. The IRU 100 routes and converts the interrupt request into an interrupt instruction according to a predetermined route conversion rule, and outputs the interrupt instruction to the APS 300 through the output port 150. In an embodiment, the output port 150 is directly connected to the APS 300, and thus the interrupt instruction output from the IRU 100 is directly applied to the APS 300.

In S506, the APS 300 receives the interrupt instruction, and implements the corresponding function according to the interrupt instruction.

Further referring to fig. 6, in an embodiment, the SOC according to the above embodiment includes a plurality of interrupt controllers cascaded with each other, and the configuration of each interrupt controller refers to the description of the above embodiment. In the example shown in FIG. 6, IRU 100-1, IRU 100-2 \8230, 8230, IRU 100-n are cascaded in sequence. In the example shown in FIG. 6, the input port of IRU 100-1 is directly connected to external hardware, the output port of IRU 100-1 is directly connected to the input port of IRU 100-2, the output port of IRU 100-2 is directly connected to the input port of IRU 100-3, and so on, the output port of IRU 100-n is directly connected to the APS.

The IRU 100-1 receives an interrupt request (e.g., an interrupt message or an interrupt signal) from external hardware via its input port, and routes and converts the interrupt request into an interrupt instruction (in this embodiment, a message instruction). The message instructions output by IRU 100-1 serve as inputs to IRU 100-2 in cascade with IRU 100-1. The IRU 100-2 receives from the IRU 100-1 through its input port (in this example, a message input channel) a message instruction output from the IRU 100-1 as its interrupt request and performs route conversion thereon, thereby outputting an interrupt instruction (in this example, a message instruction) from the IRU 100-2. And so on until the IRU 100-n outputs an interrupt instruction (which may be a signal instruction or a message instruction) to the APS via its output port.

In the example shown in FIG. 6, in cascade mode, all of the remaining IRUs 100-2 through 100-n, except IRU 100-1, which is directly connected to external hardware, are configured to receive interrupt messages serially from the message input channel; except for the IRU-n directly connected to the APS, the rest of the IRUs are configured to serially output message instructions from the message output channel. The interrupt request input from the external hardware to the cascaded IRU may be either or both of an interrupt message and an interrupt signal, and the interrupt instruction output from the cascaded IRU to the APS may be either or both of a signal instruction or a message instruction, as a whole.

In the cascade mode, the number of APSs 300 may be one or more. It should be noted that, the MCU 200 is the only management unit in the SOC, and multiple cascaded IRUs can be controlled by the same MCU 200.

The present application further provides an intelligent device comprising an SOC according to the above-described embodiments. Illustratively, the smart device may be an automobile. Accordingly, the plurality of APS isolated from each other may be, for example, a cabin system, a vehicle control system, a driving assistance system (e.g., ADAS/ADS system), etc., and respectively correspond to functions of human-machine interaction, vehicle control, automatic driving assistance, etc. Each system is directly in hardware butt joint with the interrupt controller, and the interrupt instruction is directly output to each functional application subsystem through an output port connected with each functional application subsystem.

The present application further provides an interrupt processing method, which can be applied to the interrupt controller described in the foregoing embodiment. As shown in fig. 7, the interrupt processing method includes steps S710 to S750 shown in fig. 7.

In S710, an interrupt request from external hardware is received. For example, the interrupt controller receives an interrupt request from external hardware through an input port. In S730, the interrupt request is bypassed or routed and converted into an interrupt instruction. In S750, the interrupt instruction is output to one or more of the plurality of mutually isolated functional application subsystems. And clearing the interrupt source after the functional subsystem completes the relevant interrupt processing.

In one embodiment, receiving an interrupt request from external hardware comprises: receiving an interrupt signal as the interrupt request from one input signal line or from a plurality of input signal lines in parallel; and/or serially receiving an interrupt message as the interrupt request from a message input channel.

In an embodiment, outputting the interrupt instruction to one or more of the plurality of functional application subsystems that are isolated from each other comprises: and outputting a signal instruction as the interrupt instruction to a specified one or more of the functional application subsystems through an output signal line, and/or outputting a message instruction as the interrupt instruction to a specified one or more of the functional application subsystems through a message output channel.

In one embodiment, bypassing the interrupt request or routing and converting the interrupt request into an interrupt instruction comprises: in the case of receiving the interrupt signal, when a disable bypass instruction from the management control processor is not received, bypassing the interrupt signal by default without converting into an interrupt instruction, and when a disable bypass instruction from the management control processor is received, routing and converting the interrupt signal into the interrupt instruction; in case the interrupt message is received, the interrupt message is routed and converted into the interrupt instruction.

In one embodiment, the interrupt processing method further includes: setting an enable state and a parameter of the input signal line, an enable state and a parameter of the output signal line, enable states of the message input channel and the message output channel, and a trigger mode of the interrupt controller based on control of the management control processor.

In one embodiment, the interrupt processing method further includes: according to the control of the management control processor, the message instructions are put into the cache modules in the plurality of message output channels with the appointed priority order and are sequentially output to the plurality of functional application subsystems according to the priority order.

In one embodiment, the interrupt processing method further includes: and counting the interrupt request and the interrupt instruction to generate statistical information, and interacting the statistical information with one or more functional application subsystems.

In the present application, the features described in the embodiments of the interrupt controller may be applied to an interrupt processing method. For the specific definition of the interrupt processing method, reference may be made to the above definition of the interrupt controller, which is not described herein again.

According to the interrupt controller, the system on chip and the intelligent device, the interrupt instruction output by the interrupt controller is directly connected with the plurality of mutually isolated functional application subsystems in a butt joint mode through hardware, so that the control and the use of the interrupt can be separated from each other, and the classification and role separation management of the system is realized. In addition, the interrupt controller is compatible with signal-based and message-based input and output, can be compatible with current mainstream signal-based interrupt, and simultaneously realizes message-based interrupt, thereby realizing personalized and customized dynamic configuration of the system according to the actual requirements of the functional application subsystem, and improving the adaptability and safety of the whole system.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent should be subject to the appended claims.

Claims (11)

1. An interrupt controller controlled by the management control processor and comprising:

an input port configured to receive an interrupt request from external hardware;

an interrupt routing module configured to bypass output of the interrupt request or route and convert the interrupt request into an interrupt instruction; and

an output port configured to output the interrupt instruction to one or more of a plurality of functional application subsystems that are isolated from each other.

2. The interrupt controller of claim 1, wherein the input port comprises an input signal line and a message input channel;

wherein the input port is configured to: receiving an interrupt signal as the interrupt request from one input signal line or from a plurality of input signal lines in parallel; and/or serially receiving an interrupt message as the interrupt request from the message input channel.

3. The interrupt controller of claim 1 or 2, wherein the output port comprises an output signal line and a message output channel;

wherein the output port is configured to output a signal instruction as the interrupt instruction to a specified one or more of the functional application subsystems through the output signal line and/or output a message instruction as the interrupt instruction to a specified one or more of the functional application subsystems through the message output channel.

4. The interrupt controller of claim 2, wherein the interrupt routing module is configured to:

in a case where the interrupt signal is received, when a disable bypass instruction is not received from the management control processor, bypassing the interrupt signal by default without converting to an interrupt instruction; when a bypass disabling instruction is received from the management control processor, routing the interrupt signal and converting the interrupt signal into the interrupt instruction;

routing and converting the interrupt message into the interrupt instruction in case the interrupt message is received.

5. An interrupt controller as claimed in claim 3, wherein the interrupt routing module is further configured to set the enable state and parameters of the input signal line, the enable state and parameters of the output signal line, the enable states of the message input channel and the message output channel, and the trigger mode of the interrupt controller, based on control by the management control processor.

6. The interrupt controller of claim 3, further comprising a cache module included in the message output channel;

and according to the control of the management control processor, the message instruction is put into a cache module in a plurality of message output channels with assigned priority orders and is sequentially output to a plurality of function application subsystems according to the priority orders.

7. The interrupt controller of claim 1, further comprising a statistics module, as an interface to the functional application subsystem, configured to perform statistics on the interrupt requests and the interrupt instructions.

8. A system on a chip, comprising:

an interrupt controller according to any one of claims 1 to 7;

the management control processor is configured to control the interrupt controller; and

the plurality of mutually isolated functional application subsystems are configured to receive the interrupt instruction according to the priority order of the interrupt instruction so as to realize the functions of terminal application.

9. The system on a chip of claim 8, comprising a plurality of said interrupt controllers cascaded with one another, said interrupt request being routed and translated into said interrupt instruction via a plurality of said interrupt controllers.

10. Smart device comprising a system on chip according to claim 8 or 9.

11. The interrupt processing method is applied to an interrupt controller and comprises the following steps based on the control of a management control processor:

receiving an interrupt request from external hardware;

bypassing the interrupt request for output, or routing and converting the interrupt request into an interrupt instruction; and

outputting the interrupt instruction to one or more of the plurality of functional application subsystems that are isolated from each other.

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