CN115687237A

CN115687237A - Method, apparatus, medium, and program for drawing pipeline CPU architecture diagram

Info

Publication number: CN115687237A
Application number: CN202111234049.XA
Authority: CN
Inventors: 陈鑫; 汪威
Original assignee: Shenzhen Injoinic Technology Co Ltd
Current assignee: Shenzhen Injoinic Technology Co Ltd
Priority date: 2021-07-22
Filing date: 2021-07-22
Publication date: 2023-02-03
Also published as: WO2023000938A1; CN113282219A; CN113282219B

Abstract

The application provides a method for drawing a pipeline CPU architecture diagram and a terminal device, wherein the method is applied to the terminal device and comprises the following steps: acquiring a module selection instruction input by a user through terminal equipment, and determining a CPU initial frame in a working area according to the module selection instruction; acquiring an instruction set selection instruction input by a user through terminal equipment, and determining the CPU instruction set in the working area according to the instruction set selection instruction; acquiring a combined instruction input by a user through terminal equipment, combining a target instruction in the CPU instruction set with the CPU initial frame according to the combined instruction, and generating the module component in the working area according to a combined result; and acquiring a finishing instruction input by a user through the terminal equipment, and generating a CPU architecture diagram according to the module component and the CPU initial framework. According to the method, the drawing method of the assembly line CPU architecture diagram is software-based, so that the visibility and convenience of drawing are improved.

Description

Method, apparatus, medium, and program for drawing pipeline CPU architecture diagram

Technical Field

The present application relates to the field of CPU design, and in particular, to a method, an apparatus, a medium, and a program for drawing an architecture diagram of a pipeline CPU.

Background

At present, CPU teaching design methods, systems and equipment based on a pipeline structure are few, most CPU teaching design methods, systems and equipment are carried out by adopting a single-cycle or multi-cycle CPU based on a state machine, so that the characteristics of the pipeline CPU structure cannot be reflected well, and engineering technicians, students and the like are not facilitated to master the drawing method of the architecture diagram of the pipeline CPU quickly.

Thus, the prior art remains to be improved.

Disclosure of Invention

In view of the defects of the prior art, the present application aims to provide a drawing method of an assembly line CPU architecture diagram and a terminal device, and aims to solve the problem that the existing CPU teaching design method is not beneficial to engineers, students, and the like to grasp quickly.

In order to achieve the purpose, the following technical scheme is adopted in the application:

in a first aspect, the present application provides a method for drawing a pipeline CPU architecture diagram, which is applied to a terminal device, and the method includes:

acquiring a module selection instruction input by a user through the terminal equipment, and determining a CPU initial frame in a working area according to the module selection instruction, wherein the working area is used for displaying a drawing control, and the drawing control comprises a CPU instruction set, a target instruction and a module component;

acquiring an instruction set selection instruction input by a user through the terminal equipment, and determining the CPU instruction set in the working area according to the instruction set selection instruction, wherein the CPU instruction set comprises one or more target instructions which are used for realizing preset operation;

acquiring a combined instruction input by a user through the terminal equipment, combining the target instruction in the CPU instruction set with the CPU initial frame according to the combined instruction, and generating the module component in the working area according to a combined result, wherein the module component is used for realizing the preset operation of the target instruction;

and acquiring a finishing instruction input by a user through the terminal equipment, and generating a CPU architecture diagram according to the module component and the CPU initial frame.

Therefore, the problem that in the prior art, engineering technicians, students and the like are not favorable for rapidly mastering the drawing method of the assembly line CPU architecture diagram is solved by converting the drawing method of the assembly line CPU architecture diagram into software, and the visibility and the convenience of drawing are improved.

In a second aspect, the present application further provides a terminal device, including: a processor and a memory; the memory has stored thereon a computer readable program executable by the processor; the processor, when executing the computer readable program, implements the steps in the method as described above.

In a third aspect, the present application also provides a computer readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the steps in the method as described above.

Drawings

Fig. 1 is a schematic structural diagram of a terminal device provided in the present application;

FIG. 2 is a diagram of a CPU architecture provided herein;

FIG. 3 is a block diagram of a work area provided herein;

FIG. 4a is an instruction data flow diagram of a mov instruction provided herein;

FIG. 4b is an instruction dataflow diagram of an lui instruction provided herein;

FIG. 4c is an instruction data flow diagram of an inc instruction or a dec instruction provided herein;

FIG. 4d is an instruction data flow diagram of an ori instruction provided herein;

FIG. 4e is a diagram of an instruction data flow for a jmp instruction as provided herein;

FIG. 4f is an instruction data flow diagram of a beq instruction provided herein;

FIG. 4g is an instruction data flow diagram of an in instruction provided herein;

FIG. 4h is an instruction dataflow diagram of an out instruction as provided by the present application;

FIG. 5 is a block diagram of a CPU architecture provided herein;

fig. 6 is a flowchart of a method for drawing a pipeline CPU architecture diagram provided in the present application.

Detailed Description

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the foregoing drawings are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

In the present application, "at least one" means one or more, and a plurality means two or more. In the present application and/or, an association relationship of an association object is described, which means that there may be three relationships, for example, a and/or B, which may mean: a exists singly, A and B exist simultaneously, and B exists singly, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein each of a, b, c may itself be an element or a set comprising one or more elements.

It should be noted that, in the embodiments of the present application, the term "equal to" may be used in conjunction with more than, and is applicable to the technical solution adopted when more than, and may also be used in conjunction with less than, and is applicable to the technical solution adopted when less than, and it should be noted that when equal to or more than, it is not used in conjunction with less than; when the ratio is equal to or less than the combined ratio, the ratio is not greater than the combined ratio. In the embodiments of the present application, "of", "corresponding" and "corresponding" may be sometimes used in combination, and it should be noted that the intended meaning is consistent when the difference is not emphasized.

First, partial terms referred to in the embodiments of the present application are explained so as to be easily understood by those skilled in the art.

1. A CPU. The Central Processing Unit (CPU) is the core device of the computer hardware, and the three major core devices of the electronic computer are the CPU, the internal memory, and the input/output device. The CPU is a final execution unit for information processing and program operation, which is an operation and control core of the computer system. Is one of the main devices of electronic computers, the core accessory in the computer. Its function is mainly to interpret computer instructions and to process data in computer software. The CPU is a core component of the computer responsible for reading, decoding, and executing instructions. The central processor mainly comprises two parts, namely a controller and an arithmetic unit, and also comprises a cache memory and a data and control bus for realizing the communication between the cache memory and the arithmetic unit. The functions of the central processing unit are mainly processing instructions, executing operations, controlling time and processing data. The current commercial CPUs or Microcontrollers (MCU) almost exclusively use a pipeline architecture.

2. A work area. The work area generally includes a toolbar, an editing area, a material area, and other areas. The toolbar is an area which is integrated with various tools in a software program and is convenient for a user to use; the editing area is an area for editing the CPU architecture diagram by using each command, and the document can be moved, added, deleted, modified and the like in the area; the material area is an area for displaying various drawing controls. In the present application, the editing area is a structure display area; the material area comprises an instruction set area and a module component area; the toolbar defaults to setting conventional tools required for drawing, including but not limited to a moving tool, a font tool, a paragraph tool, an editing tool, etc.; other areas include, but are not limited to, a confirmation area, an information display area, and the like.

3. An instruction data flow graph. An instruction dataflow graph is a flow diagram that embodies the flow of a series of data in the system that is caused by an instruction. In the present application, the specific data flow of the data call required to complete the preset function of the target instruction is referred to. At present, CPU teaching design methods, systems and equipment based on a pipeline structure are few, most of the CPU teaching design methods, systems and equipment are performed by adopting a single-cycle or multi-cycle CPU based on a state machine, so that the characteristics of the pipeline CPU structure cannot be reflected well, engineering technicians, students and the like cannot conveniently master the drawing method of the architecture diagram of the pipeline CPU, and a novice cannot be guided to be familiar with the overall architecture of the CPU quickly.

In order to solve the problems, the application provides a drawing method of an assembly line CPU architecture diagram, and solves the problems that in the prior art, engineering technicians, students and the like are not favorable for quickly mastering the drawing method of the assembly line CPU architecture diagram, and a novice cannot be guided to quickly become familiar with the overall architecture of a CPU.

The following describes an information query method provided by the present application with specific embodiments.

As shown in fig. 3 and fig. 6, the present application provides a method for drawing a pipeline CPU architecture diagram, which is applied to a terminal device, and the method includes:

step 101, obtaining a module selection instruction input by a user through the terminal device, and determining a CPU initial frame in a working area 10 according to the module selection instruction.

For example, the user may be a person who uses a terminal device to draw a pipeline CPU architecture diagram, the user may input the module selection instruction to the terminal device through an external device, and a processor in the terminal device determines the CPU initial framework in the work area 10 according to the module selection instruction.

Specifically, the specific operation is different according to different input modes of the module selection instruction, and the following examples are given.

In the mode 1, the module selection instruction may be a single-click operation triggered by an external device or a touch screen, and the CPU initial frame is determined by clicking a corresponding module.

In the mode 2, the module selection instruction may also be a dragging operation triggered by a mouse or a touch screen, so as to drag the CPU initial frame to the working area 10, so as to determine the CPU initial frame.

The working area 10 is used for displaying drawing controls, and the drawing controls include a CPU instruction set, a target instruction, and a module component.

In one possible example, after the step 101, the method further comprises:

201. and acquiring a port setting instruction input by the user through the terminal equipment, and configuring the port definition of the CPU initial architecture according to the port setting instruction.

For example, referring to fig. 5, the initial architecture of the CPU only includes the initial module, and the corresponding port definitions need to be configured for the module, for example, an input port, an output port, a clock port, and the like are configured. Attributes of a port include, but are not limited to: 1. a port name; 2. data directionality: input/output/bi-directional; 3. the data bit width. And obtaining a CPU structural block diagram based on the CPU initial architecture, the port definition and the module component. The CPU structural block diagram includes a CPU main body (CPU), the CPU main body is configured with an input Port (Instr), a reset Port (Rst _ n), a data input Port (Port _ in), a data output Port (Port _ out), an instruction memory enable Port (Rom _ e), a clock input Port (Clk), and an address output Port (Add), and the CPU main body further includes a control module 110 and a data path module 111. And the data path module and the Control module perform data interaction through a Control signal (Control _ signal) and an instruction operation code (Instr _ op) respectively.

In one possible example, continuing to refer to fig. 3, the working area 10 includes a configuration display area 11, an instruction set area 12, a module component area 13, an information display area 14, and a confirmation area 15; the structure display area 11 is configured to display the CPU initial architecture, the instruction set area 12 is configured to display all instructions in the instruction set, the module component area 13 is configured to display the module components, the information display area 14 is configured to prompt an operation to be performed in the current step, and the confirmation area 15 is configured to input the completion instruction.

In one possible example, the step 101 includes:

step 1011, obtaining a first module selection instruction input by the user through the terminal device, and determining the control module 110 in the structure display area 11.

For example, the first selection instruction may be a single-click operation triggered by an external device or a touch screen, and the control module 110 is added to the structure display area 11 by clicking the control module 110; the first selection instruction may also be a drag operation triggered by a mouse or a touch screen, and the control module 110 is dragged to the structure display area by dragging the control module 110.

Step 1012, acquiring a second module selection instruction input by the user through the terminal device, and determining the data path module 111 in the structure display area 11.

For example, the first selection instruction may be a single-click operation triggered by an external device or a touch screen, and the control module 110 is added to the structure display area 11 by clicking the data path module 111; the first selection instruction may also be a dragging operation triggered by a mouse or a touch screen, and the data path module 111 is dragged to the structure display area by dragging the data path module 111.

Step 1013, composing the CPU initial frame according to the control module 110 and the datapath module 111.

Illustratively, the control module 110 is connected to the data path module 111 to form the initial architecture of the CPU.

In this example, it can be seen that a drawing visualization operation is implemented, and a corresponding module is placed in the structure display area 11 by clicking or dragging to form an initial frame of the CPU.

And 102, acquiring an instruction set selection instruction input by a user through the terminal equipment, and determining the CPU instruction set in the working area 10 according to the instruction set selection instruction.

For example, the user may input the instruction set selection instruction to the terminal device through an external device, after receiving the instruction set selection instruction, the terminal device determines the CPU instruction set shown in table 1 according to the instruction set selection instruction, and sets an instruction width and a data width of a target instruction in the CPU instruction set, where the instruction width is used to limit a bit width of the target instruction, and the data width is used to limit a bit width of data. It will be appreciated that the CPU instruction set may be customized and is not limited to the target instructions in table 1.

The CPU instruction set comprises one or more target instructions, and the target instructions are used for realizing preset operations.

Specifically, the input mode of the selected instruction according to the instruction set is different, and the specific operation is also different, which will be described below by way of example.

In the mode 1, the instruction set selection instruction may be a single-click operation triggered by an external device or a touch screen, and a corresponding target instruction is clicked, added to the CPU instruction set, and displayed in the work area 10.

In the mode 2, the instruction set selection instruction may also be a drag operation triggered by a mouse or a touch screen, so as to drag a target instruction to the working area 10, so as to determine the CPU instruction set.

TABLE 1CPU instruction set

103, acquiring a combined instruction input by a user through the terminal device, combining the target instruction in the CPU instruction set with the CPU initial frame according to the combined instruction, and generating the module component in the working area 10 according to a combined result.

For example, the user may input the combination instruction to the terminal device through an external device, and after receiving the combination instruction, the terminal device combines the CPU initial frame with the target instruction according to the combination instruction.

The module component is used for realizing preset operation of the target instruction.

Specifically, the specific operation is different according to the input mode of the combination instruction, and the following description will be given by way of example.

Mode 1, the combined instruction may be a single-click operation triggered by an external device or a touch screen, and the target instruction is added to the CPU initial frame by clicking a corresponding target instruction; or a series of combined operations formed by multiple single click operations, and finally realizing the function of the combined instruction, for example, clicking a CPU initial frame, popping up a target instruction selection interface, selecting a corresponding target instruction in the target instruction selection interface, adding the target instruction into the CPU initial frame, and completing the input of the combined instruction.

In the mode 2, the combined instruction may also be a drag operation triggered by a mouse or a touch screen, and the target instructions are directly dragged one by one into the CPU initial frame to add the target instruction into the CPU initial frame, so as to complete the input of the combined instruction.

Further, after the input of the combination instruction is completed, the terminal device screens out the module components of the actual circuit module required for realizing the target instruction according to the combination instruction, and displays the module components in the working area 10. It is understood that there may be one or more module components that implement the same target instruction, and are not limited to the only one. As can be seen, the present example enables automated screening of module components.

In one possible example, the step 103 includes:

step 1031, obtaining the target instruction in the CPU instruction set from the instruction set region 12 according to the combined instruction, and combining the target instruction with the control module 110.

Illustratively, the corresponding target instructions in the CPU instruction set are combined with the control module 110 according to the combination instruction. The combination operation specifically comprises the following steps: and obtaining module components required by the control module 110 to execute the target instruction according to a preset rule, and generating a combined result.

Step 1032, generating the module component in the module component area 13 according to the combination result.

The module component is specifically configured to form the data path module 111 and implement the function of the target instruction.

For example, the module component is generated in the module component area 13 according to the combination result, and one or more module components that achieve the same function may be included, so that the user can freely select the module components.

And 104, acquiring a finishing instruction input by a user through the terminal equipment, and generating a CPU architecture diagram according to the module component and the CPU initial frame.

For example, referring to fig. 2, after the module components are screened out, a user inputs a completion instruction, and after the terminal device receives the completion instruction, the CPU architecture diagram shown in fig. 2 is generated according to the module components and the CPU initial framework.

As shown in fig. 2, the CPU architecture diagram includes a control module 110, a data path module 111, and a memory module (Rom), where the control module 110 is a pure combinational logic circuit, and the data path module 111 includes a combinational logic circuit and a sequential logic circuit. The combinational logic circuit includes a data selector (MUX), an Arithmetic Logic Unit (ALU), a subtractor (Sub), and a comparator (Cmp _ zero). The sequential logic circuit includes a Program Counter (PC), a register set (Regs), an Output register (Output _ reg), and an Add _ reg (address register).

Specifically, the specific operation is different according to the input mode of the completion instruction, and the following description will be given by way of example.

In the mode 1, the completion instruction can be a single-click operation triggered by external equipment or a touch screen, and the completion instruction is input by clicking a confirmation control or a confirmation button; or the completing instruction is a series of combined operations consisting of a plurality of one-click operations.

In the mode 2, the completion instruction may be a drag operation triggered by a mouse or a touch screen, and the like, and the corresponding module component is selected to be dragged to the work area 10, so as to form a CPU architecture diagram.

In mode 3, the completing instruction may also be a combined operation consisting of one or more single-click operations and one or more drag operations, so as to implement the input of the completing instruction. For example, dragging a module component to the work area 10 and then automatically generating a CPU architecture diagram by clicking a confirmation control or a confirmation button.

Further, in the process of automatically generating the CPU architecture diagram, wires may be automatically generated according to each module component and the CPU initial framework and port definition to generate the CPU architecture diagram. For example, by interconnecting interfaces that have the same port number.

In one possible example, after the step 104, the method further comprises:

step 105, or acquiring a component selection instruction input by the user through the terminal device, and adding the module component into the data path module 111 to form the data path module 111, so as to obtain the CPU architecture diagram.

For example, the component selection instruction may be a single-click operation triggered by an external device or a touch screen through a single-click operation triggered by the device or the touch screen, may be a series of combined operations formed by a plurality of single-click operations, may be a drag operation triggered by a mouse or the touch screen, and may be a combined operation formed by one or more single-click operations and one or more drag operations. By triggering the component selection instruction, the corresponding module components are added into the data path module 111 one by one, and finally, a complete data path module 111 is formed, and finally, the control module 110 and the data path module 111 form a CPU architecture diagram.

In one possible example, after the step 104, the method further comprises:

301, acquiring a simulation instruction input by a user through the terminal device, and simulating the CPU architecture diagram.

For example, after the CPU architecture diagram is obtained, simulation is required to determine whether the CPU architecture diagram can accurately implement a corresponding function, so that a simulation function is set, a simulation instruction input by a user through the terminal device is obtained, and a simulation mode is entered, so that the user can perform a corresponding simulation operation.

In one possible example, after the step 301, the method further comprises:

step 302, a first instruction input by a user based on the CPU instruction set is obtained, and the CPU architecture diagram executes a corresponding operation according to the first instruction, so as to obtain an execution result.

For example, a first instruction is input to select a first target instruction in the CPU instruction set, so that the CPU architecture diagram executes the first target instruction, and an execution result after the CPU architecture diagram executes the first target instruction is obtained.

And 303, if the execution result is correct, prompting that the simulation is successful.

In an example, the execution result is compared with a preset result of the target instruction, if the execution result is the same as the preset result, the execution result is judged to be correct, and then the popup prompts that the simulation is successful.

And 304, if the execution result is wrong, reporting the error.

In an example, the execution result is compared with a preset result of the target instruction, if the execution result is different from the preset result of the target instruction, the execution result is judged to be an error, then a popup window is performed to report the error, and error information is displayed, so that a user can check an error source conveniently.

In one possible example, after the step 104, the method further comprises:

step 401, obtaining a mode switching instruction input by a user through the terminal device, and switching to a teaching mode or a normal mode according to the mode switching instruction.

For example, the component selection instruction may be a single-click operation triggered by an external device or a touch screen through a single-click operation triggered by the device or the touch screen, may be a series of combined operations formed by a plurality of single-click operations, may be a drag operation triggered by a mouse or the touch screen, and may be a combined operation formed by one or more single-click operations and one or more drag operations.

Specifically, after the mode switching instruction is acquired, if the current mode is the normal mode, the current working area 10 is converted into the teaching mode according to the mode switching instruction; and if the current work area is the teaching mode, converting the current work area 10 into a normal mode according to the mode switching instruction.

And step 402, when the teaching mode is in, locking the working area 10 which is not involved in the current step, and displaying the operation to be executed and the operation requirement of the current step in the information display area 14.

For example, in the teaching mode, the steps 101 to 104 are sequentially executed, the work area 10 involved in the executed step (i.e., the current step) is in an editable state, and the work area 10 not involved in the executed step is in a locked state. When the corresponding step is executed, the information display area 14 prompts the operation and the operation requirement to be executed in the current step for the current step so as to guide a new person to perform the corresponding operation, so that the new person can be familiar with the drawing process of the CPU architecture diagram quickly, and the mastering speed of the CPU structure is improved.

It is understood that all steps in this application may be performed according to a specific order before and after, and are not limited to steps 101-104.

Step 403, after the current step is completed, unlocking the work area 10 involved in the next step, and displaying the operation and the operation requirement to be executed in the next step in the information display area 14.

For example, after unlocking the work area 10 involved in the next step, the user is instructed to perform the operation and operation requirement related to the next step through the information display area 14, and the area not involved in the next step is locked.

Therefore, in the example, by setting the teaching mode, guidance for drawing the CPU architecture diagram is provided for users such as students and new employees, so that a novice can quickly become familiar with the drawing process of the CPU architecture diagram, and the mastering speed of the novice on the CPU structure is increased.

In one possible example, after the step 104, the method further comprises:

and 501, generating an instruction data flow diagram according to the instruction set and the CPU initial framework.

Illustratively, after the CPU architecture diagram is generated, the instruction dataflow graph can also be synchronously generated. The CPU instruction set may include target instructions as in table 1, as illustrated below with reference to the instruction data flow diagrams of a pair of instructions as shown in fig. 4 a-4 h.

As shown in fig. 4a, an instruction data flow diagram of the mov instruction is shown. The mov instruction transfers the value of the read register corresponding to the rs address to the write register corresponding to the rd address. Specifically, the address of the read register (Raddr) and the address of the write register (Waddr) and the data to be written to the registers (the value of the read register) are given in the first clock cycle, and the data is written to the second register in the second clock cycle.

As shown in FIG. 4b, an instruction data flow diagram for the lui instruction is illustrated. The lui instruction transfers the immediate (bits 0 through 7 of the instruction) into the register corresponding to the rd address. Specifically, the address and immediate (imm) of the write register are given in the first clock cycle, and the immediate is written into the write register in the second clock cycle.

As shown in fig. 4c, the diagram is an instruction data flow diagram of an inc instruction or a dec instruction, and the data flow diagrams of the inc instruction and the dec instruction are the same, except that operations performed in Alu are different. The read address and the write address of the inc instruction or the dec instruction are the same, the register data (Rdata) is read out in the first clock cycle and sent to Alu for operation, and sent to the data input end (Wdata) of the register group (Regs), and the operation result is written into the write register in the second clock cycle.

As shown in FIG. 4d, an instruction data flow diagram of an ori instruction is shown. ori commands give addresses (Raddr) for reading and writing registers (Waddr) in a first clock cycle, send immediate (imm) and register data (Rdata) to Alu together for bitwise OR operation, and write Alu operation results into the registers in a second clock cycle.

As shown in fig. 4e, an instruction data flow diagram of a jmp instruction is shown. The jmp instruction data flow diagram inputs the value (Rdata) of a given register to the address terminal of a program memory (Rom) in the first clock cycle to realize instruction jump, and simultaneously inputs the value (Rdata) of the given register to a Pc module (program counter), and updates the input address when the next clock effective edge comes.

As shown in FIG. 4f, an instruction data flow diagram for the beq instruction is shown. The beq instruction compares the value of the corresponding register with the value of 0 through a Sub module (subtracter) in a first clock cycle, and if the two values are equal, the output value of the Sub module is the current address value plus one, so that the instruction is sequentially executed; if the two are not equal, the Sub module output value is the current address value minus num, so that the instruction jumps, and meanwhile, the Sub module output value is given to a Pc module (program counter) so as to update the address when the next clock cycle arrives.

As shown in FIG. 4g, an instruction data flow diagram for an in instruction is shown. The in instruction gives the address (Waddr) to write the register in the first clock cycle and the data from the input port (port _ in) is written into the corresponding register in the second clock cycle.

As shown in FIG. 4h, an instruction data flow diagram for the out instruction is illustrated. The out instruction gives the address of the read register (Raddr) and reads the data out to the input of the output register (output _ reg) in the first clock cycle, and outputs the data to the port (port _ out) in the second clock cycle.

And 502, generating a CPU structural block diagram according to the module component and the CPU initial framework.

For example, referring to fig. 5, after the CPU architecture diagram is generated, a CPU structure diagram may also be generated synchronously, where the CPU structure diagram is specifically a module structure diagram of the CPU. Since the structural block diagram of the CPU has been described in detail above, it is not described herein again.

In a possible example, before the step 101, the method further includes:

step 601, pre-configuring one or more first templates of the initial architecture of the CPU, and when the module selection instruction is obtained, directly adding the selected first template to the structure display area 11 in the work area 10.

For example, in order to improve the drawing efficiency of the CPU architecture diagram, one or more first templates may be formed and stored in a common CPU initial architecture, and when the first templates are needed, the first templates may be directly added to the structure display area 11 through the module selection instruction. For example, a common CPU two-layer pipeline structure, a common CPU three-layer pipeline structure, or the like may be used as the first template, or other pipeline structures may be provided, which is not limited herein.

In a possible example, before the step 101, the method further includes:

step 701, configuring one or more second templates of the CPU instruction set in advance, and when the instruction set selection instruction is acquired, directly adding the selected second template to the instruction set area 12 in the work area 10.

For example, in order to improve the drawing efficiency of the CPU architecture diagram, a common CPU instruction set may be further formed into one or more second templates and stored, and when the second templates are used, the second templates may be directly added to the structure display area 11 through the instruction set selection instruction.

In summary, the present application provides a method for drawing an architecture diagram of a pipeline CPU and a terminal device, where the method is applied to a terminal device, and the method includes: acquiring a module selection instruction input by a user through the terminal equipment, and determining a CPU initial frame in a working area according to the module selection instruction; acquiring an instruction set selection instruction input by a user through the terminal equipment, and determining the CPU instruction set in the working area according to the instruction set selection instruction; acquiring a combined instruction input by a user through the terminal equipment, combining the target instruction in the CPU instruction set with the CPU initial frame according to the combined instruction, and generating the module component in the working area according to a combined result; and acquiring a finishing instruction input by a user through the terminal equipment, and generating a CPU architecture diagram according to the module component and the CPU initial frame. According to the method, the drawing method of the assembly line CPU architecture diagram is software-based, so that the visibility and convenience of drawing are improved.

The present application also provides a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement the steps in the method described in the above embodiments.

The present application also provides a terminal device 25, as shown in fig. 1, which includes at least one processor (processor) 20; a display screen 21; and a memory (memory) 22, and may further include a communication Interface (Communications Interface) 23 and a bus 24. The processor 20, the display 21, the memory 22 and the communication interface 23 can communicate with each other through the bus 24. The display screen 21 is configured to display a user guidance interface preset in the initial setting mode. The communication interface 23 may transmit information. The processor 20 may call logic instructions in the memory 22 to perform the methods in the embodiments described above.

Furthermore, the logic instructions in the memory 22 may be implemented in software functional units and stored in a computer readable storage medium when sold or used as a stand-alone product.

The memory 22, which is a computer-readable storage medium, may be configured to store a software program, a computer-executable program, such as program instructions or modules corresponding to the methods in the embodiments of the present disclosure. The processor 20 executes the functional application and data processing, i.e. implements the method in the above-described embodiments, by executing the software program, instructions or modules stored in the memory 22.

The memory 22 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device 25, and the like. Further, the memory 22 may include a high speed random access memory and may also include a non-volatile memory. For example, a variety of media that can store program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, may also be transient storage media.

Optionally, as shown in fig. 1, the drawing method of the pipeline CPU architecture diagram is embodied as drawing software, the drawing software is applied to a terminal device, and an interface of the drawing software is displayed through the display screen 21; the specific program of the drawing method of the pipeline CPU architecture diagram is stored by the memory 22 and called by the processor 20. And inputting corresponding instructions to the terminal equipment by a user through external equipment or a touch screen so as to realize corresponding drawing operation. Including but not limited to one or more of a mouse, buttons, keyboard, voice module, etc.

In addition, the specific processes loaded and executed by the storage medium and the instruction processors in the mobile terminal are described in detail in the method, and are not stated herein.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A method for drawing a pipeline CPU architecture diagram is applied to terminal equipment, and the method comprises the following steps:

acquiring a module selection instruction input by a user through the terminal equipment, and determining a CPU initial frame in a working area according to the module selection instruction, wherein the working area is used for displaying a drawing control, and the drawing control comprises a CPU instruction set, a target instruction and/or a module component;

2. The method of claim 1, wherein after the generating a CPU architecture diagram from the module components and the CPU initial framework, the method further comprises:

and acquiring a simulation instruction input by a user through the terminal equipment, and simulating the CPU architecture diagram.

3. The method of claim 2, wherein after the simulating the CPU architecture diagram, the method further comprises:

acquiring a first instruction input by a user based on the CPU instruction set, and executing corresponding operation according to the first instruction by the CPU architecture diagram to obtain an execution result;

if the execution result is correct, prompting that the simulation is successful;

and if the execution result is wrong, reporting the error.

4. The method of any one of claims 1 to 3, wherein the work area comprises a structure display area, an instruction set area, a module component area, an information display area, and a confirmation area; the structure display area is used for displaying the CPU initial architecture, the instruction set area is used for displaying all instructions in the instruction set, the module component area is used for displaying the module components, the information display area is used for prompting the operation to be performed in the current step, and the confirmation area is used for inputting the completion instruction;

the acquiring a module selection instruction input by a user through the terminal device, and determining a CPU initial frame according to the module selection instruction comprises the following steps:

acquiring a first module selection instruction input by a user through the terminal equipment, and determining a control module in the structure display area;

acquiring a second module selection instruction input by a user through the terminal equipment, and determining a data path module in the structure display area;

and forming the CPU initial frame according to the control module and the data path module.

5. The method of claim 4, wherein combining the target instruction in the CPU instruction set with the CPU initial frame according to the combined instruction, and generating the module component in the working area according to a combined result comprises:

acquiring a target instruction in the CPU instruction set from the instruction set area according to the combined instruction, and combining the target instruction with the control module;

and generating the module component in the module component area according to the combination result, wherein the module component is specifically used for forming the data path module and realizing the function of the target instruction.

6. The method of claim 4, wherein after the generating the CPU architecture diagram from the module components and the CPU initial framework, the method further comprises: and acquiring a component selection instruction input by the user through the terminal equipment, and adding the module component into the data path module to form the data path module so as to obtain the CPU architecture diagram.

7. The method of claim 4, further comprising:

acquiring a mode switching instruction input by a user through the terminal equipment, and switching to a teaching mode or a normal mode according to the mode switching instruction;

when the mobile terminal is in a teaching mode, locking a working area which is not involved in the current step, and displaying the operation to be executed and the operation requirement in the current step in the information display area;

and after the current step is completed, unlocking a work area related to the next step, and displaying the operation and the operation requirement to be executed in the next step in the information display area.

8. The method of any of claims 1 to 7, wherein after generating the CPU architecture diagram from the module components and the CPU initial framework, the method further comprises:

generating an instruction data flow graph according to the instruction set and the CPU initial frame;

and generating a CPU structural block diagram according to the module component and the CPU initial frame.

9. A terminal device, comprising: a processor and a memory; the memory has stored thereon a computer readable program executable by the processor; the processor, when executing the computer readable program, implements the method of any of claims 1-8.

10. A computer readable storage medium or computer program product, wherein the computer readable storage medium stores one or more programs which are executable by one or more processors to implement the method of any one of claims 1 to 8, or the computer program product is for implementing the method of any one of claims 1 to 8.