CN109683962B - Method and device for modeling instruction set simulator assembly line - Google Patents
Method and device for modeling instruction set simulator assembly line Download PDFInfo
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- CN109683962B CN109683962B CN201710971527.2A CN201710971527A CN109683962B CN 109683962 B CN109683962 B CN 109683962B CN 201710971527 A CN201710971527 A CN 201710971527A CN 109683962 B CN109683962 B CN 109683962B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
Abstract
A method of instruction set simulator pipeline modeling, comprising: constructing the pipeline into a two-dimensional structure array, wherein n is the number of the pipelines, and m is the maximum depth of all the pipelines; defining a pointing mark for each running level, wherein the pointing mark points to corresponding running data according to the assigned value; and each clock cycle, the new flow data covers the flow data flowing out of the pipeline, and the value of the pointing mark of each flow level is modified correspondingly. An apparatus for pipeline modeling of an instruction set simulator. The method reduces the copying times of the array data, improves the efficiency and improves the user experience.
Description
Technical Field
The present disclosure relates to the field of simulator design modeling, and in particular, but not exclusively, to a method and apparatus for instruction set simulator pipeline modeling.
Background
In processor architecture and hardware design, an Instruction Set Simulator (ISS) refers to a model of the cycle accuracy level of a processor, typically implemented in a high-level software language such as C/c++, which simulates the hardware units of the processor, including instruction fetch units, decode units, execution units, pipelines, instruction memories, data memories, internal buses, data paths, peripherals, and so forth. The method is matched with the real hardware design to achieve the cycle accuracy level, is mainly used for RTL (Register Transfer Level, register conversion stage circuit) collaborative verification, software development and debugging, processor architecture and performance evaluation and the like, and is an important component of any processor design and development.
The pipeline is used as a core part of the design of the processor, is a unit which is most actively operated in the processor, and the modeling of the pipeline is the most important part in the design of the ISS, so that the operation efficiency and the performance of the ISS are directly influenced, and particularly for a very long instruction word (Very Long Instruction Word, VLIW) processor, the multi-instruction concurrency is supported, the pipeline design is generally longer, and the pipeline design is more complicated.
First, a method for implementing a pipeline in a hardware circuit is described, and as shown in fig. 1, a VLIW processor generally supports multiple instruction parallelism and has multiple pipelines (pipelines). Each pipeline typically has a multi-stage pipeline stage (also called pipeline depth), here n pipelines are assumed, each pipeline having m stages (typically the pipeline depth m of different pipelines is different, denoted by m1, m2, m3, …, mn). Each stage typically contains 2 registers, one for each:
1) valid: the instruction valid register, if 1, indicates that the instruction on this pipeline stage is valid.
2) instrucing: the instruction content and the data length are related to a specific instruction set architecture, and can be 16, 32 or 64 bits, etc., when the valid is 1, the decoding unit or the executing unit can fetch the corresponding field for analysis and execution. The register contents are flushed from the current stage to the next stage of pipeline at each clock cycle, as shown in FIG. 1, until the end of the pipeline.
If modeling is completely implemented according to the hardware implementation mode, the implementation method is as follows:
1. the pipeline information of each stage is defined as a structure body, and each structure body contains 2 necessary registers and can also contain other information refreshed along with the pipeline, for example, some instructions are decoded in the pipeline stage1, but the decoded information is not used immediately, but is used when the pipeline flows to a certain stage. This is relevant to the pipeline design of a particular processor, particularly one with a deeper pipeline depth, so that the architecture may contain multiple variables representing information of the first order of the pipeline.
2. Also, since each pipeline may contain a different number of levels, each pipeline may be modeled as an array of level structures, containing k=m1+m2+ … mn level structures.
3. After the pipeline model is built, hardware behaviors are simulated, data of each pipeline and pipeline stages are refreshed every clock cycle, a first-stage pipeline information structure body is copied to a second-stage pipeline information structure body, and the like, a last-stage instruction is executed completely, the first-stage instruction flows out of the pipeline, the first-stage instruction is distributed from an instruction cache (Instruction Buffer, IB for short), and whether a valid instruction is controlled by an IB_valid signal or not is judged. Thus, the analog clock cycle of each ISS needs to make at most K copies of the data of the pipeline information structure, and the operation efficiency is low, and the above process is shown in fig. 2.
Disclosure of Invention
The embodiment of the disclosure provides a method and a device for modeling an instruction set simulator pipeline, which are used for reducing the copying times of array data and improving the efficiency.
A method of instruction set simulator pipeline modeling, comprising:
constructing the pipeline into a two-dimensional structure array, wherein n is the number of the pipelines, and m is the maximum depth of all the pipelines;
defining a pointing mark for each running level, wherein the pointing mark points to corresponding running data according to the assigned value;
and each clock cycle, the new flow data covers the flow data flowing out of the pipeline, and the value of the pointing mark of each flow level is modified correspondingly.
Optionally, after defining a pointing mark for each level, the method further includes:
and sequentially assigning the pointing marks to 0 to m-1 according to the order of the running water steps.
Optionally, the modifying the value of the pointing flag of each level accordingly includes:
m-1 is assigned to the index of the running level whose value is 0 at this time, and the values of the index of the other running levels are subtracted by 1.
Optionally, the modifying the value of the pointing flag of each level accordingly includes:
and assigning the value of the running level of the new running data to a first pointing mark, and subtracting 1 from the values of the pointing marks corresponding to other running levels.
An apparatus for instruction set simulator pipeline modeling, comprising:
the construction module is used for constructing the pipeline into a two-dimensional structural body array, wherein n is the number of the pipelines, and m is the maximum depth of the running steps of all the pipelines;
the definition module is used for defining a pointing mark for each running level, and the pointing mark points to corresponding running data according to the assigned value;
and the processing module is used for covering the flow data flowing out of the pipeline by the new flow content in each clock period and correspondingly modifying the value of the pointing mark of each flow level.
Optionally, the defining module is further configured to, after defining a pointing flag for each running level: and sequentially assigning the pointing marks to 0 to m-1 according to the order of the running water steps.
Optionally, the processing module modifies the value of the pointing flag of each running water level accordingly, including: m-1 is assigned to the index of the running level whose value is 0 at this time, and the values of the index of the other running levels are subtracted by 1.
Optionally, the processing module modifies the value of the pointing flag of each running water level accordingly, including: and assigning the value of the running water level of the new running water content to a first pointing sign, and subtracting 1 from the values of the pointing signs corresponding to other running water levels.
An apparatus for instruction set simulator pipeline modeling, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor when executing the program performs the steps of:
constructing the pipeline into a two-dimensional structure array, wherein n is the number of the pipelines, and m is the maximum depth of the running steps of all the pipelines;
defining a pointing mark for each running level, wherein the pointing mark points to corresponding running data according to the assigned value;
and each clock cycle, the new flow data covers the flow data flowing out of the pipeline, and the value of the pointing mark of each flow level is modified correspondingly.
An instruction set simulator comprising the above device
In summary, the embodiments of the present disclosure provide a method and apparatus for pipeline modeling of an instruction set simulator, which reduce the number of copies of array data, improve the efficiency, and improve the user experience.
Drawings
FIG. 1 is a schematic diagram of a related art hardware implemented pipeline unit;
FIG. 2 is a schematic diagram of pipeline flush modeling of related art fully simulated hardware;
FIG. 3 is a flow chart of a method of instruction set simulator pipeline modeling in accordance with an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of pipeline flush modeling of an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of an apparatus for instruction set simulator pipeline modeling in accordance with an embodiment of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be arbitrarily combined with each other.
FIG. 3 is a flow chart of a method of instruction set simulator pipeline modeling according to an embodiment of the present disclosure, as shown in FIG. 3, the method of the present embodiment includes the steps of:
step 11, constructing the pipeline into a two-dimensional structure array, wherein n is the number of the pipelines, and m is the maximum depth of all the pipelines;
this simplifies the design.
Step 12, defining a pointing mark for each running water level, wherein the pointing mark points to corresponding running water content according to the assigned value;
and 13, each clock cycle, the new flow content covers the flow content flowing out of the pipeline, and the value of the pointing mark of each flow level is correspondingly modified.
In an embodiment, said modifying the value of the pointing flag of each step accordingly includes:
and assigning the value of the running water level of the new running water content to a first pointing sign, and subtracting 1 from the values of the pointing signs corresponding to other running water levels.
In this embodiment, when the pipeline is refreshed in each clock cycle, only the pointing flag needs to be updated to point to the new pipeline content, and the refresh pipeline content does not need to be copied between the stages of the pipeline.
The method of the embodiment of the disclosure greatly reduces the copying times of the array data, and only needs to refresh a new instruction, namely n times of structure data copying. The operation efficiency of the ISS is improved, through practical verification, the operation efficiency of the ISS assembly line can be improved by 90%, the ISS arrangement operation efficiency is improved by 15%, the simulation operation of large-scale software is improved greatly, the simulation time is shortened, and the user experience is improved.
The method of the embodiment solves the problem of lower modeling operation efficiency of the pipeline of the periodic level instruction set simulator in the existing processor design, and the method efficiently simulates the behavior of the processor pipeline from the software perspective, and greatly improves the efficiency compared with the method for completely simulating the logic of hardware.
The method of the present disclosure is described in detail below with reference to a specific example.
Firstly, a whole processor pipeline model is established, the length difference of each pipeline is ignored, and the length difference is uniformly considered according to the maximum pipeline depth m.
Since the execution result of the final instruction is determined by the decode unit and the execution unit, this does not affect the instruction execution result. Abstract into a two-dimensional structural body data pipeline [ n ] [ m ] of n x m.
Next, a pointing flag is defined for each level, for example: stage1, stage2, … … stage < m >, the pipeline contents pointing to a certain stage are fixed.
Wherein, stageM (m=1, 2,3, …, M) is fixedly directed to the mth order flowing water while its value is initialized to M-1.
For example:
stage1 is fixedly pointed to the first-order flowing water, and the value is initialized to 0;
stage2 is fixedly pointed to second-order running water, and the value is initialized to 1;
……
stage < m > is fixedly directed to the mth order pipeline, and the value is initialized to m-1.
Furthermore, each clock cycle, the following operations are only needed to be performed on the running level mark:
judging whether each running water order value is 0, if so, directly assigning the value to be m-1, otherwise, directly subtracting 1.
Meanwhile, the new value incoming stream data is used for replacing the stream data of the outflow pipeline, the new incoming stream data becomes the first-order stream, the stage1 is fixedly pointed to the new value incoming stream data, and the value of the stream level where the new incoming stream data is located is assigned to the stage1.
As shown in fig. 4.
Every cycle, the instruction code of each pipeline stage needs to be referenced when decoding or executing, and the following method is adopted.
For example: the pipeline 1, 3 rd order pipeline data can be directly referenced through the structural pipeline [0] [ stage3 ].
The procedure illustrates:
the state of the pipeline at the nth clock cycle is as follows, assuming m=5, n=1:
| stage mark | Directional running water step | Data of running water level |
| Stage1＝0 | First order running water | pipeline[0][0] |
| Stage2＝1 | Second-order running water | pipeline[0][1] |
| Stage3＝2 | Third order running water | pipeline[0][2] |
| Stage4＝3 | Fourth order running water | pipeline[0][3] |
| Stage5＝4 | Fifth order running water | pipeline[0][4] |
After one clock cycle, the state of the n+1 cycle pipeline is reached:
after the stage is updated, the level pointed by each stage is unchanged, the level content pipeline [0] [4] of the last stage5 of the period N reaches the period N+1, and is covered by the new data in IB, and stage1 points to the new data. Similarly, the data pointed by other stage changes, so that the effect that pipeline data flows according to the pipeline beat is achieved.
FIG. 5 is a schematic diagram of an apparatus for pipeline modeling of an instruction set simulator according to an embodiment of the disclosure, as shown in FIG. 5, the apparatus of the embodiment includes:
the construction module is used for constructing the pipeline into a two-dimensional structural body array, wherein n is the number of the pipelines, and m is the maximum depth of the running steps of all the pipelines;
the definition module is used for defining a pointing mark for each running level, and the pointing mark points to corresponding running data according to the assigned value;
and the processing module is used for covering the flow data flowing out of the pipeline by the new flow content in each clock period and correspondingly modifying the value of the pointing mark of each flow level.
In an embodiment, the defining module is further configured to, after defining a pointing flag for each level: and sequentially assigning the pointing marks to 0 to m-1 according to the order of the running water steps.
In one embodiment, the processing module modifies the value of the index flag of each level accordingly, including: m-1 is assigned to the index of the running level whose value is 0 at this time, and the values of the index of the other running levels are subtracted by 1.
In one embodiment, the processing module modifies the value of the pointing flag of each level accordingly, including: and assigning the value of the running water level of the new running water content to a first pointing sign, and subtracting 1 from the values of the pointing signs corresponding to other running water levels.
The device of the embodiment of the disclosure greatly reduces the copying times of the array data, and only needs to refresh new instructions, namely, n times of structure data copying, improves the operation efficiency of the ISS, and through practical verification, the operation efficiency of the ISS assembly line can be improved by 90%, the ISS arrangement operation efficiency is improved by 15%, and the device has larger efficiency improvement on the simulation operation of large-scale software, shortens the simulation time and improves the user experience.
The present disclosure also provides an apparatus for instruction set simulator pipeline modeling, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor when executing the program performs the steps of:
constructing the pipeline into a two-dimensional structure array, wherein n is the number of the pipelines, and m is the maximum depth of the running steps of all the pipelines;
defining a pointing mark for each running level, wherein the pointing mark points to corresponding running data according to the assigned value;
and each clock cycle, the new flow data covers the flow data flowing out of the pipeline, and the value of the pointing mark of each flow level is modified correspondingly.
The disclosure also provides an instruction set simulator, comprising the device for modeling the instruction set simulator pipeline.
The embodiment of the application also provides a computer readable storage medium which stores computer executable instructions which when executed implement the page processing method.
Those of ordinary skill in the art will appreciate that all or a portion of the steps of the methods described above may be implemented by a program that instructs associated hardware, and the program may be stored on a computer readable storage medium such as a read-only memory, a magnetic or optical disk, etc. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiment may be implemented in the form of hardware, or may be implemented in the form of a software functional module. The present application is not limited to any specific form of combination of hardware and software.
The foregoing is merely a preferred embodiment of the present application, and of course, various other embodiments of the application may be made by those skilled in the art without departing from the spirit and scope of the application, and it is intended that all such modifications and variations be considered as falling within the scope of the appended claims.
Claims (8)
1. A method of instruction set simulator pipeline modeling, comprising:
constructing the pipeline into a two-dimensional structure array, wherein n is the number of the pipelines, and m is the maximum depth of all the pipelines;
defining a pointing mark for each running level, wherein the pointing mark points to corresponding running data according to the assigned value;
each clock cycle, the new stream data covers the stream data flowing out of the pipeline, and the value of the pointing mark of each stream level is correspondingly modified;
the corresponding modification of the value of the pointing mark of each running level comprises the following steps:
and assigning the value of the running level of the new running data to a first pointing mark, and subtracting 1 from the values of the pointing marks corresponding to other running levels.
2. The method of claim 1, wherein: after defining a pointing mark for each running level, the method further comprises:
and sequentially assigning the pointing marks to 0 to m-1 according to the order of the running water steps.
3. The method of claim 2, wherein: the corresponding modification of the value of the pointing mark of each running level comprises the following steps:
m-1 is assigned to the index of the running level whose value is 0 at this time, and the values of the index of the other running levels are subtracted by 1.
4. An apparatus for modeling an instruction set simulator pipeline, comprising:
the construction module is used for constructing the pipeline into a two-dimensional structural body array, wherein n is the number of the pipelines, and m is the maximum depth of the running steps of all the pipelines;
the definition module is used for defining a pointing mark for each running level, and the pointing mark points to corresponding running data according to the assigned value;
the processing module is used for covering the flow data flowing out of the pipeline by the new flow content in each clock period and correspondingly modifying the value of the pointing mark of each flow level;
the processing module correspondingly modifies the value of the pointing mark of each running water level, and comprises the following steps: and assigning the value of the running water level of the new running water content to a first pointing sign, and subtracting 1 from the values of the pointing signs corresponding to other running water levels.
5. The apparatus as claimed in claim 4, wherein:
the definition module is further configured to, after defining a pointing flag for each level,: and sequentially assigning the pointing marks to 0 to m-1 according to the order of the running water steps.
6. The apparatus as claimed in claim 5, wherein:
the processing module correspondingly modifies the value of the pointing mark of each running water level, and comprises the following steps: m-1 is assigned to the index of the running level whose value is 0 at this time, and the values of the index of the other running levels are subtracted by 1.
7. An apparatus for instruction set simulator pipeline modeling, comprising: a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the following steps when executing the program:
constructing the pipeline into a two-dimensional structure array, wherein n is the number of the pipelines, and m is the maximum depth of the running steps of all the pipelines;
defining a pointing mark for each running level, wherein the pointing mark points to corresponding running data according to the assigned value;
each clock cycle, the new stream data covers the stream data flowing out of the pipeline, and the value of the pointing mark of each stream level is correspondingly modified;
the corresponding modification of the value of the pointing mark of each running level comprises the following steps:
and assigning the value of the running level of the new running data to a first pointing mark, and subtracting 1 from the values of the pointing marks corresponding to other running levels.
8. An instruction set simulator comprising the apparatus of any of claims 4-7.
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| CN113515348B (en) * | 2021-07-16 | 2023-11-14 | 江苏师范大学 | Simulator modeling method and device based on opportunity action flow |
| CN115687237A (en) * | 2021-07-22 | 2023-02-03 | 深圳英集芯科技股份有限公司 | Method, apparatus, medium, and program for drawing pipeline CPU architecture diagram |
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