CN115687200A

CN115687200A - PCIe data transmission method and system applied to EPA based on FPGA

Info

Publication number: CN115687200A
Application number: CN202211713522.7A
Authority: CN
Inventors: 谢伟军; 王天林; 金伟江; 劳立辉; 童庆
Original assignee: ZHEJIANG SUPCON RESEARCH CO LTD
Current assignee: ZHEJIANG SUPCON RESEARCH CO LTD
Priority date: 2022-12-30
Filing date: 2022-12-30
Publication date: 2023-02-03
Anticipated expiration: 2042-12-30
Also published as: CN115687200B

Abstract

The invention discloses a PCIe data transmission method and system based on FPGA application to EPA. Aiming at the problem that the transmission efficiency of the existing EPA PCIe transmission efficiency is easily influenced by a processor hardware platform and an operating system to cause the transmission efficiency to be low, the method does not need a processor to intervene in data transmission when the EPA normally works, the FPGA directly accesses a memory of a processor system through the PCIe, the transmission efficiency of the PCIe is greatly improved, the data processing quantity of the EPA is greatly improved, the application scene of the EPA is expanded, any hardware cost is not increased, the PCIe driving design of the processor is simplified, the load of the processor is reduced at the same time, and the processor can process more other system transactions.

Description

PCIe data transmission method and system applied to EPA based on FPGA

Technical Field

The invention belongs to the technical field of high-speed interfaces, and particularly relates to a PCIe data transmission method, system and device applied to EPA based on FPGA and computer equipment.

Background

PCI-Express (peripheral component interconnect Express) is a high-speed serial computer expansion bus standard, EPA (Ethernet for Plant Automation) is a brand-new open real-time Ethernet standard suitable for industrial field equipment, a great deal of mature IT technology is applied to an industrial control system, and a brand-new standard is established for real-time work suitable for the field equipment by utilizing a deterministic communication scheduling strategy of high-efficiency, stable and standard Ethernet and UDP/IP protocols. In a conventional EPA-based PCIe data communication method, for example, in a PCIe communication mode between the EPA and another processor architecture system (e.g., a CPU system or an SOC system), handshaking is performed in an Interrupt (Legacy Interrupt or MSI Interrupt) mode, so as to perform data communication.

In the above conventional interrupt-based PCIe data communication method, when the communication data amount between the EPA system and the processor is small, the real-time performance of processing can be ensured, but when the communication data amount between the EPA system and the processor is large, due to the increase of the number of interrupts, the communication method of data transmission in the interrupt mode is likely to be too frequent due to interrupts, so that it is difficult for the processor and the operating system to respond to the interrupts in time, the PCIe transmission efficiency is greatly reduced, the communication delay is increased, and the processing amount and the real-time performance of system data are affected.

In summary, the conventional method for PCIe data communication applied to EPA has disadvantages in that: when the communication of large data volume, the interruption response is too frequent, which easily causes that the processing capacity and the real-time performance of the system can not meet the requirements, i.e. the traditional EPA PCIe communication mode is only suitable for the low-performance scene of low-data volume processing, thereby causing the great waste of the processor capacity and PCIe bandwidth, and also limiting the application of the EPA in the field of large-data volume transmission processing.

Disclosure of Invention

The invention aims to provide a PCIe data transmission method and a system applied to EPA based on FPGA, which can improve the PCIe transmission performance of an EPA system and greatly reduce the load of a processor participating in transmission on the premise of not increasing hardware cost, so that the processor can be concentrated on data processing or other system affairs.

In order to achieve the above technical effects, the present invention provides a PCIe data transmission system applied to EPA based on an FPGA, including: the system comprises a processor system and a processor memory, wherein the processor memory comprises a receiving cache and a sending cache; the EPA unit is communicated with the processor system through a PCIe bus and constructed based on FPGA, the EPA unit comprises a PCIe communication module, a data cache management module and an interrupt management module, the PCIe communication module is used for communicating with the processor, the data cache management module is used for initiating data writing and reading operations to a memory of the processor, the interrupt management module is used for managing an initiation interval of MSI interrupt or directly shielding, the PCIe communication module comprises a PCIe cache region, a PCIe data transceiving protocol stack and a DMA, the PCIe cache region comprises an EPA sending cache and an EPA receiving cache, the data cache management module is used for triggering and controlling the DMA to realize moving in different directions, and the interrupt management module can be configured by the processor in real time to realize shielding or opening interrupt.

In a preferred embodiment, the data cache management module includes: the system comprises a processor sending cache management module, a processor receiving cache management module and a DMA (direct memory access) triggering module; the processor sending cache management module comprises two head and tail pointers, when the EPA unit is initialized, the processor writes the initial address and the size of the processor sending cache into the processor sending cache management module by driving according to a system application program, and the EPA unit initializes the head and tail pointers; when the EPA unit works normally, the head pointer is maintained by the processor, the tail pointer is maintained by the EPA unit, and an empty mark or a full mark of a sending cache is generated in real time; the processor receiving cache management module contains two head and tail pointers, when the processor initializes the EPA unit, the initial address and the size of the processor receiving cache are written into the processor receiving cache management module through driving according to a system application program, and the EPA unit initializes the head and tail pointers; when the EPA unit works normally, the head pointer is maintained by the EPA unit, the tail pointer is maintained by the processor, and an empty or full mark of the receiving cache is generated in real time; the DMA triggering module triggers the DMA which sends the cache and reads the data frame from the processor according to the non-empty mark of the processor sending cache management module, and triggers the DMA which writes the data frame into the processor receiving cache according to the non-full mark of the processor receiving cache management module when the data needs to be written into the processor receiving cache.

In a preferred embodiment, the interrupt management module may be configured by the processor to set different interrupt trigger frequencies, and when an interrupt is turned on, the MSI interrupt may be periodically sent according to a non-empty indication that the processor receives the cache management module.

Based on the same inventive concept, the invention also provides a PCIe data transmission method applied to EPA based on FPGA, which is applied to any one of the above data transmission systems, and includes: reading the data length from the transmission buffer of the current processor system and transmitting the frame data under the condition that the transmission buffer of the processor system is not empty, and updating a transmission completion mark of the frame data in the transmission buffer of the processor system after the frame data is completely transmitted by the EPA unit; under the condition that data exists in the EPA unit receiving buffer, reading the data length from the EPA unit receiving buffer and sending the frame data to the receiving buffer of the processor system; before the EPA unit is started to work formally, the starting addresses and the sizes of the receiving cache and the sending cache are written into the EPA unit based on the FPGA in a processor system based on the pre-allocated receiving cache and sending cache, and the receiving cache and the sending cache are maintained in a ring queue mode.

In a preferred embodiment, the pre-allocated receive buffer and transmit buffer addresses are consecutive and are in 2KB of a small unit for storing a frame of EPA data.

In a preferred embodiment, the processor, upon initialization of the EPA unit, in accordance with the system application: writing the initial address and the size of a processor sending cache into a processor sending cache management module through driving, and initializing head and tail pointers by an EPA unit; when the EPA unit works normally, the head pointer is maintained by the processor, the tail pointer is maintained by the EPA unit, and an empty or full mark of a sending cache is generated in real time; writing the initial address and the size of a processor receiving cache into a processor receiving cache management module through driving, and initializing head and tail pointers by an EPA unit; when the EPA unit works normally, the head pointer is maintained by the EPA unit, the tail pointer is maintained by the processor, and the empty or full mark of the receiving cache is generated in real time.

In a preferred embodiment, the transfer length of the DMA is determined by the frame length of the data packet, the FPGA actively reads the length of the data packet to be transmitted before starting the DMA, and the length of the data packet is taken as the transfer length of the DMA, so as to further improve the transmission efficiency.

In a preferred embodiment, when the interrupt management module is configured by the processor, different interrupt trigger frequencies are set based on different working conditions, and when the interrupt is started, the MSI interrupt is periodically sent according to a non-empty indication that the processor receives the cache management module.

Based on the same inventive concept, the invention also provides a PCIe data transmission device applied to EPA based on FPGA, which includes: the data reading module is used for reading the data length from the sending buffer of the current processor system and sending the frame data under the condition that the sending buffer of the processor system is not empty, and updating a sending completion mark of the frame data in the sending buffer of the processor system after the sending of the frame data by the EPA unit is completed; the data writing module is used for reading the data length from the receiving cache of the EPA unit and sending the frame data to the receiving cache of the processor system under the condition that the data exists in the receiving cache of the EPA unit; before the EPA unit is started to work formally, the starting addresses and the sizes of the receiving cache and the sending cache are written into the EPA unit based on the FPGA in a processor system based on the pre-allocated receiving cache and sending cache, and the receiving cache and the sending cache are maintained in a ring queue mode.

Based on the same inventive concept, the present invention also provides a computer apparatus, comprising: a memory for storing a processing program; and the processor is used for realizing any PCIe data transmission method applied to EPA based on the FPGA when executing the processing program.

Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects:

according to the PCIe data transmission method and system based on the FPGA and applied to the EPA, the problem that the existing EPA PCIe cannot be applied to the field of large data volume transmission because the processing capacity and the real-time performance of the system cannot meet the requirements due to too frequent interrupt response when the communication of the large data volume is carried out is solved, the interaction between the two parties is reduced by directly accessing the memory of a processor through the FPGA PCIe, the transmission efficiency of the PCIe is greatly improved, the hardware cost is not increased, and the hardware does not need to be changed. The method benefits from abundant memory resources of a processor system, so that the data transmission rate between the EPA and the processor is greatly improved, the application scene of the EPA is expanded, the load brought to the processor by PCIe transmission is reduced, and the processor can concentrate on data processing and other system transactions.

Drawings

FIG. 1 is a schematic diagram of a PCIe transport system applied to EPA based on FPGA according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a cache management method according to an embodiment of the present invention;

FIG. 3 is a flow chart of a processor dispatch flow in an embodiment of the present invention;

fig. 4 is a flowchart of an FPGA transmission flow in an embodiment of the present invention;

FIG. 5 is a flow chart of a receiving flow of a processor according to an embodiment of the invention;

FIG. 6 is a flow chart of an FPGA receive flow in an embodiment of the present invention;

FIG. 7 is a flowchart of FPGA interrupt management according to an embodiment of the present invention.

Detailed Description

The PCIe data transmission method and system applied to EPA according to the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims.

As described above, in the PCIe data communication method based on interrupts, when the communication data size between the EPA system and the processor is small, the real-time performance of the processing can be ensured, but in the case of large data size, due to the increase of the number of interrupts, the communication method of data transmission in the interrupt mode is likely to be too frequent due to interrupts, so that it is difficult for the processor and the operating system to respond to the interrupts in time, the PCIe transmission efficiency is greatly reduced, the communication delay is increased, and the processing amount and the real-time performance of the system data are affected.

In order to solve the above problem, embodiments of the present disclosure provide a PCIe data transmission method and system applied to EPA based on an FPGA. According to the method and the system, the PCIe does not need to intervene in a processor in the transmission process through a mode that the PCIe directly accesses the memory of the processor through an FPGA, and meanwhile, an interrupt management function which can be configured by the processor is provided for guaranteeing the real-time performance of data processing.

Hereinafter, specific examples of the present scheme will be described in more detail with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of a PCIe transport system based on FPGA applied to EPA according to an embodiment of the present disclosure. As shown in fig. 1, the system includes an EPA unit, a processor system (including processor memory), a PCIe bus, and an ethernet. The EPA unit and the processor system are in data communication via a PCIe bus.

The EPA unit (only describing the scope of the application) comprises a PCIe communication module, a data cache management module and an interrupt management module.

The PCIe communication module comprises a PCIe cache region, a PCIe data transceiving protocol stack and a DMA.

The PCIe buffer area includes an EPA send buffer and an EPA receive buffer, where the EPA send buffer is used to store a frame of data to be sent read from the processor system send buffer, and the EPA receive buffer is used to store a frame of data received from the ethernet and to be written to the processor system receive buffer.

The PCIe data transceiving protocol stack is controlled by DMA, and executes read-write function to the processor system cache through a PCIe bus.

The DMA is controlled by the data cache management module, different data moving lengths are obtained according to different moving directions when the DMA is triggered, cache reading lengths are sent from the current processor when cache reading operations are sent from the processor, and cache reading lengths are received from PCIe when cache writing operations are received from the processor; after a frame of data is sent by the EPA, the DMA updates the send complete tag for the frame of data in the processor send buffer.

The data cache management module comprises a processor sending cache management module, a processor receiving cache management module and a DMA trigger module.

The processor sending cache management module comprises two head and tail pointers, and when the processor initializes EPA, the FPGA initializes the head and tail pointers by driving and writing in the initial address and size of the sending cache according to a system application program; when EPA normally works, the head pointer is maintained by the processor, the tail pointer is maintained by the FPGA, and the empty or full mark of the sending buffer memory is generated in real time.

The processor receiving cache management module contains two head and tail pointers, and when the processor initializes EPA, the FPGA initializes the head and tail pointers by driving and writing in the initial address and size of the receiving cache according to a system application program; when EPA normally works, the head pointer is maintained by FPGA, the tail pointer is maintained by a processor, and the empty or full mark of the receiving buffer memory is generated in real time.

And the DMA triggering module triggers the reading DMA of the sending cache from the processor according to the non-empty mark of the sending cache management module, and triggers the writing DMA of the receiving cache from the processor according to the non-full mark of the receiving cache management module when data needs to be written into the receiving cache of the processor.

The interrupt management module can be configured by the processor in real time, the processor can shield or start the interrupt according to actual needs, and a certain interrupt triggering frequency can be set. When the interrupt is turned on, the MSI interrupt is periodically sent based on the processor receiving a non-empty indication from the cache management module.

PCIe data transmission method and system based on FPGA applied to EPA according to the embodiment of the present disclosure will be described below with reference to fig. 2, fig. 3, fig. 4, fig. 5, fig. 6, and fig. 7. Fig. 2 illustrates a cache management method of the PCIe data transmission method and system applied to EPA based on FPGA according to an embodiment of the present disclosure. Fig. 3 and 4 are flowcharts illustrating a sending direction in a PCIe data transmission method based on FPGA applied to EPA according to an embodiment of the disclosure, since the present invention optimizes the interaction between the processor and the FPGA, the sending process of the processor and the FPGA is relatively independent, where fig. 3 shows the sending flow of the processor, and fig. 4 shows the sending flow of the FPGA. Fig. 5 and 6 are flowcharts illustrating a receiving direction in the PCIe data transmission method applied to the EPA based on the FPGA according to the embodiment of the present disclosure, and a receiving process of the processor and the FPGA is also a relatively independent process, where fig. 5 represents the receiving flow of the processor, and fig. 6 represents the receiving flow of the FPGA. Fig. 7 illustrates an interrupt management flow in the PCIe data transmission method applied to the EPA based on the FPGA according to an embodiment of the present disclosure.

Fig. 2 illustrates a cache management method according to an embodiment of the present disclosure, in which both a transmission cache and a reception cache are managed.

The head pointer and the tail pointer of the sending cache and the receiving cache are both positioned in the FPGA, the head pointer of the sending cache is maintained by the processor, the tail pointer is maintained by the FPGA, the head pointer of the receiving cache is maintained by the FPGA, and the tail pointer is maintained by the processor; the cached states are uniformly managed by the FPGA so as to avoid state conflicts caused by asynchronous information.

The buffer takes 2KB as a small space and can store one frame of data, the blank 2KB in the figure represents idle, and the shaded 2KB represents data; for the transmission buffer, the first 4 bytes of the 2KB space represent transmission completion indication, 0 represents no transmission, and 1 represents transmission completion, when the processor writes data to be transmitted, the first 4 bytes are 0, and after the epa transmission is completed, the FPGA writes the first 4 bytes of the space to 1, which represents transmission completion. The processor may determine whether the frame of data needs to be retransmitted based on the flag.

The cache is maintained in a circular queue mode, although two cases of head and tail pointers are listed in the figure, the maintenance method is consistent; the head pointer points to the next space to be written, and the tail pointer points to the space which is read at present; the tail pointer +1 equals the head pointer indicating that the buffer is empty, and the head pointer equals the tail pointer indicating that the buffer is full.

Fig. 3 shows a flow diagram of a processor transmit flow according to an embodiment of the disclosure.

In step 301, the processor schedules a sending task, before sending data, the FPGA register needs to be queried to determine whether a sending buffer is full, if so, the sending task is exited, the sending task is resumed when the sending task is scheduled next time, and if not, the process proceeds to step 302.

At step 302, the processor obtains the head pointer of the transmit buffer, writes the data to be transmitted into the 2KB free space in the transmit buffer pointed to by the head pointer, and then points the head pointer +1 to the next 2KB free space, and updates the transmit buffer head pointer inside the FPGA.

By the mode, the processor can judge whether the processor can fill the sending buffer with the sending buffer by only sending buffer state indication of the FPGA, the sending task of the processor can be finished by only updating the sending buffer head pointer after the filling, and particularly, the processor can write a large amount of data to be sent once due to the large memory of the processor, so that the frequency of dispatching the sending task by the processor is reduced, and the load of the processor is effectively reduced.

Fig. 4 shows a flow diagram of an FPGA transmission flow according to an embodiment of the present disclosure.

At step 401, if the transmit buffer in the processor is not empty, the FPGA starts the process of transmitting one frame of data.

At step 402, the FPGA pre-adds 1 to the tail pointer of the transmission buffer, points to the 2KB space to be transmitted in the transmission buffer, and obtains the length of the data to be transmitted.

At step 403, the FPGA starts DMA for reading data from the send buffer and storing the data into the EPA send buffer according to the length of the obtained data and the send buffer real address pointed by the tail pointer of + 1.

At step 404, it is waited for whether the DMA of the read data is complete.

At step 405, DMA of the read data has been completed, enabling EPA transmission of this frame of data.

At step 406, it waits for the data in the EPA send cache to be sent.

After the frame data is sent, the FPGA formally updates the tail pointer +1, updates the tail pointer, and updates the send complete flag located in the processor send buffer in step 407, and then returns to step 401.

Through the mode, the FPGA can continuously process the data in the sending cache, the sending process does not depend on interaction with a processor, and the PCIe transmission efficiency and the EPA sending efficiency are maximized.

Fig. 5 shows a flow diagram of a processor receive flow in accordance with an embodiment of the present disclosure.

The processor enters step 501 according to the regular query or the MSI interrupt, the processor firstly queries a receiving cache status register in the FPGA, if the receiving cache status register is empty, the operation is exited, and if the receiving cache status register is not empty, the operation enters step 502.

At step 502, the processor pre-adds 1 to the tail pointer to point to the 2KB data space to be processed in the receive buffer, then obtains the data, processes the data, formally updates the tail pointer +1 of the receive buffer in the FPGA after the processing is finished, and then reenters step 501.

By the mode, the processor can judge whether the received data need to be processed only through the receiving buffer state indication of the FPGA, and can continue processing the next frame only by updating the receiving buffer tail pointer after processing one frame until the receiving buffer is empty. The method benefits from the large memory of the processor, the processor can process a large amount of receiving at one time, the times of scheduling receiving tasks by the processor are reduced, and the data processing efficiency of the processor is greatly improved.

Fig. 6 shows a flow diagram of an FPGA reception flow according to an embodiment of the present disclosure.

The FPGA receives a frame of EPA data from the Ethernet, and the step 601 is entered, the FPGA enters the step 602 if the receiving buffer is not full according to the state of the receiving buffer, and the step 606 if the receiving buffer is full.

At step 606, the frame EPA data is discarded, the receive overflow flag is set, and overflow packet count is performed.

At step 602, the FPGA obtains the data length in the EPA receive cache.

At step 603, the FPGA starts DMA writing data to the receive buffer, moves the length of the data in the EPA receive buffer, and writes the data into the 2KB free space in the receive buffer pointed to by the head pointer.

At step 604, it is waited whether the write data DMA is complete.

At step 605, after the FPGA updates the head pointer by +1, the FPGA updates the head pointer to point to the next 2KB space to be written in the receive cache.

Through the mode, the FPGA can continuously process the EPA data received from the Ethernet, the receiving flow of the FPGA does not depend on the interaction with the processor, and the PCIe transmission efficiency and the EPA receiving efficiency are maximized.

FIG. 7 shows a flow diagram of FPGA interrupt management according to an embodiment of the present disclosure.

At step 701, if the interrupt of the FPGA is enabled, the next step is performed.

At step 702, the FPGA obtains the status of the receive buffer, and if not empty, performs the next step.

At step 703, the FPGA determines whether the minimum interval time from the last MSI interrupt is reached, and if so, performs the next step. Where the minimum interrupt interval time is written by the processor in real time, ranging from 1us to 10ms.

At step 704, the FPGA sends MSI interrupts over PCIe.

By the mode, the minimum interrupt interval can be adjusted in real time by the processor, and the real-time performance of data processing and the load of the processor can be balanced by the processor according to actual conditions.

The PCIe data transmission method based on the FPGA applied to the EPA greatly improves the transmission efficiency of the PCIe, greatly improves the data transmission rate between the EPA and a processor, expands the application scene of the EPA, and simultaneously reduces the load brought to the processor by the PCIe transmission, so that the processor can be concentrated on data processing and other system transactions.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the embodiments. Even if various changes are made to the present invention, it is still within the scope of the present invention if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A PCIe data transmission system applied to EPA based on FPGA, comprising:

the system comprises a processor system and a processor memory, wherein the processor memory comprises a receiving cache and a sending cache;

the EPA unit is communicated with the processor system through a PCIe bus and constructed on the basis of FPGA, and comprises a PCIe communication module, a data cache management module and an interrupt management module, wherein the PCIe communication module is used for communicating with the processor, the data cache management module is used for initiating data writing and reading operations on a memory of the processor, the interrupt management module is used for managing an initiation interval of MSI interrupt or directly shielding, the PCIe communication module comprises a PCIe cache region, a PCIe data transceiving protocol stack and a DMA, the PCIe cache region comprises an EPA sending cache and an EPA receiving cache, the data cache management module is used for triggering and controlling the DMA to realize moving in different directions, and the interrupt management module can be configured by the processor in real time to realize shielding or opening interrupt.

2. The FPGA-based PCIe data transfer system for EPA of claim 1 wherein said data cache management module comprises: the system comprises a processor sending cache management module, a processor receiving cache management module and a DMA (direct memory access) triggering module;

the processor sending cache management module comprises two head and tail pointers, when the EPA unit is initialized, the processor writes the initial address and the size of the processor sending cache into the processor sending cache management module through driving according to a system application program, and the EPA unit initializes the head and tail pointers; when the EPA unit works normally, the head pointer is maintained by the processor, the tail pointer is maintained by the EPA unit, and an empty mark or a full mark of a sending cache is generated in real time;

the processor receiving cache management module contains two head and tail pointers, when the processor initializes the EPA unit, the initial address and the size of the processor receiving cache are written into the processor receiving cache management module through driving according to a system application program, and the EPA unit initializes the head and tail pointers; when the EPA unit works normally, the head pointer is maintained by the EPA unit, the tail pointer is maintained by the processor, and an empty or full mark of the receiving cache is generated in real time;

the DMA triggering module triggers the DMA which sends the cache and reads the data frame from the processor according to the non-empty mark of the processor sending cache management module, and triggers the DMA which writes the data frame into the processor receiving cache according to the non-full mark of the processor receiving cache management module when data needs to be written into the processor receiving cache.

3. The FPGA-based PCIe data transport system for EPA as claimed in claim 1, wherein the interrupt management module is configured by the processor to set a different interrupt trigger frequency, and when the interrupt is turned on, the MSI interrupt is sent periodically according to a non-empty indication received by the processor from the cache management module.

4. A PCIe data transmission method applied to the EPA based on the FPGA, which is applied to the data transmission system according to any one of claims 1 to 3, and the PCIe data transmission method includes:

when the sending buffer of the processor system is not empty, reading the data length from the sending buffer of the current processor system and sending the frame data, and after the sending of the frame data by the EPA unit is finished, updating a sending completion mark of the frame data in the sending buffer of the processor system;

reading the data length from the receiving buffer of the EPA unit and sending the frame data to the receiving buffer of the processor system under the condition that the EPA unit has data in the receiving buffer;

before the EPA unit is started to work formally, the starting addresses and the sizes of a receiving buffer and a sending buffer are written into the EPA unit based on the receiving buffer and the sending buffer which are distributed in advance in a processor system, and the receiving buffer and the sending buffer are maintained in a ring queue mode.

5. The FPGA-based PCIe data transfer method applied to EPA as claimed in claim 4 wherein the pre-allocated receive buffer and send buffer addresses are contiguous and have 2KB as a small unit to store one frame of EPA data.

6. The method of claim 4, wherein the processor, upon initializing the EPA unit, in accordance with the system application:

writing the initial address and the size of a processor sending cache into a processor sending cache management module through driving, and initializing head and tail pointers by an EPA unit; when the EPA unit works normally, the head pointer is maintained by the processor, the tail pointer is maintained by the EPA unit, and an empty or full mark of a sending cache is generated in real time;

writing the initial address and the size of a processor receiving cache into a processor receiving cache management module through driving, and initializing head and tail pointers by an EPA unit; when the EPA unit works normally, the head pointer is maintained by the EPA unit, the tail pointer is maintained by the processor, and the empty or full mark of the receiving cache is generated in real time.

7. The PCIe data transmission method based on FPGA for EPA as claimed in claim 4 wherein the DMA transfer length is determined by the frame length of the data packet, the FPGA actively reads the data packet length to be transmitted before starting the DMA, and takes the data packet length as the DMA transfer length, thereby further improving the transmission efficiency.

8. The method of claim 4, wherein the interrupt management module is configured by the processor to set different interrupt trigger frequencies based on different operating conditions, and when the interrupt is turned on, the MSI interrupt is sent periodically according to a non-empty indication received by the processor from the cache management module.

9. A PCIe data transfer apparatus applied to EPA based on FPGA, comprising:

the data reading module is used for reading the data length from the sending buffer of the current processor system and sending the frame data under the condition that the sending buffer of the processor system is not empty, and updating a sending completion mark of the frame data in the sending buffer of the processor system after the frame data is sent by the EPA unit;

the data writing module is used for reading the data length from the receiving cache of the EPA unit and sending the frame data to the receiving cache of the processor system under the condition that the data exists in the receiving cache of the EPA unit;

before the EPA unit is started to work formally, the starting addresses and the sizes of the receiving cache and the sending cache are written into the EPA unit based on the FPGA in a processor system based on the pre-allocated receiving cache and sending cache, and the receiving cache and the sending cache are maintained in a ring queue mode.

10. A computer device, comprising:

a memory for storing a processing program;

a processor which, when executing the processing program, implements the method for PCIe data transfer applied to the EPA based on the FPGA of any one of claims 4 to 8.