CN115668643A - Routing and placement in antennas - Google Patents

Abstract

The present disclosure describes routing and placement of antennas. In one embodiment, the antenna includes an aperture having: a plurality of Radio Frequency (RF) radiating antenna elements, wherein each antenna element of the plurality of RF radiating antenna elements comprises an iris slit opening and an electrode over the iris slit opening; a plurality of drive transistors coupled to the plurality of antenna elements; and a plurality of storage capacitors, each coupled to an electrode of one of the plurality of antenna elements. The pore size further includes at least one of: a driving transistor of one antenna element is located under an electrode of the antenna element; the storage capacitor of one antenna element is located under the electrode of the antenna element; and the metal routing of the first voltage to the one antenna element overlaps, in the overlap region, the common voltage routing that routes the common voltage to the one antenna element to form the storage capacitor.

Description

Routing and placement in antennas

Cross Reference to Related Applications

Priority is claimed for this application to U.S. provisional patent application No. 63/004,274 filed on day 2, 4-2020, U.S. provisional patent application No. 63/005,067 filed on day 3, 4-2020, U.S. provisional patent application No. 63/005,056 filed on day 3, 4-2020, and U.S. non-provisional patent application No. 17/219,745 filed on day 31, 3-2021, which are all incorporated herein by reference.

Technical Field

Embodiments of the present invention relate to wireless communications; more particularly, embodiments of the invention relate to routing wires or traces in an antenna (e.g., a satellite antenna).

Background

Radio Frequency (RF) metamaterial antennas having multiple frequency bands and/or operating at high frequencies (e.g., ka band) require a high density of RF antenna elements. One type of metamaterial antenna uses a Liquid Crystal (LC) based RF radiating metamaterial antenna element. These antenna elements may be controlled or driven by an active matrix driver. In some embodiments, one transistor is coupled to each LC-based RF metamaterial antenna element and the antenna elements are turned on or off by applying a voltage to a select signal coupled to the transistor gate. Many different types of transistors may be used, including Thin Film Transistors (TFTs). In this case, the active matrix is referred to as a TFT active matrix.

The active matrix uses address and drive circuitry to control each LC-based RF metamaterial antenna element. To ensure that each antenna element has a unique address, the matrix uses rows and columns of conductors to create connections for the select transistors. When the number of antenna elements is large, the number of rows and columns of conductors that control and drive the antenna elements may make routing of all connections difficult.

An RF metamaterial antenna typically includes a storage capacitor and a drive transistor. For example, when the drive transistor is a TFT, the RF metamaterial antenna puts many TFT/capacitor structures into the layout. When the RF antenna elements are arranged in a ring, these TFT/capacitor structures consume a large portion of the space between the rings of RF antenna elements. This space is needed to route signals to the RF antenna elements. However, in RF metamaterial antennas having a high density of RF antenna elements, the available area between RF antenna elements is reduced, which reduces the available space for routing lines (e.g., source, gate, and drain lines, etc.) of the drive transistors in these structures and in them.

Disclosure of Invention

The present disclosure describes routing and placement of antennas. In one embodiment, the antenna includes an aperture having: a plurality of Radio Frequency (RF) radiating antenna elements, wherein each antenna element of the plurality of RF radiating antenna elements comprises an iris slit (slot) opening and an electrode above the iris slit opening; a plurality of drive transistors coupled to the plurality of antenna elements; and a plurality of storage capacitors, each storage capacitor coupled to an electrode of one of the plurality of antenna elements. The pore size further comprises at least one of: a driving transistor of one antenna element is located under an electrode of the antenna element; the storage capacitor of one antenna element is located under the electrode of the antenna element; and the metal routing of the first voltage to the one antenna element overlaps, in the overlap region, the common voltage routing that routes the common voltage to the one antenna element to form the storage capacitor.

In one embodiment, an antenna includes: a plurality of Radio Frequency (RF) radiating antenna elements, wherein each antenna element of the plurality of RF radiating antenna elements comprises an iris slit opening and an electrode above the iris slit opening; and a plurality of drive transistors, each drive transistor coupled to one of the plurality of antenna elements, wherein one or more metal routing lines between pairs of drive transistors pass through one or more RF radiating antenna elements.

In one embodiment, an antenna includes: a plurality of RF radiating antenna elements; and a plurality of structures coupled to the plurality of RF radiating antenna elements, each structure having a drive transistor coupled to the storage capacitor to drive the plurality of antenna elements, wherein each structure of the plurality of structures includes a plurality of drain terminals.

Drawings

The embodiments and their advantages are best understood by referring to the following description taken in conjunction with the accompanying drawings. These drawings in no way limit any changes in form and detail that may be made to the described embodiments by one skilled in the art without departing from the spirit and scope of the described embodiments.

Figure 1A illustrates one embodiment of a prior art storage capacitor structure for an RF antenna element.

FIG. 1B illustrates one embodiment of a layout of antenna elements and drive transistor/storage capacitor structures.

Fig. 1C shows another embodiment of a layout that extends a common voltage routing line under the source metal routing and uses the source metal and common voltage metal overlap under the patch electrode.

Fig. 2A shows one embodiment of a portion of an antenna aperture having an antenna element with a drive transistor located in an electrode area.

Figure 2B shows an embodiment of an antenna element with a drive transistor and a storage capacitor located in the electrode area.

Figure 2C illustrates a side view of one embodiment of the antenna element shown in figure 2B having a drive transistor and a storage capacitor located in an electrode area.

Fig. 2D illustrates one embodiment of a drive transistor and a portion of a storage capacitor shifted into an electrode region.

Fig. 3A and 3B show examples of RF elements having parallel routing traces along major axes.

Fig. 3C shows an example of using a new metal layer and an added passivation layer in an RF antenna element.

Fig. 4 shows an example where the patch electrodes extend beyond the iris slit opening.

Figure 5A illustrates one embodiment of a structure containing a drive transistor (e.g., TFT) and a storage capacitor as part of a matrix drive control system.

Figure 5B shows a structure of a drive transistor/storage capacitor with multiple drain connections.

Figure 5C illustrates one embodiment of a drive transistor/storage capacitor structure having inverted drain and gate locations.

Figure 5D illustrates one embodiment of a rotary drive transistor/storage capacitor structure.

Figure 6 shows an aperture having one or more arrays of antenna elements placed in concentric rings around the input feed of a cylindrical feed antenna.

Fig. 7 shows a perspective view of a row of antenna elements comprising a ground plane and a reconfigurable resonator layer.

Figure 8A shows one embodiment of a tunable resonator/slit.

Figure 8B illustrates a cross-sectional view of one embodiment of a physical antenna aperture.

Fig. 9A shows a portion of a first iris plate layer positioned to correspond to the slits.

Figure 9B shows a portion of a second iris plate layer containing slits.

Fig. 9C shows a patch on a portion of a second iris plate layer.

Fig. 9D shows a top view of a portion of the slot array.

Figure 10 illustrates a side view of one embodiment of a cylindrical feed antenna structure.

Fig. 11 shows another embodiment of an antenna system with an outgoing wave.

Figure 12 illustrates one embodiment of the placement of the matrix drive circuitry relative to the antenna elements.

Fig. 13 illustrates one embodiment of a TFT package.

Fig. 14 is a block diagram of another embodiment of a communication system with simultaneous transmit and receive paths.

Detailed Description

In the following description, numerous details are set forth to provide a more thorough explanation of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

Techniques are disclosed to increase the area available for routing wires or traces in an antenna (e.g., a satellite antenna). Throughout the specification, the terms "line" and "trace" will be used interchangeably. In one embodiment, the antenna has Radio Frequency (RF) metamaterial antenna elements driven by Thin Film Transistors (TFTs) that are part of a matrix driver. Examples of such antennas (e.g., electronically steerable antennas with Liquid Crystal (LC) based metamaterial RF radiating antenna elements, etc.) will be described in detail below; however, the techniques described herein are not limited to such antennas and may be used for other antennas having other types of antenna elements (e.g., varistor-based antenna elements, MEMs-based antenna elements, etc.) controlled by other types of drive mechanisms and/or drive transistors.

In one embodiment, by placing the storage capacitor for the RF metamaterial antenna driving the transistor drive in a previously unavailable or forbidden area of the layout, e.g., the area occupied by the RF element (i.e., the RF element area), the area available for routing wires (traces) is increased in a manner that does not degrade the RF antenna performance. In one embodiment, this is accomplished by using a routing line from the storage capacitor to an electrode (e.g., a patch electrode) of the RF antenna element as part of the storage capacitor of the RF antenna element. This increases the area available for routing. In one embodiment, the voltage routing lines are used as part of the storage capacitors of the RF antenna elements by extending the voltage routing lines above or below each other, overlapping the voltage routing lines. This overlap of voltage routing lines can result in additional capacitance. In one embodiment, one voltage routing line may be positioned over the center of another voltage routing line. In one embodiment, the metal lines from the drain of the drive transistor (e.g., TFT) of the antenna element overlap (e.g., above, below) the common voltage (Vcom) routing lines. The overlap does not necessarily have to extend the entire length of the route line. During the design process, the capacitance that can be generated per unit length can be calculated, and then the length of overlap calculated to achieve the desired capacitance value. In one embodiment, the overlapping voltage routing lines are routed on a substrate (e.g., a chip substrate) of the antenna aperture and are separated from each other by one or more layers of material (e.g., a dielectric (e.g., a passivation layer)).

In another embodiment, the area available for routing wires (traces) is increased by placing some or all of the storage capacitors under the electrodes of the RF antenna elements that locate and control the operation of the iris slit opening. In one embodiment, the electrodes are patch electrodes of an iris/patch pair. In another embodiment, the electrode is a tunable dielectric device.

In one embodiment, the area available for routing is increased by placing the drive transistors (e.g., TFTs) of the RF antenna elements under the electrodes (e.g., patch electrodes).

As a result of using these techniques, storage capacitor structures are placed in spaces not previously used for storage capacitors, and the size of the storage capacitors is reduced, creating more space for routing in these areas.

In one embodiment, an antenna includes an antenna aperture having a plurality of Radio Frequency (RF) radiating antenna elements. Each antenna element of the plurality of RF radiating antenna elements includes an iris slit opening and an electrode over the iris slit opening. In one embodiment, the antenna aperture includes a plurality of drive transistors (e.g., matrix drive transistors, etc.) and a plurality of storage capacitors coupled to the plurality of antenna elements. Each storage capacitor is coupled to an electrode of one of the antenna elements. In one embodiment, the aperture further comprises one or more of:

1) The drive transistor of one antenna element is located below an electrode (e.g., patch electrode, etc.) of the antenna element,

2) The storage capacitor of an antenna element is located below the electrode of the antenna element, an

3) The metal routing of the first voltage to one antenna element overlaps a second voltage routing (e.g., common voltage routing, etc.) within the overlap region that, when overlapped, routes the second voltage to one antenna element, thereby forming a storage capacitor.

Figure 1A illustrates one embodiment of a prior art storage capacitor structure for an RF antenna element. Referring to fig. 1A, a driving transistor/capacitor structure includes a storage capacitor 101 and a transistor (e.g., a Thin Film Transistor (TFT) or the like) 102. In one embodiment, storage capacitor 101 and transistor 102 are connected by a metal trace on the source routing layer. A common voltage (Vcom) route 103 is coupled to the storage capacitor 101 and the transistor 102. The antenna element is coupled to the transistor/capacitor structure and includes an iris slit opening 105 and a patch electrode 106 (e.g., patch metal) positioned on a surface of iris slit opening 105. Drain metal routing line 104 is coupled to the drain of transistor 102 and to patch electrode 106 using one or more vias 111, the drain of transistor 102 being coupled to storage capacitor 101. In one embodiment, the source and drain are both patterned on the same metal layer, with the source line connecting the TFT source terminal to the driver integrated circuit and the drain line connecting the TFT drain terminal to the storage capacitor and the patch.

FIG. 1B illustrates one embodiment of a layout of antenna elements and drive transistor/storage capacitor structures. The illustrated arrangement provides additional capacitance by extending the Vcom routing lines under the drain metal routing lines so that they overlap. In one embodiment, these are separated by a passivation layer between those metal layers. In one embodiment, a dielectric material is used as the passivation layer. In one embodiment, the amount of separation between the two electrodes depends on a number of factors, such as, but not limited to, the processability of the dielectric material, the characteristics of the dielectric material, the size of the TFT array, the refresh frequency of the TFT array. Note that dielectric layers 0.1-0.3um thick are commonly used in LCDs. The extra capacitance provided by this arrangement makes the storage capacitors of the drive transistor/storage capacitor structure smaller than if the Vcom routing line and the drain metal routing line were non-overlapping.

Referring to fig. 1B, the driving transistor/storage capacitor structure includes a storage capacitor 115 and a transistor 102. In one embodiment, transistor 102 is a TFT. However, in alternative embodiments, the transistor 102 is another type of drive transistor. The storage capacitor 115 is smaller than the storage capacitor 101 of fig. 1A due to the capacitance generated by the overlapping voltage routing lines, and its profile is set as the front storage capacitor region 112 in fig. 1B.

The drive transistor/storage capacitor structure is coupled to Vcom routing line 113.Vcom routing line 113 is a metal trace running under drain metal routing line 104 and connected to patch electrode 106 along drain metal line 104 using one or more vias 111. Thus, from the drive transistor/storage capacitor structure to its connection with the patch electrode (e.g., patch metal) 106, the Vcom routing line 113 overlaps the drain metal routing line 104. In an alternative embodiment, vcom metal routing line 113 is located above drain metal routing line 104. As described above, the overlap of the voltage routing lines provides additional capacitance, which means that the storage capacitor 115 can be smaller than the conventional storage capacitor shown in FIG. 1A.

FIG. 1C shows another arrangement that provides additional capacitance by extending the Vcom routing lines under the drain metal routing and forming additional capacitance between the drain metal and Vcom metal under the patch electrode.

Referring to fig. 1C, the driving transistor/storage capacitor structure includes a capacitor 116 and a transistor 102 (e.g., a TFT). Storage capacitor 116 can be smaller than storage capacitor 101 of FIG. 1A, with its outline shown as front storage capacitor region 112, because the additional capacitance provided by the overlapping voltage routing lines and the capacitance formed between the Vcom metal and the drain metal under electrode 106.

The drive transistor/storage capacitor structure is coupled to Vcom routing line 113. As in fig. 1B, vcom metal 113 overlaps drain metal 104, and both continue to patch electrode 106. The drain metal routing line 104 is coupled to the patch electrode 106 using one or more vias 120.

The drain metal routing line 104 is connected to the drain metal 122. The drain metal 122 is larger in area than the drain metal connected to the patch electrode 106. In one embodiment, vcom metal 121 is larger than and extends beyond both sides of drain metal 122, and forms a capacitance between Vcom metal 121 and drain metal 122. Even so, drain metal 122 and Vcom metal 121 form a capacitor by occupying a small area. In this case, the capacitance will be very small. To obtain the required capacitance, the TFT array parameters are configured, which can range from, for example, 10x10um up to 600x600um, depending on the design. In one embodiment, the overlap dimension (e.g., width) between Vcom metal 121 and drain metal 122 is larger under the electrode than outside the electrode. Due to the overlap of Vcom metal 121 and drain metal 122, the capacitance under patch electrode 106 can be adjusted by adjusting the size of one or both of common voltage metal layer 121 and drain metal layer 122.

In one embodiment, the drive transistor (e.g., TFT) of one antenna element is located below an electrode (e.g., patch electrode) of the antenna element, while the storage capacitor of one antenna element remains outside the electrode area. That is, the transistors (e.g., TFTs that are part of a direct matrix drive control system) used to control the antenna elements are placed within the patch electrode areas. This results in an increase in the area available for routing.

Fig. 2A illustrates one embodiment of a portion of an antenna aperture having an antenna element with a drive transistor located within an electrode area (e.g., a patch electrode area). Referring to fig. 2A, the storage capacitor 201 is coupled to the patch electrode 206 using a via 204 via a drain metal routing line 210. The transistor 202 (e.g., TFT) is placed in the area occupied by the patch electrode 206, which is positioned above the iris slit opening 205.

In one embodiment, the patch electrode 206 is part of a patch structure having a patch and a patch substrate, and the transistor 202 is formed below the patch electrode 206 and between the patch substrate and a patch metal layer attached to the patch structure.

The transistor 202 is coupled to the electrode connection 211 of the next row of driving transistors of the antenna element and to the electrode connection 212 of the previous row of driving transistors of the antenna element.

In one embodiment, both the drive transistor and the storage capacitor are moved into the electrode area (e.g., the patch electrode area). Figure 2B illustrates one embodiment of an antenna element having a drive transistor and a storage capacitor located within an electrode area (e.g., a patch electrode area). Referring to fig. 2B, the patch electrode 206 is positioned over the iris slit opening 205. A drive transistor 222 (e.g., TFT) is located in the area of the patch electrode 206 along with the storage capacitor 221. In one embodiment, the drive transistor 222 and the storage capacitor 221 are both located below the patch electrode 206. In one embodiment, the patch electrode 206 is part of a patch structure having a patch and a patch substrate, and the drive transistor 222 and the storage capacitor 221 are formed below the patch electrode 206 and between the patch substrate and a patch metal layer attached to the patch structure.

Vcom metal 225 is coupled to storage capacitor 221. Drain metal 226 couples storage capacitor 221 to patch electrode 206 using via 214.

A passivation layer is used to separate the transistor 222 and the patch electrode 206 (not shown in fig. 2B). Fig. 2C is a side view of fig. 2B. Electrical connection 211 includes the source and gate electrodes of transistor 222. The source electrode is between passivation layers 245 and 246 of fig. 2C, where passivation layer 245 is a gate insulator layer. In one embodiment, the active region (e.g., a-Si) of transistor 222 is not shown in fig. 2C, but it would be between passivation layers 245 and 246. The passivation layer 245 is a dielectric material that separates the relevant layers of the transistor 222 (e.g., TFT) from the patch electrode 206.

In one embodiment, the drive transistor and the first storage capacitor of one antenna element are located below the electrode of the antenna element, while the second storage capacitor of the antenna element is located outside the electrode of the antenna element. The first and second storage capacitors provide capacitance for the drive transistor.

Fig. 2D illustrates one embodiment of a drive transistor and a portion of a storage capacitor that is moved into an electrode area (e.g., a patch electrode area). Referring to fig. 2D, storage capacitor-2 231 is coupled to a patch electrode 206 via drain metal 210, the patch electrode 206 being located over the iris slit opening 205. The drive transistor 222 (e.g., TFT) and the storage capacitor-1 221 are located in the area of the patch electrode 206. In one embodiment the patch electrode 206 is part of a patch structure with a patch and a patch substrate, and the drive transistor 222 and the storage capacitor 221 are formed below the patch electrode 206 and between the patch substrate and a patch metal layer attached to the patch structure, while the storage capacitor-2 261 is located outside the area of the patch electrode 206.

Vcom metal 225 is coupled to storage capacitor-1 221, and drain metal 226 is coupled to patch electrode 206 using one or more vias 214. Vcom metal 225 is also coupled to an electrical connection 231 with the Vcom of the next row of drive transistors of the antenna element, and an electrical connection 232 with the Vcom of the previous row of drive transistors of the antenna element. The transistor 222 is coupled to an electrical connection 211 to the source and gate of the next row of drive transistors of the antenna element and to an electrical connection 212 to the source and gate of the previous row of drive transistors of the antenna element.

The techniques described herein use space not previously used for routing traces by creating structures that allow the routing traces to pass through the RF element without causing a performance degradation thereof. In one embodiment, parallel routing traces may be used to increase the otherwise available area for routing electrical traces without degrading RF antenna performance.

In one embodiment, the area available for routing electrical traces is increased without degrading RF antenna performance by reallocating the area used in a single RF antenna element in an antenna (e.g., an RF metamaterial antenna), which was previously unavailable or forbidden, such as the RF antenna element area. In other words, space not previously used for routing traces can be used by creating structures that allow routing traces to pass through the RF elements.

For example, the area available for routing electrical traces is increased by one or more of the following.

1) Placing a routing trace structure through the RF antenna elements along a major axis of the RF elements;

2) Reducing the parasitic capacitance of the patch electrode having the routing structure by, for example, increasing the distance between metal layers of the parasitic capacitance and/or changing the dielectric constant of the dielectric material of the parasitic capacitance;

3) Changing connections to the patch electrodes to enable routing; and/or

4) Additional metal layers are added to assist in routing through the RF elements.

Fig. 3A and 3B show examples of RF elements having parallel routing traces along major axes. In one embodiment, the major axis is the axis through the iris slit opening. In one embodiment, the traces are symmetric about the major axis. In one embodiment, the traces are in a gate metal layer. In alternative embodiments, the traces are in the source metal layer or in both the gate and source metal layers.

Referring to fig. 3A, iris slit opening 301 has an axis 310 extending along a longer portion of iris slit opening 301. Routing traces 312 provide routing between drive transistors (e.g., TFTs) and run parallel to the long axis of iris opening 301. This does not impede the routing 311 of the drain metal voltage coupled to the patch electrode using one or more vias 304.

Fig. 3B shows a cross-sectional view of an RF element having the parallel routing traces of fig. 3A. This cross-sectional view is taken along the axis A-A' shown in FIG. 3A. Referring to fig. 3B, patch electrode 302 is shown surrounded by passivation layer 332 and passivation layers 333 and 334. Between passivation layers 333 and 334 is a to-patch route 311 (shown in fig. 3A) that routes the drain voltage to patch electrode 302 using one or more vias 304. Passivation layers 333 and 334 are attached to the patch glass 320 along with routing lines 312 between the transistors. That is, the routing lines 312 running between the drive transistors of the different antenna elements are attached to the patch glass 320 and are located between the patch glass 320 and the patch electrodes 302. In one embodiment, the one or more routing lines 312 comprise parallel metal routing lines that are symmetric with respect to a major axis of the at least one RF element. In one embodiment, routes 312 and 311 are electrodes of a capacitor and passivation layer 334 is a dielectric separating them.

Also shown in fig. 3B is iris glass 321, with iris metal 322 attached to iris glass 321. Iris metal 322 is covered by passivation layers 330 and 331.

In an alternative embodiment, the antenna element comprises a tunable dielectric device over the iris slit opening 301, rather than a patch. In this case, the route 312 is between transistors (e.g., PMOS, gaAs, etc.) that control or drive other antenna elements in the antenna aperture.

In one embodiment, the layer thickness and dielectric constant of the routing passivation may be varied to reduce the parasitic capacitance between the routing lines (e.g., routing lines 312) and the patch electrodes 302. In one embodiment, the thickness of the passivation layers 333 and 334 is increased (e.g., 5-10 microns) to reduce parasitic capacitance. In one embodiment, the dielectric constant of the passivation layer is lowered (e.g., 0.2-0.3) to reduce parasitic capacitance. The material may be changed to silicon dioxide, silicon oxynitride, organic (e.g., polyimide), or the like.

In one embodiment, a new metal layer is added between the patch glass and the gate metal layer. In addition, a new passivation layer is added between the new metal layer and the gate metal layer. This increased stack of passivation layers reduces the parasitic capacity between the patch electrodes and the routing lines.

Fig. 3C shows an example of using a new metal layer and an added passivation layer. Routing 340 between the drive transistors (e.g., TFTs) of the antenna elements occurs on the new metal layer. A new metal layer for routing 340 and a passivation layer (335) are added under the gate metal layer (312 in fig. 3B). A new passivation layer 335 is shown over the routing layer 340 for routing between TFTs, with the routing passivation layer 333 and the passivation layer 334 on top of the passivation layer 335. The new passivation layer 335 operates as a dielectric between the patch electrode 302 and the metal routing lines to reduce parasitic capacitance between the patch electrode 302 and the metal routing lines.

In one embodiment, the patch electrode may extend beyond the iris slit opening to move the via coupling the drain metal to the patch electrode beyond the area of the iris slit opening. In one embodiment, the trace width of the routing lines is thinned in the patch electrode area to reduce parasitic capacitance. Thinning may be done so as not to increase the resistance to a level that adversely affects the operation of the antenna element.

Fig. 4 shows an example where the patch electrodes extend beyond the iris slit opening. Referring to fig. 4, patch electrode 403 includes an extension extending across iris slit opening 301 to via 402, via 402 coupling routing 311 to patch electrode 403. Moving the vias 402 outside the area of the patch electrodes 302 may reduce parasitic capacitance.

In one embodiment, the routing of lines to and from the drive transistor/storage capacitor structure is modified compared to the design in FIGS. 1A-1C. In one embodiment, the modification involves driving a transistor box (e.g., TFT) and based on the position and rotation of nearby RF antenna elements to improve the placement of the gate, source, vcom, and drain routing of the structure. This design differs from the state of the art in the direction of the source and gate lines into and out of the drive transistor box (the area reserved for the transistor and the storage capacitor if required), the position and rotation of the TFT within the transistor box and the direction of the drain from the transistor box. In one embodiment, the transistor box is rotated to improve and optimize as much as possible the connection position with respect to the local RF element geometry.

In one embodiment, the drain routes from the drive transistor/storage capacitor structure are routed away from multiple directions of the structure. In one embodiment, the drains from the drive transistor/storage capacitor structures are routed away to connect RF elements on different rings of antenna elements. Examples of antenna loops are described in more detail below. The rings may be of a larger or smaller radius.

In one embodiment, the drain lines may cross the gate lines, adding some parasitic capacitance. In one embodiment, the drain route from the drive transistor/storage capacitor structure is away from the structure opposite the source line. In one embodiment, an algorithm is used to select the drain location to be connected.

Figure 5A illustrates one embodiment of a structure containing a drive transistor (e.g., TFT) and a storage capacitor as part of a matrix drive control system. Referring to fig. 5A, a transistor 510 (e.g., a TFT) is positioned with a storage capacitor 500 including a bottom plate 520 and a top plate 521. The gate 501 and source 502 are coupled to a transistor 510 and a storage capacitor 500. In one embodiment, the storage capacitor 500 includes a drain terminal 503. Storage capacitor 500 is coupled to Vcom 530.

In one embodiment, an antenna includes a plurality of RF radiating antenna elements (e.g., metamaterial antenna elements) and a plurality of structures coupled to the plurality of RF radiating antenna elements. Each structure has a drive transistor (e.g., TFT) coupled to the storage capacitor to drive the plurality of antenna elements. In one embodiment, each of the plurality of structures includes a plurality of drain terminals.

Figure 5B shows a structure of a drive transistor/storage capacitor with multiple drain connections. Referring to fig. 5B, a gate 501 and a source 502 are coupled to a transistor 510 (e.g., TFT, etc.) and a storage capacitor 500. In one embodiment, the storage capacitor 500 includes 3 drain terminals 540 away from the storage capacitor 500. Each of the drain terminals 540 may be coupled to an RF antenna element. Storage capacitor 500 is coupled to Vcom 530.

In one embodiment, in the drive transistor/storage capacitor structure, the locations of the gate metal lines and the source metal lines are swapped so that the drain lines leave the storage capacitors to the left of the gate and Vcom metal lines. In one embodiment, this occurs without passing the drain line through the source metal line.

Figure 5C illustrates one embodiment of a drive transistor/storage capacitor structure having inverted drain and gate positions. Referring to fig. 5C, the drain terminal 553 is located at the left side of the gate signal 551 such that the voltage on the drain does not cross the gate signal. This allows a variety of configurations to be used in routing, depending on the layout of the antenna elements and the gate and source lines.

Based on the placement of the routing lines, it may be advantageous to rotate the storage capacitors of the RF antenna elements. This may simplify routing. In one embodiment, the drive transistor/storage capacitor structure is rotated compared to its position in the above-described figures to better accept the preferred routing direction and simplify the routing placement algorithm. In one embodiment, one or more connection locations of the routing lines of the drive transistor/storage capacitor structure are rotated to align with routes tangential to the local loop of the element. In one embodiment, one or more connection locations of routing lines of the drive transistor/storage capacitor structure are rotated to align with the routing of a tangent line through a partial ring of elements.

Figure 5D illustrates one embodiment of a rotary drive transistor/storage capacitor structure. Referring to fig. 5D, the storage capacitor 500 is the same as that of fig. 5A except that its position is rotated in the direction of the previous driving transistor 570 and the direction of the next driving transistor 571. In this case, the drain 503 is in the direction of the next RF antenna element. The next RF element may be in a loop corresponding to the antenna element next to the antenna element of the storage capacitor 500. The loop may have a larger radius than the loop of the antenna element associated with the storage capacitor 500 or may have a smaller radius than the loop of the antenna element associated with the storage capacitor 500.

Also shown are gate 501 and source 502.

Example Algorithm Using TFT Box with multiple terminal positions

In one embodiment, the process looks for an area where there is not enough space across the RF element to place a drive transistor/storage capacitor structure for each drive transistor element (e.g., TFT) in the local area. In one embodiment, this is done by checking to determine if there is room to place the drive transistor/storage capacitor structure in the next smaller radius ring or the next largest radius ring. If there is space, the logic will place the drive transistor/storage capacitor structure and select which drain terminal is connected to the drive transistor (e.g., TFT element).

Example Algorithm Using mirroring (from the present drive transistor/storage capacitor Structure)

In one embodiment, the process compares the routing difficulty between two loops of antenna elements. In one embodiment, this comparison is made by measuring, for example, whether the best drive transistor/storage capacitor configuration will have more drains routed to the right or more drains routed to the left. In one embodiment, if the optimal routing of the ring is to use a mirror image structure, where the routing locations of the gate metal and the drain are to use a mirror image drive transistor/storage capacitor structure.

Example Algorithm Using rotational Placement of drive transistor/storage capacitor Structure

Since the RF elements are placed in rings, in one embodiment, the routing between the rings changes direction throughout the layout. In one embodiment, multiple bends in routing may be required to connect the current drive transistor/storage capacitor structure with its single fixed orientation. In one embodiment, the algorithm for placing the drive transistor/storage capacitor structure in a rotational manner includes looking at the local orientation of the routing and RF elements and calculating the rotation of the drive transistor/storage capacitor structure to reduce and minimize as much as possible the routing length required to connect the drive transistor/storage capacitor structure to the neighboring drive transistor/storage capacitor structure and its target RF element.

Examples of antenna embodiments

The above-described techniques may be used for a panel antenna. Embodiments of such a panel antenna are disclosed. The panel antenna includes one or more arrays of antenna elements over an antenna aperture. In one embodiment, the antenna element comprises a liquid crystal cell. In one embodiment, the patch antenna is a cylindrical feed antenna that includes matrix driving circuitry to uniquely address and drive each antenna element that is not placed in rows and columns. In one embodiment, the elements are placed in a ring.

In one embodiment, an antenna aperture having one or more arrays of antenna elements is made up of multiple segments coupled together. When coupled together, the combination of segments forms a closed concentric ring of antenna elements. In one embodiment, the concentric rings are concentric with respect to the antenna feed.

Examples of antenna systems

In one embodiment, the patch antenna is part of a metamaterial antenna system. Embodiments of a metamaterial antenna system for a communication satellite ground station are described. In one embodiment, the antenna system is a component or subsystem of a satellite Earth Station (ES) operating on a mobile platform (e.g., airborne, marine, terrestrial, etc.) that operates using Ka band frequencies or Ku band frequencies to enable civilian commercial satellite communications. It is noted that embodiments of the antenna system may also be used in earth stations that are not on a moving platform (e.g., fixed or transportable earth stations).

In one embodiment, the antenna system uses surface scattering metamaterial technology to form and direct transmit and receive beams through separate antennas.

In one embodiment, the antenna system consists of three functional subsystems: (1) a waveguide structure consisting of a cylindrical wave feed structure; (2) An array of wave scattering metamaterial units as part of an antenna element; and (3) commanding the formation of a control structure that can adjust the radiation field (beam) from the metamaterial scattering elements using holographic principles.

Antenna element

Fig. 6 shows a schematic diagram of an embodiment of a cylindrical fed holographic radial aperture antenna. Referring to fig. 6, the antenna aperture has an array 601 of one or more antenna elements 603, the array 601 of antenna elements 603 being placed in a concentric ring around the input feed 602 of the cylindrical feed antenna. In one embodiment, antenna element 603 is a Radio Frequency (RF) resonator that radiates RF energy. In one embodiment, antenna element 603 includes Rx and Tx irises that are interleaved and distributed over the entire surface of the antenna aperture. Examples of such antenna elements will be described in more detail below. Note that the RF resonators described herein may be used with antennas that do not include a cylindrical feed.

In one embodiment, the antenna comprises a coaxial feed for providing a cylindrical wave feed via the input feed 602. In one embodiment, a cylindrical wave feed architecture feeds the antenna from a central point, with its excitation spreading out from the feed point in a cylindrical fashion. That is, the cylindrically fed antenna generates a concentric feed wave propagating outward. Even so, the shape of the cylindrical feed antenna surrounding the cylindrical feed may be circular, square, or any shape. In another embodiment, a cylindrical feed antenna generates an inwardly propagating feed wave. In this case, the feed wave comes most naturally from a circular structure.

In one embodiment, antenna element 603 comprises an iris, and the aperture antenna of fig. 6 is used to generate a main beam formed by excitation of a cylindrical feed wave radiating the iris through a tunable Liquid Crystal (LC) material. In one embodiment, the antenna may be energized to radiate a horizontally or vertically polarized electric field at a desired scan angle.

In one embodiment, the antenna elements comprise a set of patch antennas. The set of patch antennas includes an array of scattering metamaterial elements. In one embodiment, each scattering element in the antenna system is part of a unit cell comprised of a lower conductor, a dielectric substrate, and an upper conductor that embeds a complementary electrically induced capacitive resonator ("complementary electrical LC" or "CELC") etched or deposited on the upper conductor. As understood by those skilled in the art, in the context of CELC, LC refers to inductive capacitance, not liquid crystal.

In one embodiment, liquid Crystals (LC) are arranged in a gap around the scattering element. The LC is driven by the direct drive embodiment described above. In one embodiment, liquid crystal is encapsulated in each cell and separates the lower conductor associated with the slit from the upper conductor associated with its patch. The liquid crystal has a dielectric constant that is a function of the orientation of the molecules that make up the liquid crystal, and the orientation of the molecules (and thus the dielectric constant) can be controlled by adjusting the bias voltage on the liquid crystal. With this feature, in one embodiment, the liquid crystal integrates an on/off switch for transmitting energy from the guided wave to the CELC. When open, the CELC emits electromagnetic waves like an electrically small dipole antenna. Note that the teachings herein are not limited to having liquid crystals that operate in a binary manner in terms of energy transfer.

In one embodiment, the feed geometry of the antenna system allows the antenna elements to be positioned at a forty-five degree (45 °) angle to the vector of waves in the wave feed. Note that other positions (e.g., 40 ° angle) may be used. Such a position of the element enables control of free space waves received by or emitted/radiated from the element. In one embodiment, the antenna elements are arranged such that the spacing between the elements is less than the free space wavelength of the operating frequency of the antenna. For example, if there are four scattering elements per wavelength, the elements in a 30GHz transmit antenna would be about 2.5mm (i.e., 1/4 of the 10mm free-space wavelength of 30 GHz).

In one embodiment, the two sets of elements are perpendicular to each other and have equal amplitude excitations at the same time if controlled in the same tuning state. Both of these desired characteristics can be achieved simultaneously by rotating them +/-45 degrees with respect to the feed wave excitation. Rotating one set by 0 degrees and another by 90 degrees will achieve the goal of verticality but not equal amplitude excitation. Note that both 0 degrees and 90 degrees may be used to achieve isolation when feeding the antenna element array in a single structure from both sides.

The amount of radiated power per cell is controlled by applying a voltage (potential on the LC channel) to the patch using a controller. Tracking of each patch is used to provide a voltage to the patch antenna. The voltage is used to tune or attenuate the capacitance and thus the resonant frequency of the individual elements to achieve beamforming. The required voltage depends on the liquid crystal mixture being used. The voltage tuning characteristics of a liquid crystal mixture are mainly described by the threshold voltage, at which the liquid crystal starts to be influenced by the voltage, and the saturation voltage, above which an increase in the voltage does not cause a major tuning of the liquid crystal. These two characteristic parameters can be varied for different liquid crystal mixtures.

In one embodiment, as described above, a matrix driver is used to apply voltages to the patch in order to drive each cell separately from all other cells, without the need for separate connections for each cell (direct drive). Due to the high density of elements, matrix driving is an efficient way to handle each cell individually.

In one embodiment, the control structure of the antenna system has 2 main parts: an antenna array controller for an antenna system includes drive electronics located below a wave scattering structure, and a matrix drive switch array is interleaved throughout the radiating RF array in a manner that does not interfere with the radiation. In one embodiment, the drive electronics of the antenna system comprise an off-the-shelf LCD control device used in commercial television equipment that adjusts the bias voltage of each scattering element by adjusting the amplitude or duty cycle of the AC bias signal to that element.

In one embodiment, the antenna array controller further comprises a microprocessor running software. The control structure may also include sensors (e.g., GPS receivers, three-axis compasses, three-axis accelerometers, three-axis gyroscopes, three-axis magnetometers, etc.) to provide position and orientation information to the processor. The position and orientation information may be provided to the processor by other systems in the earth station and/or may not be part of the antenna system.

More specifically, the antenna array controller controls which elements are turned off, which elements are turned on, and at which phase and amplitude level at the operating frequency. The element selectively detunes frequency operation by applying a voltage.

For transmission, the controller provides an array of voltage signals to the RF patches to create a modulation or control pattern. The control mode causes the elements to go to different states. In one embodiment, multi-state control is used, where the various elements are turned on and off to different levels, further approaching a sinusoidal control pattern, rather than a square wave (i.e., a sine wave grayscale modulation pattern). In one embodiment, some elements radiate more strongly than others, rather than some elements radiating, some do not. Variable radiation is achieved by applying certain voltage levels that adjust the dielectric constant of the liquid crystal to different amounts, thereby variably detuning the elements and making some elements radiate more strongly than others.

The focused beam generated by the array of metamaterial elements can be explained by the phenomena of constructive and destructive interference. If the individual electromagnetic waves have the same phase when they meet in free space, they add (constructive interference); if the waves meet in free space in opposite phases, they cancel each other out (destructive interference). If the slits in a slit antenna are positioned such that each successive slit is located at a different distance from the excitation point of the guided wave, the scattered wave from that element will have a different phase than the scattered wave from the previous slit. If the slits are spaced one-quarter of the guided wave wavelength, each slit will scatter waves one-quarter of the phase delay from the previous slit.

Using this array, the number of constructive and destructive interference patterns that can be generated can be increased so that, using the principles of holography, a beam can theoretically be directed in any direction plus or minus ninety degrees (90 °) from the line of sight of the aperture of the antenna array. Thus, by controlling which metamaterial units are turned on or off (i.e., by changing the pattern of which units are turned on and which units are turned off), different constructive and destructive interference patterns may be generated, and the antenna may change the direction of the main beam. The time required to turn the cells on and off determines the speed at which the beam can be switched from one location to another.

In one embodiment, the antenna system generates a steerable beam for the uplink antenna and a steerable beam for the downlink antenna. In one embodiment, the antenna system uses metamaterial technology to receive beams and decode signals from satellites and form transmit beams directed to the satellites. In one embodiment, the antenna system is an analog system, as opposed to an antenna system that employs digital signal processing to electrically form and steer beams (e.g., a phased array antenna). In one embodiment, the antenna system is considered a "surface" antenna, which is planar and relatively low, particularly as compared to conventional satellite dishes.

Fig. 7 shows a perspective view of a row of antenna elements including a ground plane and a reconfigurable resonator layer. Reconfigurable resonator layer 1230 includes an array of tunable slits 1210. The array of tunable slits 1210 can be configured to point the antenna in a desired direction. Each tunable slit can be tuned/adjusted by changing the voltage over the liquid crystal.

A control module 1280 is coupled to the reconfigurable resonator layer 1230 to modulate the array of tunable slits 1210 by varying the voltage across the liquid crystals in fig. 8A. Control module 1280 may include a field programmable gate array ("FPGA"), a microprocessor, a controller, a system on a chip (SoC), or other processing logic. In one embodiment, the control module 1280 includes logic circuitry (e.g., multiplexers) to drive the array of tunable slits 1210. In one embodiment, the control module 1280 receives data that includes specifications of the holographic diffraction pattern to be driven onto the array of tunable slits 1210. The holographic diffraction pattern may be generated in response to the spatial relationship between the antenna and the satellite such that the holographic diffraction pattern directs the downlink beam (and the uplink beam if the antenna system performs transmission) into the appropriate direction to enable communication. Although not shown in each figure, a control module similar to the control module 1280 may drive each tunable slot array described in the figures of the present disclosure.

Radio frequency ("RF") holography can also be performed using similar techniques, and when an RF reference beam encounters an RF holographic diffraction pattern, a desired RF beam can be generated. In the case of satellite communications, the reference beam is in the form of a feed wave, such as feed wave 1205 (in some embodiments approximately 20 GHz). For converting the feed wave into a radiation beam (for transmitting or receiving purposes), at the desired RF beam (target beam) and the feed waveThe interference pattern is calculated between (reference beams). The interference pattern is driven as a diffraction pattern onto the array of tunable slits 1210 so that the feed wave is "steered" to the desired RF beam (with the desired shape and direction). In other words, the feed wave encountering the holographic diffraction pattern "reconstructs" the target beam, which is formed according to the design requirements of the communication system. The holographic diffraction pattern comprises actuation of each element and passes

Calculation of where w _in Is the wave equation of the waveguide, w _out Is the wave equation of the emergent wave.

Figure 8A shows one embodiment of a tunable resonator/slit 1210. Tunable slit 1210 includes an iris/slit 1212, a radiation patch 1211, and liquid crystals 1213 disposed between iris 1212 and patch 1211. In one embodiment, the radiation patches 1211 are co-located with the iris 1212.

Figure 8B illustrates a cross-sectional view of one embodiment of a physical antenna aperture. The antenna aperture includes a ground plane 1245 and a metal layer 1236 within the iris layer 1232, the metal layer 1236 being included in a reconfigurable resonator layer 1230. In one embodiment, the antenna aperture of fig. 8B includes the plurality of tunable resonators/slots 1210 of fig. 8A. Iris/slit 1212 is defined by the opening of metal layer 1236. The feed wave (e.g., feed wave 1205 of fig. 7) may have a microwave frequency compatible with the satellite communication channel. The feed wave propagates between the ground plane 1245 and the resonator layer 1230.

The reconfigurable resonator layer 1230 also includes a gasket layer 1233 and a patch layer 1231. The gasket layer 1233 is disposed between the patch layer 1231 and the iris layer 1232. Note that in one embodiment, spacers may be substituted for gasket layer 1233. In one embodiment, the iris layer 1232 is a printed circuit board ("PCB") that includes a copper layer as the metal layer 1236. In one embodiment, iris layer 1232 is glass. The iris layer 1232 can be other types of substrates.

An opening may be etched in the copper layer to form a slot 1212. In one embodiment, iris layer 1232 is conductively coupled to another structure (e.g., a waveguide) in fig. 8B by a conductive bonding layer. Note that in embodiments, the iris layer is not conductively coupled by a conductive bonding layer, but is bordered by a non-conductive bonding layer.

The patch layer 1231 may also be a PCB including metal as the radiation patch 1211. In one embodiment, the gasket layer 1233 includes spacers 1239 that provide a mechanical standoff to define the dimension between the metal layer 1236 and the patch 1211. In one embodiment, the spacers are 75 microns, but other sizes (e.g., 3-200 millimeters) may be used. As described above, in one embodiment, the antenna aperture of fig. 8B includes multiple tunable resonators/slots, e.g., tunable resonator/slot 1210 includes patch 1211, liquid crystal 1213, and iris 1212 of fig. 8A. The cavity of the liquid crystal 1213A is defined by the spacer 1239, the iris layer 1232 and the metal layer 1236. When the cavity is filled with liquid crystal, the patch layer 1231 may be laminated over the spacer 1239 to seal the liquid crystal within the resonant layer 1230.

The voltage between the patch layer 1231 and the iris layer 1232 may be modulated to tune the liquid crystal in the gap between the patch and the slit (e.g., tunable resonator/slit 1210). Adjusting the voltage on the liquid crystal 1213 changes the capacitance of the slit (e.g., tunable resonator/slit 1210). Thus, the reactance of the slot (e.g., tunable resonator/slot 1210) can be changed by changing the capacitance. The resonant frequency of the slit 1210 is also according to the equation

In the variation, where f is the resonant frequency of the slit 1210, and L and C are the inductance and capacitance, respectively, of the slit 1210. The resonant frequency of the slot 1210 affects the radiation of energy propagating in the waveguide by the feed wave 1205. As an example, if the feed wave 1205 is 20GHz, the resonant frequency of the slot 1210 may be adjusted (by changing the capacitance) to 17GHz such that the slot 1210 does not substantially couple energy from the feed wave 1205. Alternatively, the resonant frequency of the slit 1210 may be adjusted to 20GHz such that the slit 1210 couples energy from the feed wave 1205 and radiates the energy to free space. Although the examples given are binary (fully radiated or fully finished)All non-radiative), but by voltage variation over a multi-valued range, full gray scale control of the reactance, and thus control of the resonant frequency of the slit 1210, can be achieved. Accordingly, the energy radiated from each slit 1210 may be finely controlled, so that a detailed holographic diffraction pattern may be formed by an array of tunable slits.

In one embodiment, the tunable slits of a row are spaced a distance of λ/5 from each other. Other spacings may also be used. In one embodiment, each tunable slit in one row is spaced a distance of λ/2 from the nearest tunable slit in an adjacent row, and thus the spacing of commonly used tunable slits in different rows is λ/4, although other spacings are possible (e.g., λ/5, λ/6.3). In another embodiment, each tunable slit in one row is spaced a distance λ/3 from the nearest tunable slit in an adjacent row.

Embodiments use Reconfigurable metamaterial technologies such as described in U.S. patent application No. 14/550,178 entitled "Dynamic Polarization and Coupling Control from Steerable cylindrical Fed Holographic Antenna (Dynamic Polarization and Coupling Control from a Steerable cylindrical Fed Holographic Antenna"), filed 11/21/2014, and U.S. patent application No. 14/610,502 entitled "Ridged Waveguide Fed Structures for Reconfigurable Antenna" (filed 2015 30/11).

FIGS. 9A-9D illustrate one embodiment for creating the different layers of the slit-shaped array. The antenna array includes antenna elements positioned in a loop (e.g., the example loop shown in fig. 6). Note that in this example, the antenna array has two different types of antenna elements, which are used for two different types of frequency bands.

Fig. 9A shows a portion of a first iris plate layer positioned to correspond with the slit. Referring to fig. 9A, the circles are open areas/slits in the bottom metallization of the iris substrate and are used to control the coupling of the elements to the feed (feed wave). Note that this layer is an optional layer and is not used in all designs. Figure 9B shows a portion of a second iris plate layer including slits. Fig. 9C shows a patch on a portion of a second iris plate layer. Fig. 9D shows a top view of a portion of the slot array.

Figure 10 illustrates a side view of one embodiment of a cylindrical feed antenna structure. The antenna uses a dual-layer feed structure (i.e., a two-layer feed structure) to generate inwardly propagating waves. In one embodiment, the antenna comprises a circular outer shape, although this is not required. That is, non-circular, inwardly propagating structures may be used. In one embodiment, the Antenna structure of fig. 10 includes coaxial feed, such as described in U.S. publication entitled "Dynamic Polarization and Coupling Control from Steerable cylindrical Fed Holographic Antenna (Dynamic Polarization and Coupling controlled from a Steerable cylindrical Holographic Antenna," filed 21/11/2014, published as 2015/0236412.

Referring to fig. 10, a coaxial pin 1601 is used to excite the field underneath the antenna. In one embodiment, coaxial pin 1601 is a ready-to-use 50-pin coaxial pin. The coaxial pin 1601 is coupled (e.g., bolted) to the bottom of the antenna structure, i.e., the conductive ground plane 1602.

Separated from the conductive ground plane 1602 are interstitial conductors 1603, which are inner conductors 1603. In one embodiment, conductive ground plane 1602 and gap conductor 1603 are parallel to each other. In one embodiment, the distance between ground plane 1602 and gap conductor 1603 is 0.1-0.15". In another embodiment, the distance may be λ/2, where λ is the wavelength of the wave traveling down the operating frequency.

Ground plane 1602 is separated from gap conductor 1603 via spacer 1604. In one embodiment, spacer 1604 is a foam or air-like spacer. In one embodiment, spacer 1604 comprises a plastic spacer.

On top of the gap conductor 1603 is a dielectric layer 1605. In one embodiment, the dielectric layer 1605 is plastic. The purpose of the dielectric layer 1605 is to slow down the traveling wave relative to the velocity of free space. In one embodiment, the dielectric layer 1605 slows the traveling wave by 30% relative to free space. In one embodiment, the refractive index range suitable for beamforming is 1.2-1.8, where free space, by definition, has a refractive index equal to 1. Other dielectric spacer materials (e.g., plastic) may be used to achieve this effect. It is noted that other materials than plastic may be used, as long as they achieve the desired wave-damping effect. Alternatively, a material with a distributed structure (e.g., a periodic subwavelength metal structure that can be machined or lithographically defined) can be used as dielectric 1605.

RF-array 1606 is on top of dielectric 1605. In one embodiment, the distance between gap conductor 1603 and RF-array 1606 is 0.1-0.15". In another embodiment, the distance may be λ _eff /2, wherein λ _eff Is the effective wavelength in the medium at the design frequency.

The antenna includes sides 1607 and 1608. Sides 1607 and 1608 are angled to allow the traveling wave feed from coaxial pin 1601 to propagate via reflection from the area under spacer conductor 1603 (spacer layer) to the area over spacer conductor 1603 (dielectric layer). In one embodiment, the angle of sides 1607 and 1608 is a 45 ° angle. In alternative embodiments, sides 1607 and 1608 may be replaced with a continuous radius to achieve reflection. Although fig. 10 shows a side at an angle of 45 degrees, other angles may be used to accomplish signal transmission from a lower feed to a higher feed. That is, given that the effective wavelength in the lower feed will generally be different from the upper feed, some deviation from the ideal 45 ° angle may be used to facilitate transmission from the lower feed to the upper feed. For example, in another embodiment, a 45 ° angle is replaced with a single step. A step at one end of the antenna surrounds the dielectric layer, the gap conductor and the spacer layer. The same two steps are at the other end of the layers.

In operation, when a feed wave is fed from the coaxial pin 1601, the wave propagates concentrically outward from the coaxial pin 1601 in the region between the ground plane 1602 and the spacer conductor 1603. The concentric outward waves are reflected by sides 1607 and 1608 and propagate inward in the region between the spaced conductor 1603 and the RF array 1606. Reflections from the edges of the circumference keep the waves in phase (i.e., in-phase reflections). The traveling wave is slowed by dielectric layer 1605. At this point, the traveling wave begins to interact with and excite the elements in the RF array 1606 to achieve the desired scattering.

To terminate the traveling wave, a terminal 1609 is included in the antenna at the geometric center of the antenna. In one embodiment, the terminals 1609 include pin terminals (e.g., 50 Ω pins). In another embodiment, terminal 1609 includes an RF absorber that terminates unused energy to prevent the unused energy from being reflected back through the feed structure of the antenna. These may be used on top of the RF array 1606.

Fig. 11 shows another embodiment of an antenna system with an outgoing wave. Referring to fig. 11, two ground planes 1610 and 1611 are substantially parallel to each other with a dielectric layer 1612 (e.g., plastic layer, etc.) between the ground planes. An RF absorber 1619 (e.g., a resistor) couples the two ground planes 1610 and 1611 together. Coaxial pin 1615 (e.g., 50 Ω) feeds the antenna. RF array 1616 is on top of dielectric layer 1612 and ground plane 1611.

In operation, a feed wave is fed through the coaxial pin 1615 and propagates concentrically outward and interacts with the elements of the RF array 1616.

The cylindrical feeding in the two antennas of fig. 10 and 11 improves the service angle of the antennas. In one embodiment, the angle of service of the antenna system in all directions is seventy-five degrees (75 °) from the aperture line of sight, rather than a service angle of plus or minus forty-five degrees azimuth (+ -45 ° Az) and plus or minus twenty-five degrees elevation (+ -25 ° El). As with any beam forming antenna consisting of a number of individual radiators, the gain of the overall antenna is dependent on the gains of the constituent elements, which are themselves angle dependent. When using ordinary radiating elements, the overall antenna gain typically decreases as the beam is further out of the line of sight of the aperture. At 75 degrees off the aperture line of sight, a significant gain drop of about 6dB is expected.

Embodiments of antennas with cylindrical feeds solve one or more problems. These problems include: the feed structure is greatly simplified compared to antennas fed with corporate divider networks, thus reducing the total volume of antenna and antenna feed required; by maintaining high beam performance with coarser control (extending all the way to simple binary control), sensitivity to manufacturing and control errors is reduced; providing a more favorable side mode compared to a straight feed, since a cylindrically directed feed wave will produce spatially different sides in the far field; and allows dynamic polarization, including allowing left-hand circular, right-hand circular, and linear polarization, without the need for polarizers.

Wave scattering element array

RF array 1606 of fig. 10 and RF array 1616 of fig. 11 comprise a wave scattering subsystem that includes a set of patch antennas (i.e., scatterers) as radiators. The set of patch antennas includes an array of scattering metamaterial elements.

In one embodiment, each scattering element in the antenna system is part of a unit cell comprised of a lower conductor, a dielectric substrate, and an upper conductor that embeds a complementary electrically induced capacitive resonator ("complementary electrical LC" or "CELC") that is etched or deposited on the upper conductor.

In one embodiment, liquid Crystal (LC) is injected into the gap around the scattering element. Liquid crystal is encapsulated in each cell and separates the lower conductor associated with the slit from the upper conductor associated with its patch. The liquid crystal has a dielectric constant that is a function of the orientation of the molecules that make up the liquid crystal, and the orientation of the molecules (and thus the dielectric constant) can be controlled by adjusting the bias voltage on the liquid crystal. With this characteristic, the liquid crystal acts as an on/off switch for transmitting energy from the guided wave to the CELC. When open, the CELC emits electromagnetic waves like an electrically small dipole antenna.

Controlling the thickness of the LC may improve beam switching speed. A fifty percent (50%) reduction in the gap between the lower and upper conductors (thickness of the liquid crystal) results in a four-fold increase in speed. In another embodiment, the thickness of the liquid crystal produces a beam switching speed of about 14 milliseconds (14 ms). In one embodiment, the LC is doped in a manner well known in the art to improve responsiveness such that seven milliseconds (7 ms) requirements can be met.

The CELC elements respond to the applied magnetic field parallel to the plane of the CELC elements and perpendicular to the CELC gap filler. When a voltage is applied to the liquid crystals in the metamaterial scattering cell, the magnetic field component of the guided wave induces magnetic excitation of the CELC, which in turn generates an electromagnetic wave of the same frequency as the guided wave.

The phase of the electromagnetic wave produced by a single CELC can be selected by the location of the CELC on the guided wave vector. The waves generated by each cell are in phase with the guided waves parallel to the CELC. Since the CELC is smaller than the wavelength, the output wave has the same phase as the phase of the guided wave when passing under the CELC.

In one embodiment, the feed geometry of the cylindrical antenna system allows the CELC elements to be positioned at a forty-five degree (45 °) angle to the vector of the waves in the wave feed. Such a position of the element enables control of the polarization of free space waves generated from or received by the element. In one embodiment, the CELCs are arranged with a spacing between elements that is less than the free space wavelength of the operating frequency of the antenna. For example, if there are four scattering elements per wavelength, the elements in a 30GHz transmit antenna will be about 2.5mm (i.e., 1/4 of the 10mm free-space wavelength of 30 GHz).

In one embodiment, CELC is implemented with a patch antenna comprising co-located patches on a slot with liquid crystal in between. In this respect, the metamaterial antenna acts like a slit (scattering) waveguide. With a slot waveguide, the phase of the output wave depends on the position of the slot relative to the guided wave.

Unit placement

In one embodiment, the antenna elements are placed on a cylindrical feed antenna aperture in a manner that allows for system matrix driving circuitry. The placement of the cells includes the placement of transistors for matrix driving. Figure 12 illustrates one embodiment of the placement of the matrix drive circuitry relative to the antenna elements. Referring to fig. 12, a Row controller 1701 is coupled to transistors 1711 and 1712 via Row selection signals Row1 and Row2, respectively, and a Column controller 1702 is coupled to transistors 1711 and 1712 via a Column selection signal Column 1. Transistor 1711 is also coupled to antenna element 1721 via a connection to patch 1731, while transistor 1712 is coupled to antenna element 1722 via a connection to patch 1732.

In the initial method of implementing the matrix driving circuit on a cylindrical feed antenna, the cell is placed in an irregular grid, and two steps are performed. In a first step, the cells are placed on concentric rings, each cell being connected to a transistor, which is placed beside the cell and acts as a switch to drive each cell individually. In a second step, the matrix driving circuit is set up to connect each transistor with a unique address as required by the matrix driving method. Since the matrix drive circuit is built up of rows and columns of traces (similar to an LCD), but the cells are placed on a ring, there is no systematic way to assign a unique address to each transistor. This mapping problem results in a complex circuit covering all transistors and results in a large increase in the number of physical traces that complete the routing. Due to the high density of the cells, these traces interfere with the RF performance of the antenna due to coupling effects. In addition, due to the complexity and high packing density of traces, routing of traces cannot be done by commercially available layout tools.

In one embodiment, the matrix drive circuit is predefined before placing the cells and transistors. This ensures that the minimum number of traces required to drive all cells, each with a unique address. This strategy reduces the complexity of the driving circuitry and simplifies routing, thereby improving the RF performance of the antenna.

More specifically, in one approach, in a first step, cells are placed on a regular rectangular grid consisting of rows and columns that describe the unique address of each cell. In a second step, the cells are grouped and transformed into concentric circles while maintaining their addresses and connections to the rows and columns defined in the first step. The goal of this conversion is not only to place the cells on the rings, but also to keep the distance between the cells and the distance between the rings constant over the entire aperture. To achieve this goal, there are several ways to group units.

In one embodiment, the placement and unique addressing in the matrix drive is achieved using TFT encapsulation. Fig. 13 illustrates one embodiment of a TFT package. Referring to fig. 13, the TFT and holding capacitor 1803 are shown with input and output ports. There are two input ports connected to trace 1801 and two output ports connected to trace 1802 to connect the TFTs together using rows and columns. In one embodiment, the rows and columns of traces are crossed at a 90 ° angle to reduce and minimize coupling between the rows and column traces. In one embodiment, the traces for the rows and columns are on different layers.

Examples of full-duplex communication systems

In another embodiment, the combined antenna aperture is used in a full duplex communication system. Fig. 14 is a block diagram of another embodiment of a communication system having simultaneous transmit and receive paths. Although only one transmit path and one receive path are shown, the communication system may include more than one transmit path and/or more than one receive path.

Referring to fig. 14, the antenna 1401 comprises two spatially interleaved antenna arrays that are independently operable to transmit and receive simultaneously at different frequencies, as described above. In one embodiment, the antenna 1401 is coupled to a duplexer 1445. The coupling may be achieved by one or more feed networks. In one embodiment, in the case of a radially fed antenna, the duplexer 1445 combines both signals, and the connection between the antenna 1401 and the duplexer 1445 is a single broadband feed network, which can carry both frequencies.

The duplexer 1445 is coupled to a low noise block down converter (LNB) 1427, which low noise block down converter (LNB) 1427 performs noise filtering functions and down conversion and amplification functions in a manner well known in the art. In one embodiment, LNB 1427 is in an outdoor unit (ODU). In another embodiment, LNB 1427 is integrated into the antenna apparatus. LNB 1427 is coupled to modem 1460, and modem 1460 is coupled to computing system 1440 (e.g., a computer system, modem, etc.).

Modem 1460 includes an analog-to-digital converter (ADC) 1422 coupled to LNB 1427 to convert received signals output from duplexer 1445 to a digital format. Once converted to digital format, the signal is demodulated by a demodulator 1423 and decoded by a decoder 1424 to obtain encoded data on the received wave. The decoded data is then sent to controller 1425, which controller 1425 sends to computing system 1440.

The modem 1460 also includes an encoder 1430, the encoder 1430 encoding data to be transmitted from the computing system 1440. The encoded data is modulated by a modulator 1431 and then converted to analog by a digital-to-analog converter (DAC) 1432. The analog signal is then filtered by a BUC (up-conversion and high-pass amplifier) 1433 and provided to one port of a duplexer 1445. In one embodiment, the BUC 1433 is in an outdoor unit (ODU).

A duplexer 1445, operating in a manner well known in the art, provides a transmit signal to the antenna 1401 for transmission.

A controller 1450 controls the antenna 1401, the antenna 1401 comprising two arrays of antenna elements on a single combined physical aperture.

The communication system will be modified to include the combiner/winder described above. In such a case, the combiner/winder is after the modem but before the BUC and LNB.

Note that the full duplex communication system shown in fig. 14 has many applications including, but not limited to, internet communications, vehicle communications (including software updates), and the like.

Some exemplary embodiments are described herein.

Example 1 is an antenna, comprising an aperture having a plurality of Radio Frequency (RF) radiating antenna elements, wherein each antenna element of the plurality of RF radiating antenna elements comprises an iris slit opening and an electrode above the iris slit opening; a plurality of drive transistors coupled to the plurality of antenna elements; and a plurality of storage capacitors, each coupled to an electrode of one of the plurality of antenna elements, wherein the aperture comprises at least one of: a driving transistor of an antenna element is located under an electrode of the antenna element; the storage capacitor of one antenna element is located under the electrode of the antenna element; and a metal route of the first voltage to the one antenna element overlaps a common voltage route routing a common voltage to the one antenna element to form a storage capacitor in the overlap region.

Example 2 is the antenna of example 1, optionally including the electrode comprising a patch.

Example 3 is the antenna of example 1, which optionally includes the metal routing including a drain metal routing coupling one of the plurality of storage capacitors to the electrode.

Example 4 is the antenna of example 3, optionally comprising the drain metal routing above or below the common voltage routing.

Example 5 is the antenna of example 3, which optionally includes the overlap region providing a first capacitance that combines with a second capacitance of the storage capacitor to provide a capacitance of one of the antenna elements, wherein one or both of a width of the drain metal layer and a width of the common voltage route are set to obtain the first capacitance.

Example 6 is the antenna of example 1, optionally including a width of the overlap region being greater under the electrode than outside the electrode.

Example 7 is the antenna of example 1, optionally comprising the drive transistor of one antenna element positioned below an electrode of an antenna element having a storage capacitor of the one antenna element.

Example 8 is the antenna of example 1, which optionally includes the drive transistor of one antenna element being located below an electrode of the antenna element and the storage capacitor of the one antenna element being located outside the electrode of the antenna element.

Example 9 is the antenna of example 1, optionally comprising the drive transistor of one antenna element being located below an electrode of the antenna element, the first storage capacitor of one antenna element being located below the electrode of the antenna element, and the second storage capacitor of one antenna element being located outside the electrode of the antenna element.

Example 10 is the antenna of example 1, which optionally includes the electrode being part of a patch structure having a patch and a patch substrate, and further wherein the storage capacitor is formed below the electrode and between a patch metal layer of the patch structure and the patch substrate.

Example 11 is the antenna of example 10, which optionally includes adjusting the capacitance under the patch by adjusting the common voltage metal layer.

Example 12 is the antenna of example 1, which optionally includes the electrode being part of a patch structure having a patch and a patch substrate, and further wherein the drive transistor comprises a TFT, and wherein at least one TFT is formed beneath the patch structure and between the patch metal layer and the patch substrate of the patch structure.

Example 13 is an antenna, comprising: a plurality of Radio Frequency (RF) radiating antenna elements, wherein each antenna element of the plurality of RF radiating antenna elements comprises an iris slit opening and an electrode over the iris slit opening; and a plurality of drive transistors, each drive transistor coupled to one of the plurality of antenna elements, wherein one or more metal routing lines between pairs of drive transistors pass through one or more of the RF radiating antenna elements.

Example 14 is the antenna of example 13, which optionally includes each drive transistor having drain and gate metal lines coupled to its source and gate, respectively, the drain metal line being coupled to an electrode of the RF radiating antenna element, wherein the one or more metal routing lines include one or more of the source metal line and the gate metal line.

Example 15 is the antenna of example 13, which optionally includes one or more metal routing lines comprising a common voltage route.

Example 16 is the antenna of example 13, optionally comprising one or more metal routing lines along a major axis of the at least one RF element.

Example 17 is the antenna of example 16, which optionally includes the one or more metal routing lines comprising parallel routing lines that are symmetric with respect to a major axis of the at least one RF element.

Example 18 is the antenna of example 13, which optionally includes portions of the one or more metal routing lines formed on a metal layer on the substrate, the metal layer coupled between the electrode and the substrate.

Example 19 is the antenna of example 18, which optionally includes the electrode being a patch electrode and the substrate being a patch substrate.

Example 20 is the antenna of example 1, optionally comprising a dielectric between the patch electrode and the metal routing line to reduce parasitic capacitance between the patch electrode and the metal routing line.

Example 21 is the antenna of example 13, optionally comprising the metal routing wire being narrower when proximate to the electrode than when not proximate to the electrode.

Example 22 is the antenna of example 13, optionally comprising a via to connect the drain metal layer of the drive transistor to an electrode of at least one antenna element in an area outside an area above its respective iris slit opening.

Example 23 is an antenna, comprising: a plurality of RF radiating antenna elements; and a plurality of structures coupled to the plurality of RF radiating antenna elements, each structure having a drive transistor coupled to the storage capacitor to drive the plurality of antenna elements, wherein each structure of the plurality of structures includes a plurality of drain terminals.

Example 24 is the antenna of example 23, which optionally includes that the drive transistor is a TFT.

Example 25 is the antenna of example 23, optionally comprising, only one of the plurality of drain terminals coupled to the one or more RF elements on one or more different loops of the RF antenna element.

Example 26 is the antenna of example 23, which optionally includes a drain line coupled to one of the plurality of drain terminals of one of the plurality of structures crossing a gate line coupled to a drive transistor of the one structure.

Example 27 is the antenna of example 23, optionally comprising a drain line coupled to one of the plurality of drain terminals of one of the plurality of structures not crossing a gate line or a source line coupled to a drive transistor of the one structure.

Example 28 is the antenna of example 23, optionally comprising a drain line coupled to one of the plurality of drain terminals of one of the plurality of structures exiting the one structure in an opposite direction from a source line coupled to a drive transistor of the one structure.

Example 29 is the antenna of example 23, which optionally includes that the structure of the plurality of structures is aligned with a route that is tangent to a local loop of the antenna element.

Example 30 is the antenna of example 29, optionally comprising one or more connections of routing lines of the one or more TFT/storage capacitor structures aligned with a route tangent to a partial loop of elements.

Example 31 is the antenna of example 29, optionally comprising one or more connections of routing lines of the one or more TFT/storage capacitor structures aligned with a route through a tangent of a partial loop of the element.

Some portions of the detailed descriptions above are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

The present invention also relates to apparatus for performing the operations herein. The apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. In addition, the present invention is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the invention as described herein.

A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory ("ROM"); random access memory ("RAM"); a magnetic disk storage medium; an optical storage medium; flash memory devices, and the like.

Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which in themselves recite only those features regarded as essential to the invention.

Claims (31)

1. An antenna, comprising:

pore diameter of

A plurality of Radio Frequency (RF) radiating antenna elements, wherein each antenna element of the plurality of RF radiating antenna elements comprises an iris slit opening and an electrode located above the iris slit opening;

a plurality of drive transistors coupled to the plurality of antenna elements; and

a plurality of storage capacitors, each storage capacitor coupled to an electrode of one of the plurality of antenna elements, wherein the aperture comprises at least one of:

the drive transistor of said one antenna element being located below said electrode of said antenna element;

the storage capacitor of said one antenna element is located below said electrode of said antenna element; and

a metal route of a first voltage to the one antenna element overlaps a common voltage route routing the common voltage to the one antenna element to form a storage capacitor within an overlap region.

2. The antenna of claim 1, wherein the electrode comprises a patch.

3. The antenna defined in claim 1 wherein the metal routing comprises drain metal routing that couples a storage capacitor of the plurality of storage capacitors to the electrode.

4. The antenna of claim 3, wherein the drain metal route is above or below the common voltage route.

5. The antenna defined in claim 3 wherein the overlap region provides a first capacitance that combines with a second capacitance of a storage capacitor to provide a capacitance of the one antenna element, wherein one or both of a width of the drain metal layer and a width of the common voltage route are set to obtain the first capacitance.

6. The antenna of claim 1, wherein the width of the overlap region is greater under the electrode than outside the electrode.

7. The antenna of claim 1, wherein the drive transistor of said one antenna element is located below an electrode of said antenna element having the storage capacitor of said one antenna element.

8. The antenna of claim 1, wherein the drive transistor of the one antenna element is located below an electrode of the one antenna element, and the storage capacitor of the one antenna element is located outside the electrode of the one antenna element.

9. The antenna of claim 1, wherein the drive transistor of the one antenna element is located below an electrode of the one antenna element, the first storage capacitor of the one antenna element is located below the electrode of the one antenna element, and the second storage capacitor of the one antenna element is located outside the electrode of the one antenna element.

10. The antenna defined in claim 1 wherein the electrode is part of a patch structure having a patch and a patch substrate and further wherein the storage capacitor is formed beneath the electrode and between a patch metal layer of the patch structure and the patch substrate.

11. The antenna of claim 10, wherein the capacitance under the patch is adjusted by adjusting a common voltage metal layer.

12. The antenna defined in claim 1 wherein the electrode is part of a patch structure having a patch and a patch substrate and further wherein the drive transistor comprises a TFT and wherein at least one TFT is formed beneath the patch structure and between a patch metal layer of the patch structure and the patch substrate.

13. An antenna, comprising:

a plurality of Radio Frequency (RF) radiating antenna elements, wherein each antenna element of the plurality of RF radiating antenna elements comprises an iris slit opening and an electrode located above the iris slit opening;

a plurality of drive transistors, each drive transistor coupled to one of the plurality of antenna elements, wherein one or more metal routing lines between pairs of drive transistors pass through one or more RF radiating antenna elements.

14. The antenna defined in claim 13 wherein each drive transistor has a drain metal line and a gate metal line coupled to a source and a gate of each drive transistor, respectively, the drain metal line being coupled to an electrode of the RF radiating antenna element, wherein the one or more metal routing lines include one or more of the source metal line and the gate metal line.

15. The antenna defined in claim 13 wherein the one or more metal routing lines comprise a common voltage route.

16. The antenna of claim 13, wherein the one or more metal routing lines are along a major axis of the at least one RF element.

17. The antenna of claim 16, wherein the one or more metal routing lines comprise parallel routing lines that are symmetric with respect to a major axis of the at least one RF element.

18. The antenna defined in claim 13 wherein a portion of one or more metal routing lines are formed on a metal layer on a substrate that is coupled between the electrode and the substrate.

19. The antenna defined in claim 18 wherein the electrode is a patch electrode and the substrate is a patch substrate.

20. The antenna defined in claim 19 further comprising a dielectric between the patch electrode and the metal routing line to reduce parasitic capacitance between the patch electrode and the metal routing line.

21. The antenna of claim 13, wherein the metal routing lines are narrower proximate the electrode than not proximate the electrode.

22. The antenna defined in claim 13 further comprising vias to connect the drain metal layer of the drive transistor to the electrodes of the at least one antenna element in areas that are outside the area above its respective iris slit opening.

23. An antenna, comprising:

a plurality of RF radiating antenna elements; and

a plurality of structures coupled to the plurality of RF radiating antenna elements, each structure having a drive transistor coupled to a storage capacitor to drive a plurality of antenna elements, wherein each structure of the plurality of structures includes a plurality of drain terminals.

24. The antenna of claim 23, wherein the drive transistor is a TFT.

25. The antenna defined in claim 23 wherein only one of the plurality of drain terminals is coupled to one or more RF elements on one or more different loops of RF antenna elements.

26. The antenna defined in claim 23 wherein a drain line coupled to one of the plurality of drain terminals of one of the structures crosses a gate line coupled to a drive transistor of the one structure.

27. The antenna of claim 23, wherein a drain line coupled to one of the plurality of drain terminals of one of the plurality of structures does not cross a gate line or a source line of a drive transistor coupled to the one structure.

28. The antenna defined in claim 23 wherein a drain line coupled to one of the plurality of drain terminals of one of the structures leaves the one structure in an opposite direction from a source line coupled to a drive transistor of the one structure.

29. The antenna defined in claim 23 wherein a structure of the plurality of structures is aligned with a route that is tangent to a local loop of antenna elements.

30. The antenna of claim 29, wherein one or more connections of the routing lines of one or more TFT/storage capacitor structures are aligned with a route tangent to a local loop of elements.

31. The antenna of claim 29 wherein one or more connections of the routing lines of one or more TFT/storage capacitor structures are aligned with a route through a tangent of a partial loop of the element.

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