CN115664901A - Signal equalization circuit based on timing recovery loop - Google Patents
Signal equalization circuit based on timing recovery loop Download PDFInfo
- Publication number
- CN115664901A CN115664901A CN202211227055.7A CN202211227055A CN115664901A CN 115664901 A CN115664901 A CN 115664901A CN 202211227055 A CN202211227055 A CN 202211227055A CN 115664901 A CN115664901 A CN 115664901A
- Authority
- CN
- China
- Prior art keywords
- tap
- signal
- filter
- taps
- timing recovery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000011084 recovery Methods 0.000 title claims abstract description 81
- 238000001514 detection method Methods 0.000 claims abstract description 65
- 230000003044 adaptive effect Effects 0.000 claims abstract description 36
- 230000001105 regulatory effect Effects 0.000 claims abstract description 30
- 230000001276 controlling effect Effects 0.000 claims abstract description 28
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 18
- 238000012544 monitoring process Methods 0.000 claims abstract description 5
- 238000005070 sampling Methods 0.000 claims description 30
- 238000012545 processing Methods 0.000 claims description 12
- 238000011217 control strategy Methods 0.000 claims description 6
- 238000001914 filtration Methods 0.000 claims description 3
- 230000010355 oscillation Effects 0.000 claims description 3
- 239000000306 component Substances 0.000 description 25
- 238000000034 method Methods 0.000 description 25
- 238000010586 diagram Methods 0.000 description 10
- 238000001228 spectrum Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000008859 change Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- PMOWTIHVNWZYFI-WAYWQWQTSA-N cis-2-coumaric acid Chemical compound OC(=O)\C=C/C1=CC=CC=C1O PMOWTIHVNWZYFI-WAYWQWQTSA-N 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Abstract
The embodiment of the invention discloses a signal equalization circuit based on a timing recovery loop, which comprises: the digital demodulation module, the adaptive equalizer, the tap position detection and mode control component; the tap position detection and mode control component is used for monitoring whether the position information of all taps in the adaptive equalizer drifts or not, and when the tap position drift is monitored, a control signal for stabilizing the drifted tap position is generated, wherein the control signal is used for regulating and controlling the bandwidth of a timing recovery loop in the digital demodulation module and/or regulating and controlling the bandwidth of a phase tracker, so that the drifted tap position is stable. The signal equalization circuit improves the integral anti-interference capability of the timing recovery and channel equalization circuit by adjusting the phase tracker and the timing recovery loop.
Description
Technical Field
The embodiment of the invention relates to a wireless signal transmission technology, in particular to a signal equalization circuit based on a timing recovery loop.
Background
A typical wireless signal transmission receiver first converts a high-frequency signal into an intermediate-frequency signal by using a tuner and a down converter, samples the intermediate-frequency signal by using an analog-to-digital converter (ADC), and then recovers the transmitted digital signal by performing subsequent digital signal processing.
The digital signal processing of the receiver mainly comprises timing recovery, carrier recovery, phase tracking, channel equalization and the like.
Since sampling clocks used by a transmitting end and a receiving end of wireless transmission are different in frequency and phase, the synchronization of the frequency and phase of clock oscillators at the transmitting end and the receiving end needs to be completed, and the process is called timing recovery of a transmitted signal. The timing recovery aims to eliminate the frequency difference and the phase difference between clock oscillators at the transmitting end and the receiving end so as to complete the synchronization of the clocks at the transmitting end and the receiving end. Completing timing recovery will cause the received signal to be sampled at the optimum point in time sampling.
In order to complete timing recovery, the prior scheme needs the assistance of a synchronization signal, and the sideband pilot signal is used for completing carrier recovery and timing recovery of a receiver, which are recommended schemes of a plurality of wireless digital transmission systems.
However, the system using the sideband detection algorithm and the pilot signal for timing recovery is usually greatly affected by strong multipath signals, the signal spectrum may fluctuate, and even the pilot signal may be greatly weakened, which affects the effective implementation of timing recovery.
In addition, if strong single-frequency interference occurs on the sideband of the signal, a certain residual timing error still exists after the timing recovery loop using sideband detection is locked, so that the signal after carrier recovery and timing recovery is completed, and subsequent phase tracking and channel equalization are adversely affected.
Therefore, how to avoid the above problems and improve the stability and interference rejection of the phase tracking and channel equalization circuit is a technical problem that needs to be solved urgently at present.
Disclosure of Invention
To solve the problems in the prior art, at least one embodiment of the present invention provides a signal equalization circuit based on a timing recovery loop.
In a first aspect, an embodiment of the present invention provides a signal equalization circuit based on a timing recovery loop, including:
the digital demodulation module, the adaptive equalizer, the tap position detection and mode control component;
the digital demodulation module is used for sampling, demodulating and synchronously processing the received modulation signals;
the adaptive equalizer is used for equalizing the signal output by the digital demodulation module;
the tap position detection and mode control component is used for monitoring whether the position information of all taps in the adaptive equalizer drifts or not, and when the tap position drift is monitored, generating a control signal for stabilizing the drifted tap position, wherein the control signal is used for regulating and controlling the bandwidth of a timing recovery loop in a digital demodulation module, and/or is used for regulating and controlling the bandwidth of a phase tracker or switching off the whole phase tracker, so that the drifted tap position is stable.
Optionally, the tap position detection and mode control assembly is specifically configured to
After the self-adaptive equalizer finishes convergence on the signal transmitted by the digital demodulation module, reading the position information of all taps in a feedforward equalization filter in the self-adaptive equalizer at the current moment;
reading the position information of all taps in the feedforward equalization filter at the current moment at intervals of a first preset time period;
determining whether all taps in the feedforward equalization filter drift or not based on the position information of the current moment after a first preset time period and the position information after convergence;
if yes, generating a control signal for stabilizing the drifting tap position;
otherwise, repeatedly reading the position information of all taps in the feedforward equalization filter at the current moment at intervals of a first preset time period and judging again.
Optionally, the tap position detection and mode control component is further configured to generate a control signal for stabilizing the shifted tap position;
reading the position information of all taps of the feedforward equalizing filter in the self-adaptive equalizer at the current moment again at intervals of a second preset time period;
comparing the position information of the tap after the second preset time period with the position information of the tap before the second preset time period to determine whether the tap drifts;
if not, determining that the tap position in the feedforward equalization filter is in a stable state;
otherwise, generating another control signal for stabilizing the drifted tap position, wherein the other control signal is used for regulating and controlling the bandwidth of a timing recovery loop in the digital demodulation module and/or regulating and controlling the bandwidth of the phase tracker so as to stabilize the drifted tap position;
the second preset time period is greater than or equal to the first preset time period.
Optionally, the tap position detection and mode control component is configured to generate a control signal for stabilizing a shifted tap position, and includes:
the tap position detection and mode control component generates a control signal for stabilizing a drifting tap position according to a predefined drift control strategy;
the drift control strategy comprises:
when the drift is left drift and the drift amount is smaller than a first threshold value, generating a first control signal, wherein the first control signal is used for regulating and controlling an integral term coefficient K of a timing recovery loop in the digital demodulation module I And direct item coefficient K L ；
When the drift is right drift and the drift amount is less than a first threshold value, generating a second control signal, wherein the second control signal is used for regulating and controlling an integral term coefficient K of a loop filter in the phase tracker I And direct item coefficient K L 。
Optionally, the tap position detection and mode control assembly comprises:
a tap value register reading interface for reading the position information of all taps of the feedforward equalizing filter in the adaptive equalizer;
a main tap position judger for acquiring main tap positions in the position information of all taps;
a main tap position detector for detecting whether the main tap position drifts over time;
and the mode adjustment controller is used for sending out a control signal for regulating and controlling the bandwidth of a timing recovery loop in the digital demodulation module and/or regulating and controlling the bandwidth of the phase tracker.
Optionally, the digital demodulation module includes:
the ADC sampling unit is used for sampling the received modulation signal;
the mixer is used for demodulating the sampling signal of the ADC sampling unit to obtain a baseband signal;
a matched filter for filtering the baseband signal to output;
the timing recovery loop is used for detecting timing errors in the signals output by the matched filter and outputting the detection results to the ADC sampling unit so that the ADC sampling unit adjusts the sampling frequency based on the detection results;
the carrier recovery loop is used for detecting carrier frequency errors in the signals output by the matched filter and outputting the detection result to the frequency mixer so that the frequency mixer adjusts the local oscillation frequency of the frequency mixer based on the detection result;
the timing recovery loop is further configured to receive a control signal output by the tap position detection and mode control component, and is configured to adjust a bandwidth of the timing recovery loop.
Optionally, the adaptive equalizer comprises:
the feedforward equalization filter is used for performing equalization compensation on forward multipath of a channel in the output signal of the digital demodulation module to obtain an input equalization compensation signal;
the phase tracker is used for tracking and compensating residual phase errors which do not obtain the balanced compensation signals in the output signals of the digital demodulation module;
the decision device is used for deciding the output value of the adaptive equalizer;
the feedback equalization filter is used for performing equalization compensation on the backward multipath remained in the signal output by the decision device;
the detection end of the tap position detection and mode control component is connected with the feedforward equalization filter, and monitors whether the positions of all taps in the feedforward equalization filter continuously drift or not;
and the phase tracker receives a control signal output by the tap position detection and mode control component and is used for regulating and controlling the bandwidth of a loop filter in the phase tracker or switching off the phase tracker.
Optionally, when the feedforward equalization filter is a feedforward equalization filter with N-stage taps, N is a natural number greater than or equal to 256;
the N-tap feed-forward equalization filter comprises: a register;
initial position information of each tap in the N-level taps is stored in the register; and the main tap in the N-level taps is preset;
the tap value register reading interface is used for reading the position information of all taps in the register at the current moment after the self-adaptive equalizer converges, the main tap position judger acquires the position information of the main tap in all the taps at the current moment, the main tap position detector determines whether the tap drifts or not based on the position information and the initial position information of the main tap at the current moment, and if the tap drifts, the mode adjustment controller sends out the control signal.
In a second aspect, an embodiment of the present invention provides a receiver, including: a signal equalization circuit based on a timing recovery loop as described in any of the first aspect above. .
Therefore, in at least one embodiment of the embodiments of the present invention, the bandwidth of the timing recovery loop and the phase tracker is adjusted in time by detecting the change of the position of the main tap of the feedforward equalization filter in the adaptive equalizer, so as to overcome the influence of the single-frequency wave interference on the receiver system.
In addition, the signal equalization circuit can also overcome the influence of other interference sources on a receiver system by adjusting the bandwidths of the phase tracker and the timing recovery loop aiming at the drift of the tap position of a feedforward equalization filter in the self-adaptive equalizer caused by the influence of other interference on the timing recovery loop, and the stability and the anti-interference capability of the phase tracking and channel equalization circuit are improved.
It can be understood that, the tap coefficient of the feedforward equalization filter for channel equalization is monitored in real time through the tap position detection and mode control component, and when the main tap position of the feedforward equalization filter continuously moves forwards or backwards along with time, the judgment and feedback are carried out in time, for example, the bandwidth of a timing recovery loop can be adjusted first, and then the bandwidth of a phase tracker is adjusted or turned off; whether the main tap of the feedforward equalization filter stops moving or not is observed in time after adjustment at every time, so that the phenomenon that an equalizer fails due to the fact that the main tap drifts to the boundary of the feedforward equalization filter and crosses the boundary is avoided, the stability of the circuit is improved, and the anti-interference capacity of the circuit is improved. The method is easy to realize and has obvious effect in practical application.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic diagram of a signal spectrum without single frequency interference;
FIG. 2 is a schematic diagram of a signal spectrum with a sideband portion disturbed by a single frequency wave;
fig. 3 is a schematic structural diagram of a signal equalization circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a signal equalization circuit according to another embodiment of the present invention;
FIG. 5 is a flow chart illustrating a data demodulation process;
FIG. 6 is a schematic diagram of a tap structure of a feed forward equalization filter;
FIG. 7 is a schematic diagram of main tap drift for a feed forward equalization filter;
FIG. 8 is a block diagram of a tap position detection and mode control assembly;
fig. 9 is a block diagram of a loop filter in a timing recovery loop or phase tracker.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
In digital wireless communication, a digital receiver in a digital receiving system performs digital sampling (e.g., ADC sampling) on a received analog bandpass intermediate frequency modulation signal (usually a Pulse Amplitude Modulation (PAM) signal), performs spectrum shifting through a digital mixer (e.g., a mixer shown in fig. 4) to obtain a digital baseband signal, and then performs corresponding digital signal processing. It will be appreciated that the input to the digital receiver is an intermediate frequency signal, which after passing through a digital mixer in the digital receiver is referred to as a baseband signal.
Channel equalization is also an important component of a digital receiving system, can compensate for the influence of multipath interference on a signal transmission channel, can eliminate baseband intersymbol interference caused by channel interference, and is an indispensable key circuit for guaranteeing performance in a digital receiver.
At present, channel equalization is usually implemented by using an adaptive equalizer, which is an adaptive filter with several hundred taps, and the tap weight coefficients of the filter are adaptively adjusted by using a certain error calculation method, such as the least mean square error algorithm (LMS) that is widely used, to complete convergence of the adaptive equalizer.
Adaptive equalizers typically employ an architecture of a feed-forward equalization filter, a feedback equalization filter, and a phase tracker, where the values of the coefficients of the feed-forward equalization filter, or filter tap weights, are initialized by presetting a main tap value.
In a wireless channel environment interfered by a single frequency wave, the stability of a receiver can be influenced after the sideband of a signal is damaged, a timing recovery circuit of a receiver system is interfered, so that a certain timing error can be remained, the error can influence a subsequent channel equalization circuit, and in an adaptive equalizer adopting a phase tracker, the whole tap position of a feedforward equalization filter can be caused to move towards the boundary of the feedforward equalization filter.
Fig. 1 is a schematic diagram of the frequency spectrum of a wireless transmitted signal, which may be a Quadrature Amplitude Modulation (QAM) signal or a Vestigial Sideband (VSB) signal, which, when demodulated, typically uses the upper and lower sidebands of the signal to achieve timing synchronization at the receiver, and corresponding algorithms include the Gardner algorithm and the M & M algorithm, as well as the digital filtered square timing recovery algorithm, etc., and thus adversely affects timing synchronization if the sidebands of the modulated signal are disturbed. Meanwhile, the transmitted signal is viewed on the frequency spectrum, and a pilot signal for assisting synchronization can be arranged at the upper sideband or the lower sideband. The pilot signal may be synchronized by an error detection algorithm of the timing recovery loop with a completion timing clock.
Fig. 2 is a frequency spectrum of a wireless signal subjected to single-frequency interference at a lower sideband of a signal spectrum, where a is a representation of the single-frequency interference on the frequency spectrum. Due to the existence of the single-frequency interference, after timing recovery of a receiver reaches timing synchronization, a certain residual timing deviation still exists, the error affects a subsequent channel equalization circuit, in an adaptive equalizer adopting a phase tracker, the tap position of a feedforward equalization filter in the adaptive equalizer can be integrally moved to the boundary of the filter, once a main tap of the feedforward equalization filter crosses the boundary, the equalizer can be disabled, and the failure of the whole receiver can be caused.
Therefore, aiming at single-frequency wave interference in a channel, an error detection algorithm of a timing recovery loop is sensitive to the single-frequency interference in a signal spectrum sideband, and certain timing error residue can be caused. Typically, all taps of the feed forward equalization filter are moved synchronously, so monitoring the main tap position can represent a change in the position of each of all taps.
Fig. 3 is a schematic structural diagram of a signal equalization circuit, and the signal equalization circuit of this embodiment includes a digital demodulation module, an adaptive equalizer, and a tap position detection and mode control component.
The digital demodulation module is used for sampling, demodulating and synchronously processing the received modulation signals; the adaptive equalizer is used for equalizing the signal output by the digital demodulation module;
the tap position detection and mode control component is used for monitoring whether the main tap position of a feedforward equalization filter in the self-adaptive equalizer drifts within a specified range or not, and generating a control signal for stabilizing the drifted main tap when the main tap position is monitored to drift, wherein the control signal is used for regulating and controlling the bandwidth of a timing recovery loop in a digital demodulation module and/or regulating and controlling the bandwidth of a phase tracker so that the drifted main tap value is stable
It can be understood that, the tap position detection and mode control component judges the interference of the received signal of the adaptive equalizer by detecting the change of the main tap position of the feedforward equalization filter in the adaptive equalizer, so as to improve the stability of the receiver system by adjusting the bandwidth of the loop filter in the timing recovery loop and the phase tracker (the structure of the loop filter is shown in fig. 9), thereby achieving the purpose of anti-interference.
For better understanding, fig. 4 shows a specific structure of a digital demodulation module and an adaptive equalizer, and in the structure shown in fig. 4, the digital demodulation module includes: an ADC sampling unit, a mixer, i.e. a digital mixer, a matched filter, a timing recovery loop and a carrier recovery loop. The ADC sampling unit is used for digitally sampling an analog signal, the digital mixer is used for demodulating an intermediate frequency modulation signal to a baseband signal, the timing recovery loop and the carrier recovery loop are used for respectively completing timing synchronization and carrier synchronization of the baseband signal, and the matched filter is used for being matched with a forming filter of a transmitter.
It should be noted that, the structure of the digital demodulation module is the same as that of the existing digital demodulation module, and the structure of the digital demodulation module is not improved in this embodiment.
Specifically, the ADC sampling unit is configured to sample a received modulation signal;
the mixer is used for demodulating the sampling signal of the ADC sampling unit to obtain a baseband signal; a matched filter for filtering the baseband signal as an output of the digital demodulation module;
the timing recovery loop is used for detecting the timing error in the signal output by the matched filter and outputting the detection result to the ADC sampling unit so that the ADC sampling unit adjusts the sampling frequency based on the detection result;
the carrier recovery loop is used for detecting carrier frequency errors in the signals output by the matched filter and outputting the detection result to the frequency mixer so that the frequency mixer adjusts the local oscillation frequency of the frequency mixer based on the detection result;
the timing recovery loop is further configured to receive a control signal output by the tap position detection and mode control component, and is configured to adjust a bandwidth of the timing recovery loop. For example, the integral term coefficient K of the filter in the timing recovery loop may be adjusted I And direct item coefficient K L To reduce the filter bandwidth.
Loop filter in timing recovery loopWith a digital second order phase-locked loop structure, the structure has two coefficients: k is I And K L Generally, choosing a wide loop bandwidth is advantageous for capturing larger timing errors, while choosing a small loop bandwidth is advantageous for tracking phase errors and reducing steady state phase errors.
The adaptive equalizer shown in fig. 4 may include: a feedforward equalization filter, a phase tracker, a decision device and a feedback equalization filter; these structures are not improved in this embodiment, and the functions thereof are consistent with the existing functions. An adaptive equalizer is typically an adaptive digital filter. Tap coefficients of a feed-forward equalization filter and a feedback equalization filter of the current adaptive equalizer may be automatically updated based on the detected error.
The feedforward equalization filter is used for performing equalization compensation on forward multipath of a channel in an output signal of the digital demodulation module to obtain an equalization compensation signal output by the phase tracker;
the phase tracker is used for tracking and compensating residual phase errors which do not obtain the balanced compensation signals in the output signals of the digital demodulation module; the loop filter in the phase tracker of the present embodiment is shown in fig. 9, and has an integral term coefficient K for the corresponding bandwidth parameter I And direct item coefficient K L 。
The decision device is used for deciding the output value of the self-adaptive equalizer;
the feedback equalization filter is used for performing equalization compensation on backward multipath remained in the signal output by the decision device,
the detection end of the tap position detection and mode control component is connected with the feedforward equalization filter, and monitors whether the positions of all taps in the feedforward equalization filter continuously drift or not; the drift here can be illustrated as follows: the main tap is at the beginning position of 500, after one second, the position is at 501, after 10 seconds, the position is at 510, after 20 seconds, the position is at 520, and the continuous drift can be judged.
And the phase tracker receives a control signal output by the tap position detection and mode control component and is used for regulating and controlling the bandwidth of the phase tracker.
A feedforward equalization filter and a feedback equalization filter in the self-adaptive equalization module are responsible for compensating channel decay; and the tap position detection and mode control component is used as a core controller to complete the adjustment of the timing recovery loop and the phase tracker.
It should be noted that, the tap coefficient of the feedforward equalization filter needs to be preset with a main tap value, which is generally 1.
For better understanding, the tap position detection and mode control component in this embodiment may be specifically configured to, after the adaptive equalizer completes convergence on the signal transmitted by the digital demodulation module, read position information of all taps in the feedforward equalization filter in the adaptive equalizer at the current time; reading the position information of all taps in the feedforward equalization filter at the current moment at intervals of a first preset time period; determining whether all taps in the feedforward equalization filter drift or not based on the position information of the current moment after a first preset time period and the position information after convergence; if yes, generating a control signal for stabilizing the drifting tap position; otherwise, repeatedly reading the position information of all taps in the feedforward equalization filter at the current moment at intervals of a first preset time period and judging again.
In practical applications, it is sufficient to monitor the main tap position among all taps.
In addition, the tap position detection and mode control component is also used for generating a control signal for stabilizing the drifting tap position; reading the position information of all taps of the feedforward equalization filter in the adaptive equalizer at the current moment again at intervals of a second preset time period; comparing the position information of the tap after the second preset time period with the position information of the tap before the second preset time period to determine whether the drift is continuous; if not, determining that the tap position in the feedforward equalization filter is in a stable state; otherwise, generating another control signal for stabilizing the continuously drifting tap position, wherein the other control signal is used for regulating and controlling the bandwidth of a timing recovery loop in the digital demodulation module and/or regulating and controlling the bandwidth of the phase tracker, so that the drifting tap position is stabilized; in this embodiment, the second preset time period is greater than or equal to the first preset time period.
For example, the tap position detection and mode control component generates a control signal for stabilizing the shifted tap position according to a predefined shift control strategy;
the drift control strategy may include: when the drift is left drift and the drift amount is smaller than a first threshold value, generating a first control signal, wherein the first control signal is used for regulating and controlling an integral term coefficient K of a timing recovery loop in the digital demodulation module I And direct item coefficient K L (ii) a When the drift is right drift and the drift amount is less than a first threshold value, generating a second control signal, wherein the second control signal is used for regulating and controlling an integral term coefficient K of a loop filter in the phase tracker I And direct item coefficient K L 。
Of course, in other embodiments, the left drift may also correspond to the bandwidth of the regulation phase tracker, and the right drift may correspond to the bandwidth of the regulation timing recovery loop, which is only an example. It is also possible that both the left and right drifts can simultaneously adjust the bandwidth of the phase tracker and the bandwidth of the timing recovery loop.
For better understanding, the core components of the present embodiment will be described with reference to the structure of the tap position detection and mode control component shown in fig. 8.
The tap position detection and mode control assembly of the present embodiment includes: a tap value register reading interface (tap value reading interface for short), a main tap position judger, a main tap position detector and a mode adjustment controller;
the tap value register reading interface is used for reading the tap value of a feedforward equalizing filter in the self-adaptive equalizer;
the main tap position judger is used for judging the main tap position of a feedforward equalization filter in the self-adaptive equalizer;
a main tap position detector for detecting whether the main tap position drifts over time;
the mode adjustment controller sends out control signals for regulating the bandwidth of the timing recovery loop in the digital demodulation module and/or for regulating the bandwidth of the phase tracker.
The tap position detection and mode control assembly shown in fig. 8 has at least two functions: the first function is to monitor the tap coefficient of the feedforward equalizing filter of the self-adapting equalizer in real time, and to judge and feed back in time when the main tap position of the feedforward equalizing filter moves forward or backward continuously with time.
Usually, the tap values in the feedforward equalization filter are stored in registers and can be read out sequentially. For example, all tap values in the registers of the feed forward equalization filter are read out via a tap value reading interface and then compared by the main tap position detector. Assuming that the initial position of the tap value is 502, after 1 second, the position is found to change to 503, and after 1 second, the position is found to change to 504, i.e. it belongs to continuous movement with time.
The second function is mode control, that is, when the drift of the main tap of the feedforward equalization filter is detected, a control signal is sent out to perform the following adjustments:
first, the bandwidth of the timing recovery loop can be adjusted, for example, the integral term coefficient (K) of its loop filter can be adjusted I ) And direct item coefficient (K) L ) E.g. from K L ＝2 -4 ，K I ＝2 -9 Adjusted to K L ＝2 -5 ，K I ＝2 -10 To narrow the loop filter bandwidth;
second, the phase tracker is bandwidth adjusted or turned off (bandwidth adjustment refers to adjusting the bandwidth of the loop filter; turn off refers to turning off the loop completely).
In this embodiment, by continuously observing the position of the main tap, if the main tap does not move, for example, for a long time such as 10 seconds/20 seconds, the adjustment is considered to be completed.
It is detected (e.g., once in 1 s) in time after each adjustment whether the main tap of the feed forward equalization filter has stopped moving.
In this embodiment, since all the taps of the feedforward equalization filter move together when the tap coefficient moves, and not only the main tap coefficient moves alone, it is a detection method that is relatively easy to detect the drift of the main tap position. In this embodiment, by detecting the main tap position, the movement information of the other tap positions can be known. Because all taps of the entire filter are moved together as a whole.
Of course, there are many adjustment methods for mode control, and this embodiment is only an example, and it determines whether drift is prevented by detecting and adjusting, so as to better reduce signal interference.
Fig. 5 is a signal processing procedure of a digital radio receiver based on the present invention, including the position detection and mode adjustment control procedure of the main tap of the feedforward equalization filter shown in fig. 3 and 4. After the QAM or VSB signal sent by the transmitter is received by the receiver, the whole receiver system achieves the optimal output state of the signal-to-noise ratio after the self-adaptive equalizer finishes convergence after a series of digital signal processing such as timing recovery, carrier recovery and channel equalization. The digital signal processing flow added by the invention is in a tracking state after the self-adaptive equalizer finishes convergence, and whether the main tap position of a feedforward filter of the channel equalizer continuously drifts or not is detected in real time so as to avoid equalization failure after the main tap drifts to the boundary of the filter and is out of bounds.
It should be noted that, equalizer convergence means that the equalizer reaches an operating state, and convergence is reached from the beginning of initialization, which means that compensation for a channel is achieved.
The operation of the tap position detection and mode control assembly is described in conjunction with fig. 6 and 7. The number of taps in the feed-forward equalization filter in this embodiment is set according to actual product requirements, and this embodiment is not limited thereto, and is usually 256 taps, and one main tap is pre-specified in all the taps.
The tap position detection process of the present invention is illustrated by a feed forward equalization filter having 832 taps. The tap coefficients of the filter are represented by h (n), n represents the position of the tap, and the maximum position of the 832 tap filter is h (832), and in fig. 6, the coefficient values of the taps of the filter from h (1) to h (n) are all stored in a register circuit, and the value of the register can be read and detected by the tap position detection and mode controller.
If the feed-forward equalization filter with 832 taps has a main tap position h (x) after equalization convergence is completed, as shown in fig. 7, of course, the other taps have certain coefficient values, which may be h (y) and h (z), so that h (x), h (y), and h (z) form a group of coefficient values after the feed-forward equalization filter has converged, and after a period of time (e.g., 1 to 5 s) is detected, if the coefficient values of the feed-forward equalization filter have been found to have shifted in position, that is, as shown in fig. 7, the positions of h (x), h (y), and h (z) have shifted to the positions of h (x '), h (y '), and h (z '), the tap position of the feed-forward equalization filter can be considered to have shifted, and a simple method can be considered that all taps have shifted in the same position by judging the position of the main tap h (x). The above-mentioned equilibrium convergence can be understood as: the error of the signal output by the decision device basically reaches a stable state, and the signal-to-noise ratio of the whole receiver system also reaches a stable state, namely, the signal-to-noise ratio is balanced and converged.
Whether the main tap position continuously drifts can be judged by continuously detecting the main tap position of the feedforward equalization filter, if the feedforward equalization filter finishes convergence at the beginning, the main tap position is at h (512), after a certain time, the main tap position drifts to h (812), as shown in fig. 7, the main tap position can be judged to obviously drift, and meanwhile, the speed of the drift can be judged according to the time. Once the main tap position of the feed forward equalization filter continues to drift, drifting to h (832), i.e., at the tap boundary of the feed forward equalization filter, the main tap that continues to drift disappears, causing the equalizer to fail.
Therefore, the drift of the position of the main tap is detected in time, and the bandwidth of the timing recovery loop and the bandwidth of the phase tracker are adjusted, so that the stability of the system can be effectively improved. The realization method of the invention is simple and effective, and the detection of the position of the main tap and the mode adjustment can be realized by a circuit.
In addition, an embodiment of the present invention further provides a signal equalization method based on a timing recovery loop, where the method may include:
the input modulation signal is sampled by an ADC (analog to digital converter), and the signal sampled by the ADC is demodulated by a digital mixer to obtain a baseband signal; after the baseband signal passes through the carrier recovery loop and the timing recovery loop, the carrier and timing synchronization of the data is completed; the demodulated data is subjected to adaptive equalizer to compensate channel decay;
the tap position detection and mode control component monitors the main tap position of a feedforward equalization filter of the adaptive equalizer in real time; and regulating and controlling the bandwidth of the phase tracker and the timing recovery loop according to the detection result.
Specifically, when the continuous movement of the main tap position of the feedforward equalization filter in one direction is detected, the bandwidth of the timing recovery loop may be adjusted first, and then the bandwidth of the phase tracker may be adjusted or turned off.
After the above adjustment, the continuous drift of the main tap of the feedforward equalization filter is effectively controlled. In practical application, after each adjustment, whether the main tap of the feedforward equalization filter stops moving or not is observed in time (namely, the position of the main tap is continuously observed), and the channel equalization circuit improves the anti-interference capability of the timing recovery and the whole channel equalization circuit by adjusting the phase tracker and the timing recovery loop.
In the embodiment, the tap position detection and mode control component monitors the main tap of the feedforward equalization filter of the self-adaptive equalizer, the position drift of the main tap caused by single-frequency wave interference is found in time, the bandwidth of the phase tracker and the timing recovery loop is adjusted, so that the failure of the equalizer caused by the fact that the main tap drifts to the boundary of the filter and crosses the boundary is avoided, the stability of the circuit is improved, and the anti-interference capability of the circuit is improved. The method is easy to realize and has obvious effect in practical application.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For a hardware implementation, the processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof.
For a software implementation, the techniques described herein may be implemented by means of units performing the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided in the present application, it should be understood that the execution sequence of the steps of the method embodiments can be arbitrarily adjusted unless there is an explicit precedence sequence. The disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present invention may be essentially implemented or make a contribution to the prior art, or may be implemented in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods described in the embodiments of the present invention.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.
It will be appreciated by those of skill in the art that although some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (9)
1. A timing recovery loop based signal equalization circuit, comprising:
the digital demodulation module, the adaptive equalizer, the tap position detection and mode control component;
the digital demodulation module is used for sampling, demodulating and synchronously processing the received modulation signals;
the adaptive equalizer is used for equalizing the signal output by the digital demodulation module;
the tap position detection and mode control component is used for monitoring whether the position information of all taps in the adaptive equalizer drifts or not, and generating a control signal for stabilizing the drifted tap positions when the tap position drifts, wherein the control signal is used for regulating and controlling the bandwidth of a timing recovery loop in a digital demodulation module and/or regulating and controlling the bandwidth of a phase tracker so that the drifted tap positions are stable.
2. The signal equalization circuit of claim 1, wherein the tap position detection and mode control component is specifically configured to:
after the self-adaptive equalizer finishes convergence on the signal transmitted by the digital demodulation module, reading the position information of all taps in a feedforward equalization filter in the self-adaptive equalizer at the current moment;
reading the position information of all taps in the feedforward equalization filter at the current moment at intervals of a first preset time period;
determining whether all taps in the feedforward equalization filter drift or not based on the position information of the current moment after a first preset time period and the position information after convergence;
if yes, generating a control signal for stabilizing the drifting tap position;
otherwise, repeatedly reading the position information of all taps in the feedforward equalization filter at the current moment at intervals of a first preset time period and judging again.
3. The signal equalization circuit of claim 2 wherein the tap position detection and mode control component is further configured to, after generating a control signal for stabilizing a drifting tap position;
reading the position information of all taps of the feedforward equalizing filter in the self-adaptive equalizer at the current moment again at intervals of a second preset time period;
comparing the position information of the tap after the second preset time period with the position information of the tap before the second preset time period to determine whether the tap drifts;
if not, determining that the tap position in the feedforward equalization filter is in a stable state;
otherwise, generating another control signal for stabilizing the position of the drifted tap, wherein the other control signal is used for regulating and controlling the bandwidth of a timing recovery loop in the digital demodulation module and/or regulating and controlling the bandwidth of the phase tracker so as to stabilize the position of the drifted tap;
the second preset time period is greater than or equal to the first preset time period.
4. A signal equalization circuit according to claim 1 or 3 wherein the tap position detection and mode control component is configured to generate a control signal for stabilizing a drifting tap position, comprising:
the tap position detection and mode control component generates a control signal for stabilizing a drifting tap position according to a predefined drift control strategy;
the drift control strategy comprises:
when the drift is left drift and the drift amount is less than a first threshold value, generating a first control signal, wherein the first control signal is used for regulating and controlling timing recovery in the digital demodulation moduleIntegral term coefficient K of loop I And direct item coefficient K L ；
When the drift is right drift and the drift amount is less than a first threshold value, generating a second control signal, wherein the second control signal is used for regulating and controlling an integral term coefficient K of a loop filter in the phase tracker I And direct item coefficient K L 。
5. Signal equalization circuit according to claim 1,
the tap position detection and mode control assembly comprises:
a tap value register reading interface for reading the position information of all taps of the feedforward equalizing filter in the adaptive equalizer;
a main tap position judger for acquiring main tap positions in the position information of all taps;
a main tap position detector for detecting whether the main tap position drifts over time;
and the mode adjustment controller is used for sending out a control signal for regulating and controlling the bandwidth of a timing recovery loop in the digital demodulation module and/or regulating and controlling the bandwidth of the phase tracker.
6. The signal equalization circuit of claim 1 wherein the digital demodulation module comprises:
the ADC sampling unit is used for sampling the received modulation signal;
the mixer is used for demodulating the sampling signal of the ADC sampling unit to obtain a baseband signal;
a matched filter for filtering the baseband signal to output;
the timing recovery loop is used for detecting timing errors in the signals output by the matched filter and outputting the detection results to the ADC sampling unit so that the ADC sampling unit adjusts the sampling frequency based on the detection results;
the carrier recovery loop is used for detecting carrier frequency errors in the signals output by the matched filter and outputting the detection result to the frequency mixer so that the frequency mixer adjusts the local oscillation frequency of the frequency mixer based on the detection result;
the timing recovery loop is further configured to receive a control signal output by the tap position detection and mode control component, and is configured to adjust a bandwidth of the timing recovery loop.
7. The signal equalization circuit of claim 1 wherein the adaptive equalizer comprises:
the feedforward equalization filter is used for performing equalization compensation on forward multipath of a channel in the output signal of the digital demodulation module to obtain an input equalization compensation signal;
the phase tracker is used for tracking and compensating residual phase errors which do not obtain the balanced compensation signals in the output signals of the digital demodulation module;
the decision device is used for deciding the output value of the adaptive equalizer;
the feedback equalization filter is used for performing equalization compensation on the backward multipath remained in the signal output by the decision device;
the detection end of the tap position detection and mode control component is connected with the feedforward equalization filter, and monitors whether the positions of all taps in the feedforward equalization filter continuously drift or not;
and the phase tracker receives a control signal output by the tap position detection and mode control component and is used for regulating and controlling the bandwidth of a loop filter in the phase tracker or switching off the phase tracker.
8. Signal equalization circuit according to claim 5,
when the feedforward equalization filter is a feedforward equalization filter with N-level taps, N is a natural number more than or equal to 256;
the N-tap feed-forward equalization filter comprises: a register;
initial position information of each tap in the N-level taps is stored in the register; and a main tap in the N-stage taps is preset;
the tap value register reading interface is used for reading the position information of all taps in the register at the current moment after the self-adaptive equalizer converges, the main tap position judger acquires the position information of the main tap in all the taps at the current moment, the main tap position detector determines whether the tap drifts or not based on the position information and the initial position information of the main tap at the current moment, and if the tap drifts, the mode adjustment controller sends out the control signal.
9. A receiver, comprising: a timing recovery loop based signal equalisation circuit as claimed in any one of the preceding claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211227055.7A CN115664901B (en) | 2022-10-09 | 2022-10-09 | Signal equalization circuit based on timing recovery loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211227055.7A CN115664901B (en) | 2022-10-09 | 2022-10-09 | Signal equalization circuit based on timing recovery loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115664901A true CN115664901A (en) | 2023-01-31 |
| CN115664901B CN115664901B (en) | 2024-04-19 |
Family
ID=84986345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211227055.7A Active CN115664901B (en) | 2022-10-09 | 2022-10-09 | Signal equalization circuit based on timing recovery loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115664901B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61177809A (en) * | 1985-02-01 | 1986-08-09 | Nec Corp | Transvrsal type adaptive automatic equalizer |
| JPH09245436A (en) * | 1996-03-05 | 1997-09-19 | Sony Corp | Data reproducing equipment and device for adaptive equalization |
| US6167024A (en) * | 1998-03-17 | 2000-12-26 | Trw Inc. | Multiple channel control using orthogonally modulated coded drive signals |
| US20100289965A1 (en) * | 2008-01-10 | 2010-11-18 | Thomson Licensing Corporation | Equalizer based symbol timing recovery with symbol enabled control |
| CN106330320A (en) * | 2015-06-24 | 2017-01-11 | 中兴通讯股份有限公司 | Adaptive equalizer and method for realizing adaptive equalization processing by the adaptive equalizer |
| US20180123776A1 (en) * | 2016-10-27 | 2018-05-03 | Applied Micro Circuits Corporation | Mitigating interaction between adaptive equalization and timing recovery |
| US10050774B1 (en) * | 2017-05-02 | 2018-08-14 | MACOM Technology Solutions Holding, Inc. | Mitigating interaction between adaptive equalization and timing recovery |
| CN109076030A (en) * | 2016-05-10 | 2018-12-21 | Macom连接解决有限公司 | Using the Timed Recovery of adaptive channel response estimation |
| CN112583433A (en) * | 2020-12-15 | 2021-03-30 | 四川灵通电讯有限公司 | Apparatus for timing recovery error detection in digital receiver and method of use |
-
2022
- 2022-10-09 CN CN202211227055.7A patent/CN115664901B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61177809A (en) * | 1985-02-01 | 1986-08-09 | Nec Corp | Transvrsal type adaptive automatic equalizer |
| JPH09245436A (en) * | 1996-03-05 | 1997-09-19 | Sony Corp | Data reproducing equipment and device for adaptive equalization |
| US6167024A (en) * | 1998-03-17 | 2000-12-26 | Trw Inc. | Multiple channel control using orthogonally modulated coded drive signals |
| US20100289965A1 (en) * | 2008-01-10 | 2010-11-18 | Thomson Licensing Corporation | Equalizer based symbol timing recovery with symbol enabled control |
| CN106330320A (en) * | 2015-06-24 | 2017-01-11 | 中兴通讯股份有限公司 | Adaptive equalizer and method for realizing adaptive equalization processing by the adaptive equalizer |
| CN109076030A (en) * | 2016-05-10 | 2018-12-21 | Macom连接解决有限公司 | Using the Timed Recovery of adaptive channel response estimation |
| US20180123776A1 (en) * | 2016-10-27 | 2018-05-03 | Applied Micro Circuits Corporation | Mitigating interaction between adaptive equalization and timing recovery |
| CN109891842A (en) * | 2016-10-27 | 2019-06-14 | Macom连接解决有限公司 | Alleviate the interaction between adaptive equalization and Timed Recovery |
| US10050774B1 (en) * | 2017-05-02 | 2018-08-14 | MACOM Technology Solutions Holding, Inc. | Mitigating interaction between adaptive equalization and timing recovery |
| CN110582984A (en) * | 2017-05-02 | 2019-12-17 | Macom技术解决方案控股公司 | Mitigating interaction between adaptive equalization and timing recovery |
| CN112583433A (en) * | 2020-12-15 | 2021-03-30 | 四川灵通电讯有限公司 | Apparatus for timing recovery error detection in digital receiver and method of use |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115664901B (en) | 2024-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3866375B2 (en) | Multimode equalizer in digital video signal processing system | |
| US7342981B2 (en) | Digital receiver having adaptive carrier recovery circuit | |
| US6985549B1 (en) | Blind cost criterion timing recovery | |
| US6788749B2 (en) | Erasure based instantaneous loop control in a data receiver | |
| JPH09214982A (en) | Equalizing method and equalizer for using reference signal | |
| KR100930988B1 (en) | A phase tracking system and method | |
| CN109891842A (en) | Alleviate the interaction between adaptive equalization and Timed Recovery | |
| EP0965198B1 (en) | Apparatus and method for performing timing recovery | |
| KR20070009685A (en) | Carrier recovery architecture with improved acquisition | |
| KR100338755B1 (en) | Digital signal receiver and method therefor | |
| JPH11317782A (en) | Blind automatic gain control system for receiver and modem | |
| US6154510A (en) | Symbol timing recovery based on adjusted, phase-selected magnitude values | |
| US8199864B1 (en) | Quadrature phase shift keying demodulator of digital broadcast reception system and demodulation method thereof | |
| US20020131536A1 (en) | Method and apparatus for timing recovery in signal combiner | |
| CN115664901B (en) | Signal equalization circuit based on timing recovery loop | |
| EP1397880B1 (en) | Joint timing recovery and equalization for an n-antennae system | |
| KR101019373B1 (en) | A system for detecting the characteristics of a time varying multipath component | |
| US8045649B2 (en) | Carrier recovery system and carrier recovery method | |
| EP1340348B1 (en) | Method and apparatus for increasing the quality of the receiver synchronization of qam or cap modulated modem connection | |
| US20050129148A1 (en) | Control algorithm in QAM modems | |
| WO2003013051A2 (en) | Timing recovery in data communication circuits | |
| KR20000034434A (en) | Digital terrestrial broadcasting and cable broadcasting receiver | |
| JPH04252609A (en) | Automatic equalizer | |
| KR20030077204A (en) | Demodulator for europe digital television system for terrestrial broadcasting signal and cable broadcasting signal | |
| JPH04252610A (en) | Automatic equalizer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |