CN115664528B

CN115664528B - Optical module, system and method for realizing ultrafast squelch function

Info

Publication number: CN115664528B
Application number: CN202211681701.7A
Authority: CN
Inventors: 王苗庆; 蒋昌明; 寿晓峰
Original assignee: Shaoxing Zktel Equipment Co ltd
Current assignee: Shaoxing Zktel Equipment Co ltd
Priority date: 2022-12-27
Filing date: 2022-12-27
Publication date: 2023-04-28
Anticipated expiration: 2042-12-27
Also published as: CN115664528A

Abstract

The invention relates to the field of optical communication, in particular to an optical module, a system and a method for realizing an ultrafast Squelch function, which are characterized in that a comparator, a NAND gate and other hardware circuits are additionally arranged on the basis of the existing scheme, the comparator outputs a comparison level signal to the NAND gate by comparing a real-time level signal with a reference level signal, the NAND gate performs NAND logic operation on the received comparison level signal and a pin level signal, and provides a control level signal to a 4-channel CDR integrated chip according to an operation result so as to realize the fast TX Squelch function of the 4-channel integrated CDR chip; the scheme can completely meet the nanosecond level requirement, thereby realizing the purpose of extremely fast responding to system abnormality and providing powerful guarantee for system maintenance.

Description

Optical module, system and method for realizing ultrafast squelch function

Technical Field

The present invention relates to the field of optical communications, and in particular, to an optical module, system, and method for implementing an ultrafast squelch function.

Background

Data centers are one of the most important infrastructure for cloud computing, and the high Jing Qidu of cloud computing and the expanded capital expenditure of cloud service vendors directly drive the prosperity of data centers. In the long term, the trend of the data flow to keep high-speed growth is almost irreversible, with the large-scale construction of 5G, the flow is in explosive growth due to the fact that everything interconnection, meanwhile, mass flow requirements are brought to downstream explosive applications such as VR/AR, ultra-high definition video and Internet of vehicles, and the like, so that in the long term, the global data flow must be in a high-speed growth state.

Under this large trend, the leaf ridge architecture of the data center is upgraded, and the rate is upgraded in front of the increasingly strong demand, which will bring about the strong demands of the number of light-passing modules and the rate improvement. While low-rate optical communication products have failed to meet the daily data transmission requirements, the data transmission of optical modules has also been accelerated from 10G, 25G, 40G, etc. to 100G, 200G, or even 400G.

The 100G optical module on the market is packaged with CFP, CFP2, CFP4 and QSFP28, wherein the QSFP28 optical module can be inserted into a switch with a higher density interface because of smaller volume, and becomes a main scheme of the 100G optical module. Due to the heat of the 100g QSFP28 LR4 optical module in the market, the following needs arise: some end customers require that the 100g QSFP28 LR4 optical module support a nanosecond level fast TX Squelch (transmit end Squelch function) instead of a traditional slow TX Squelch.

In view of the above-mentioned needs, many domestic and foreign chip design manufacturers follow up to try to develop a 4-channel CDR integrated chip supporting the application of 100g QSFP28 LR4, and for various reasons, some manufacturers' transmitting 4-channel CDR integrated chips do not support hardware TX Squelch, so that the terminal customer cannot put forward nanosecond-level fast TX Squelch (transmitting end Squelch function). Even after the 4-channel CDR integrated chip scheme is used by an optical module manufacturer, the optical module can be realized by a mode of adding a software register assignment to an MCU chip (microcontroller), but only a software TX Squelch function called in the industry is realized, the time consumption is about 400 hundred milliseconds, and the response time is far from meeting the nanosecond-level rapid TX Squelch proposed by a terminal customer, and the difference is up to thousands of times.

As shown in fig. 1, in the conventional 100g QSFP28 LR4 optical module and client-side motherboard combining system, when HOST (client-side motherboard) does not have normal modulation data signals output to the optical module, if the lasers laser 1-4 are not turned off, the optical module can still emit direct current light instead of normal optical signals with modulation data information, and for a high-speed communication system, the direct current light is meaningless, which would lead to system erroneous judgment, so that under the abnormal condition, the lasers 1-4 optical chips should be turned off rapidly, i.e. TX Squelch function is realized. For the above-mentioned abnormal case, TX Squelch is generally implemented in the following two ways:

1. when a pin Port1 of an MCU2 (a microcontroller 2) in the optical module detects that an output pin LOL of the integrated CDR chip is low level, the internal firmware of the MCU2 sets the pin Port2 of the MCU to be high level, so that a TXDIS pin of the 4-channel integrated CDR chip is high level, thereby closing laser chips laser 1-4, realizing that the optical module does not emit light, and ensuring that the duration of the process is about 400 milliseconds and cannot meet the TX Squelch of nanosecond level;

2. the microcontroller MCU1 in HOST gives an instruction to the inside of the optical module through the I2C bus I2C_M, the register Byte231 is set to hexadecimal 0XF, or the register Byte86 is set to hexadecimal 0XF, at the moment, the microcontroller MCU2 in the optical module can set the pin Port2 of the microcontroller MCU to be high level, so that the laser chips laser 1-4 are closed, the optical module does not emit light, the time consumed by the process exceeds the 1 st point scheme, and the rapid TX Squelch of nanosecond level cannot be met.

Based on this, the present application is hereby proposed.

Disclosure of Invention

The invention aims to provide an optical module for realizing a super-fast Squelch function, which realizes a nanosecond TX Squelch function through a hardware circuit scheme.

In order to achieve the above object, the technical scheme of the present invention is as follows:

an optical module for realizing ultra-fast noise suppression comprises a multi-channel CDR integrated chip, a laser chip, a voltage regulating circuit, a comparator, a NAND gate and a microcontroller for the optical module, wherein the multi-channel CDR integrated chip is in communication connection with the microcontroller for the optical module;

the multichannel CDR integrated chip comprises an LOS unit, a logic gate circuit and a CDR & Driver unit, and is defined with an LOL pin and a TXDIS pin; the LOS unit is used for receiving and processing the electric signals transmitted by the system main board of the client side and distributing the electric signals to the CDR & Driver unit and the logic gate circuit, and the logic gate circuit is used for receiving and processing the electric signals transmitted by the LOS unit and outputting real-time level signals through LOL pins; the TXDIS pin is used for receiving a control level signal sent by the NAND gate and controlling the start and stop of the CDR & Driver unit according to the control level signal; the CDR & Driver is used for outputting an electric signal to the laser chip;

the laser chip converts the received electric signals into optical signals and outputs the optical signals;

the microcontroller for the optical module comprises a VDAC unit and is defined with an output pin, the VDAC unit provides a reference level signal for the comparator through the voltage regulating circuit, and the microcontroller for the optical module provides a pin level signal for the NAND gate through the output pin;

the comparator is used for receiving and comparing the reference level signal and the real-time level signal and outputting a comparison level signal to the NAND gate;

the NAND gate is used for receiving the comparison level signal and the pin level signal and outputting a control level signal to the TXDIS pin through NAND logic operation.

Further, the voltage value of the reference level signal is set between 0.3V and 1.5V.

Further, the voltage value of the reference level signal is set at 1.2V.

Further, the microcontroller for the optical module defines an input pin, and the microcontroller for the optical module receives the real-time level signal output through the LOL pin through the input pin.

Further, the microcontroller for the optical module comprises a register, and the register is used for receiving an instruction sent by a main board of the client side system to control the pin level signal.

The second object of the present invention is to provide a system for implementing the ultrafast noise reduction function, which comprises a client side system motherboard, wherein the client side system motherboard comprises a microcontroller for a client side, and further comprises the optical module for implementing the ultrafast noise reduction function, and the microcontroller for the client side is in communication connection with the microcontroller for the optical module.

The third object of the present invention is to provide a method for implementing an ultrafast noise reduction function based on the above optical module, comprising the following steps,

the multichannel CDR integrated chip provides real-time level signals for the comparator, the optical module provides reference level signals for the comparator by using the microcontroller, and the optical module provides pin level signals for the NAND gate by using the microcontroller;

the comparator outputs a comparison level signal to the NAND gate by comparing the real-time level signal with the reference level signal; if the real-time level signal is smaller than the reference level signal, the comparison level signal is a low level signal, otherwise, the comparison level signal is a high level signal;

the NAND gate performs NAND logic operation on the received comparison level signal and the pin level signal, and provides a control level signal for the multi-channel CDR integrated chip according to an operation result;

the multichannel CDR integrated chip opens and closes the CDR & Driver unit according to the control level signal.

Further, the nand logic operation of the nand gate is:

when the comparison level signal is a low level signal, the pin level signal is a low level signal, and the control level signal is a high level signal;

when the comparison level signal is a low level signal and the pin level signal is a high level signal, the control level signal is a high level signal;

when the comparison level signal is a high level signal and the pin level signal is a low level signal, the control level signal is a high level signal;

when the comparison level signal is a high level signal and the pin level signal is a high level signal, the control level signal is a low level signal.

Furthermore, the optical module can also be compatible with the traditional slow TX Squelch function, and comprises the following steps that the optical module uses the microcontroller to control the pin level signal to be changed into a high level signal or a low level signal through register assignment according to the instruction sent by the main board of the client system.

The invention has the advantages that:

1. the method adopts a mode of adding a comparator and a NAND gate, realizes the TX Squelch function through a hardware circuit, and can completely meet the nanosecond level requirement, thereby realizing the purpose of extremely fast response to system abnormality and providing powerful guarantee for system maintenance;

2. the digital-to-analog conversion port (namely a VDAC unit) in the microcontroller for the optical module is used, and the voltage regulating circuit consisting of the precise resistor is matched, so that the reference level signal can be conveniently regulated, the comparison level signal output by the comparator can accurately track the real-time level signal, and the NAND logic operation is convenient;

3. because the definition rules of the level signals output by the multi-channel CDR integrated chip and the micro-controller MCU are different, the LOL pin level of the multi-channel CDR integrated electric chip is converted from the CMOS level (0.3-1.92V) to 0-3.3V by adding a comparator, so that the level signals of 2 input ports of a lower-stage NAND gate circuit which is electrically connected with the multi-channel CDR integrated electric chip are ensured to be the same level signal;

4. the system provided by the invention can be compatible with the traditional slow TX Squelch function at the same time, and improves the applicability of the scheme.

Drawings

Fig. 1 is a schematic diagram of a combination system of a 100g QSFP28 LR4 optical module and a client-side motherboard in the prior art;

fig. 2 is a schematic diagram of a combination system of a 100g QSFP28 LR4 optical module and a client-side motherboard in an embodiment;

FIG. 3 is a diagram illustrating a voltage setting of a reference level signal according to an embodiment;

fig. 4 is a schematic diagram of voltage values and resistance values of the microcontroller and the comparator for the optical module when the voltage value of the reference level signal is set to 1.2V in the embodiment.

Detailed Description

The present invention is described in further detail below with reference to examples.

English notation:

HOST: a client system motherboard, which provides power and modulated data signals for the 100G QSFP28 LR4 optical module in the embodiment;

TX: a transmitting end electrical channel;

LOS: in the embodiment, LOS 1-LOS 4 is one of 4-channel CDR integrated circuit function blocks in an optical module, and the amplitude of TX 1-4 high-speed modulation data signals output by HOST side and a preset reference threshold value are judged and then are transmitted to a logic gate circuit at the later stage;

TXDIS: in the embodiment, a 4-channel CDR integrated electric chip enabling pin is used for closing all CDR & Driver 1-4 output currents when receiving a high level, and then closing laser 1-4 of a laser optical chip to complete a TX Squelch function;

CDR & Driver: clock data recovery+driving is one of the circuit functional blocks of the 4-channel CDR integrated electric chip in the embodiment, and in the embodiment, CDR & Driver 1-4 provides modulated data signal current and direct current bias current for laser optical chips laser 1-4 of the optical module;

laser, laser optical chip, in the embodiment, laser 1-4 is used as carrier of optical signal, convert the data electric signal of system motherboard side into optical signal and send out;

VDAC: the voltage form is converted into a digital-analog circuit.

As shown in fig. 2, the present embodiment provides a system for implementing an ultrafast noise suppression function, which includes a client-side system motherboard HOST and a 100g QSFP28 LR4 optical module composed of a 4-channel CDR integrated chip, laser chips Laser 1-4, a voltage regulating circuit, a comparator, a nand gate, and an optical module microcontroller MCU2.

The system comprises a client side system main board, a 100G QSFP28 LR4 optical module, a client side microcontroller MCU1, an I2C bus and a data storage and communication system, wherein the client side system main board supplies power and modulation data electric signals to the 100G QSFP28 LR4 optical module through electric channels TX 1-4, and the client side microcontroller MCU1 is arranged in the client side system main board and is in communication connection with the optical module through the microcontroller MCU2 through the I2C bus.

The 4-channel CDR integrated chip is internally provided with an LOS unit (namely LOS 1-LOS 4 in figure 2), a logic gate circuit, a CDR & Driver unit (namely CDR & Driver 1-4 in figure 2), an LOL pin and a TXDIS pin. The LOS unit is used for receiving and processing the electric signals transmitted by the HOST of the client system and distributing the electric signals to the CDR & Driver unit and the logic gate circuit, and the logic gate circuit is used for receiving and processing the electric signals transmitted by the LOS unit and outputting real-time level signals through LOL pins; the TXDIS pin is used for receiving a control level signal VTDIS sent by the NAND gate and controlling the start and stop of the CDR & Driver unit according to the control level signal VTDIS; the CDR & Driver is used for outputting an electric signal to the laser chip.

The Laser chips Laser 1-4 convert the received electrical signals into optical signals and output the optical signals.

The microcontroller for the optical module comprises a VDAC unit and defines an output pin Port2, wherein the VDAC unit provides a reference level signal VC to the comparator through a voltage regulating circuit, and the voltage regulating circuit consists of precision resistors R1 and R2 in the embodiment. The reference level signal VC can be conveniently regulated by using a digital-to-analog conversion port (namely a VDAC unit) in the microcontroller MCU2 for the optical module and matching with a voltage regulating circuit consisting of precision resistors R1 and R2, so that the comparison level signal output by the comparator can accurately track the real-time level signal. The optical module provides a pin level signal VMCU2 to the nand gate via an output pin with the microcontroller.

The comparator is used for receiving and comparing the reference level signal VC and the real-time level signal, and outputting a comparison level signal VCO to the NAND gate. Because the level signals output by the 4-channel CDR integrated chip and the optical module by the microcontroller MCU2 are different in definition rule, the LOL pin level of the multi-channel CDR integrated chip is converted from the CMOS level (0.3-1.92V) to 0-3.3V by adding the comparator, so that the level signals of 2 input ports of a lower-stage NAND gate circuit which is electrically connected with the same level signals are ensured, and the NAND logic operation is facilitated.

The nand gate is used for receiving the comparison level signal VCO and the pin level signal VMCU2, and outputting the control level signal VTDIS to the TXDIS pin through a nand logic operation.

The voltage value of the reference level signal VC is set as follows: as shown in fig. 3 and fig. 4, according to the specification of the 4-channel CDR integrated circuit chip, when the real-time level signal output by the LOL pin is at a high level, the level value is 1.5-1.92V, and when the real-time level signal output by the LOL pin is at a low level, the level value is <0.3V, and the real-time level signal is connected to the negative input port of the comparator, so theoretically calculating, the level value of the reference level signal VC can be set between 0.3-1.5V, and the embodiment suggests that the level value of the reference level signal VC be about 1.2V, so that the resistors R1 and R2 can share a same material (i.e. adopt the same resistor, such as in fig. 4, R1 and R2 are both 10kΩ), so as to be beneficial to the management of the BOM product.

Preferably, the optical module microcontroller MCU2 of the present embodiment further defines an input pin Port1, and the optical module microcontroller MCU2 receives the real-time level signal output through the LOL pin via the input pin Port 1. The purpose of this arrangement is to facilitate the ability to see the magnitude of the real-time level value output by the LOL pin when needed.

The use process of the system is as follows:

s01, the system is powered on to run, a 100G QSFP28 LR4 optical module inserted on a system board is powered on and starts to run, LOS 1-4 units of a 4-channel CDR integrated circuit chip in the system can judge and recognize the amplitude of high-speed modulation data electric signals transmitted by electric channels TX 1-4 in real time, then the high-speed modulation data electric signals are respectively output to a logic gate circuit and a CDR & Driver unit at the later stage, and the logic gate circuit outputs real-time level signals to an input port at the positive end of a comparator after performing logic operation; the optical module provides a reference level signal VC for the comparator by using a microcontroller MCU2, and provides a pin level signal VMCU2 for the NAND gate by using the microcontroller MCU2;

s02, the comparator outputs a comparison level signal VCO to the NAND gate by comparing the real-time level signal with a reference level signal VC; if any one of the electrical channels TX1 to TX 4 is abnormal (i.e. the system is running abnormally), the real-time level signal output by the logic gate circuit is a low level signal, the level value is less than 0.3V, the low level is transmitted to the positive input port of the comparator and is compared with the negative input port vc=1.2v, and the comparison level signal VCO output by the output port of the comparator is a low level signal; if TX 1-4 are normal (i.e. the system is operating normally), the real-time level signal output by the logic gate circuit is high, the level value is 1.5-1.92V, the high level signal is transmitted to the positive input port of the comparator and is compared with the negative input port vc=1.2v, and the comparison level signal VCO output by the output port of the comparator is high;

s03, performing NAND logic operation on the received comparison level signal VCO and the pin level signal VMCU2 by using a NAND gate, and providing a control level signal VTDIS for the 4-channel CDR integrated chip according to an operation result; in this embodiment, the nand logic operation of the nand gate is shown in the following table (in the table, L represents a low level signal, H represents a high level signal):

VCO	VMCU2	VTDIS
			L	L	H
L	H	H
			H	L	H
H	H	L

from the above table, it can be derived that:

a. when the comparison level signal VCO is a low level signal, the pin level signal VMCU2 is a low level signal, and the control level signal VTDIS is a high level signal;

b. when the comparison level signal VCO is a low level signal and the pin level signal VMCU2 is a high level signal, the control level signal VTDIS is a high level signal;

c. when the comparison level signal VCO is a high level signal and the pin level signal VMCU2 is a low level signal, the control level signal VTDIS is a high level signal;

d. when the comparison level signal VCO is a high level signal and the pin level signal VMCU2 is a high level signal, the control level signal VTDIS is a low level signal;

therefore, when the comparison level signal VCO and/or the pin level signal VMCU2 are/is low level signals, the control level signal VTDIS is a high level signal, so that the laser chips lasers 1-4 can be turned off, when the comparison level signal VCO is a high level signal, the control level signal VTDIS depends on the pin level signal VMCU2, and in general, the pin level signal VMCU2 is kept high level signal (but as will be seen from the following, by controlling the pin level signal VMCU2, the slow TX Squelch function can be realized);

s04, the multichannel CDR integrated chip opens and closes the CDR & Driver unit according to the control level signal, namely when the control level signal is a high level signal, the TXDIS pin is high level, and then the laser chip lasers 1-4 are closed by closing the CDR & Driver unit, so that a rapid TX Squelch function is achieved; when the control level signal is a low level signal, the TXDIS pin is low level, and the optical module works normally.

According to the steps, the hardware circuit added in the scheme of the embodiment can rapidly respond and close the laser chip when the system is abnormal, so that a rapid TX Squelch function is achieved, and the hardware circuit has no interference to the optical module when the system is in normal operation.

The scheme of the embodiment can be downward compatible with the slow TX Squelch while realizing the fast TX Squelch. The microcontroller for the optical module comprises a register which is used for receiving an instruction sent by the client microcontroller MCU1 to control the pin level signal. As shown in fig. 2, when the system is abnormal in operation, the client side micro controller MCU1 gives an instruction to the optical module by the micro controller MCU2 through the I2C bus i2c_m, sets the register Byte231 to 0XF in hexadecimal or sets the register Byte86 to 0XF in hexadecimal, at this time, the optical module will set the output pin Port2 of the optical module by the micro controller MCU2 to be at a low level, i.e. the pin level signal VMCU2 is at a low level, and according to the truth table of the nand gate, the control level signal VTDIS is at a high level, so as to close the laser chips laser 1-4, so that the optical module does not emit light, and the conventional soft TX Squelch function, i.e. the slow TX Squelch function is implemented. In the normal operation state of the system, that is, when the HOST of the system on the client side does not issue an instruction to change the default setting value (00) of the optical module register Byte231 or Byte86, that is, does not require the optical module to enter the slow TX Squelch state, the micro controller MCU2 for the optical module will set the output pin Port2 thereof to a high level, that is, the VMCU2 is a high level, and according to the truth table of the nand gate, the output pin VTDIS of the nand gate is a low level (when the system is operating normally, the implementation level signal output by the pin LOL is a high level), so that the optical module emits light normally, and the system operates normally.

The above embodiments are only for illustrating the concept of the present invention and not for limiting the protection of the claims of the present invention, and all the insubstantial modifications of the present invention using the concept shall fall within the protection scope of the present invention.

Claims

1. The optical module for realizing the ultra-fast noise reduction function is characterized by comprising a multi-channel CDR integrated chip, a laser chip, a voltage regulating circuit, a comparator, a NAND gate and a microcontroller for the optical module, wherein the multi-channel CDR integrated chip is in communication connection with the microcontroller for the optical module;

the microcontroller for the optical module comprises a VDAC unit and is defined with an output pin, the VDAC unit provides a reference level signal for the comparator through the voltage regulating circuit, the microcontroller for the optical module provides a pin level signal for the NAND gate through the output pin, and the microcontroller for the optical module comprises a register, wherein the register is used for receiving an instruction sent by a main board of a system at a client side to control the pin level signal;

2. An optical module for implementing a super-fast squelch function as defined in claim 1, wherein the reference level signal has a voltage value set between 0.3V and 1.5V.

3. An optical module for realizing a super-fast noise cancellation function as claimed in claim 1, wherein the voltage value of the reference level signal is set at 1.2V.

4. An optical module for implementing a super-fast squelch function as defined in claim 1, wherein the optical module defines an input pin for the microcontroller and the optical module receives a real-time level signal output through the LOL pin via the input pin.

5. The system for realizing the ultra-fast noise reduction function comprises a client side system main board, wherein the client side system main board comprises a microcontroller for a client side, and the system is characterized by further comprising the optical module for realizing the ultra-fast noise reduction function according to any one of claims 1 to 4, wherein the microcontroller for the client side is in communication connection with the microcontroller for the optical module.

6. A method for realizing ultra-fast squelch function based on the optical module according to any one of claims 1 to 4, characterized by comprising the following steps,

7. The method for implementing a ultrafast muting function according to claim 6, wherein the nand logic operation of the nand gate is:

8. The method for realizing the ultra-fast noise reduction function according to claim 6, wherein the optical module uses the microcontroller to control the pin level signal to be changed into the high level signal or the low level signal according to the instruction sent by the main board of the client side system through the register assignment.