CN115659700A - Waveform automatic contrast analysis method, apparatus and medium based on signal dependency relationship - Google Patents
Waveform automatic contrast analysis method, apparatus and medium based on signal dependency relationship Download PDFInfo
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Abstract
The invention relates to a waveform automatic contrast analysis method, equipment and a medium based on a signal dependency relationship, which realize the step S1 of respectively analyzing a first chip design and a second chip design to generate a first topological structure and a second topological structure; s2, simulating based on the first chip design and the second chip design to generate a first waveform file and a second waveform file; s3, comparing the first waveform file with the second waveform file to obtain a first signal difference set and a second signal difference set; s4, extracting a first topological difference set from the first topological structure based on the first signal difference set, and extracting a second topological difference set from the second topological structure based on the second signal difference set; s5, acquiring mapping logic information; and S6, merging the first topological difference set and the second topological difference set based on the mapping logic information to generate a difference signal topological set. The invention reduces the cost of waveform analysis and improves the efficiency of waveform analysis.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a waveform automatic contrast analysis method, equipment and medium based on signal dependency.
Background
In the operation result of the chip design simulation tool, the difference of the signals is often thousands of, but the difference between the signals is often dependent. In the prior art, a chip design engineer or a verification engineer usually needs to spend manual analysis on differences of the waveform signals to find out root causes which result is inferior to the expected result, so that the cost of waveform analysis is high and the efficiency is low, thereby increasing the cost of chip design and chip verification and reducing the efficiency of chip design and chip verification.
Disclosure of Invention
The invention aims to provide a waveform automatic contrast analysis method, equipment and medium based on signal dependency relationship, which reduces the cost of waveform analysis and improves the efficiency of waveform analysis, thereby reducing the cost of chip design and chip verification and improving the efficiency of chip design and chip verification.
According to an aspect of the present invention, there is provided a waveform automatic contrast analysis method based on signal dependency relationship, including the following steps:
s1, respectively analyzing a first chip design and a second chip design, and generating a first topological structure corresponding to the first chip design and a second topological structure corresponding to the second chip design, wherein the topological structures comprise signal nodes and a topological dependency relationship between the signal nodes.
And S2, respectively carrying out simulation based on the first chip design and the second chip design to generate a first waveform file corresponding to the first chip design and a second waveform file corresponding to the second chip design.
And S3, comparing the first waveform file with the second waveform file to obtain a first signal difference set of the first waveform file relative to the second waveform file and a second signal difference set of the second waveform file relative to the first waveform file.
And S4, extracting a first topological difference set from the first topological structure based on the first signal difference set, and extracting a second topological difference set from the second topological structure based on the second signal difference set.
And S5, acquiring mapping logic information, wherein the mapping logic information comprises a signal deleting identifier and signal renaming information of the second chip design relative to the first chip design.
And S6, merging the first topological difference set and the second topological difference set based on the mapping logic information to generate a difference signal topological set.
According to another aspect of the present invention, there is provided an electronic apparatus including:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method of the preceding.
According to yet another aspect of the present invention, there is provided a computer-readable storage medium having stored thereon computer-executable instructions for performing the method as set forth above.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the waveform automatic contrast analysis method, equipment and medium based on the signal dependency relationship can achieve considerable technical progress and practicability, have industrial wide utilization value and at least have the following advantages:
the invention can automatically analyze the difference of the signals according to the signal waveform based on the signal dependency relationship and derive the logic relationship diagram, thereby saving a great deal of manual time for the chip design or verification process, accurately and clearly displaying the analysis result for the user, improving the efficiency of waveform analysis, reducing the cost of waveform analysis and further improving the efficiency of chip design or chip verification.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are specifically described below with reference to the accompanying drawings.
Drawings
Fig. 1 is a flowchart of a waveform automatic contrast analysis method based on signal dependency provided in an embodiment of the present invention;
fig. 2 (a) is a schematic diagram of a first topology difference set provided in an embodiment of the present invention;
FIG. 2 (b) is a diagram illustrating a second topology difference set according to an embodiment of the present invention;
fig. 3 is a schematic diagram of combining the first topological difference and the second topological difference according to the embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be given to specific embodiments and effects of a method, an apparatus and a medium for waveform automatic comparison and analysis based on signal dependency relationship according to the present invention with reference to the accompanying drawings and preferred embodiments.
The embodiment of the invention provides a waveform automatic contrast analysis method based on signal dependency relationship, which comprises the following steps as shown in figure 1:
s1, respectively analyzing a first chip design and a second chip design, and generating a first topological structure corresponding to the first chip design and a second topological structure corresponding to the second chip design, wherein the topological structures comprise signal nodes and topological dependency relations among the signal nodes.
It should be noted that, in the chip development process, the chip design needs to be continuously adjusted, and the chip designs before and after adjustment are compared to determine whether the adjustment target is reached, so the second chip design in step S1 may be the adjusted design of the first chip design. In addition, the first chip design and the second chip design both include corresponding chip design codes, such as Verilog codes, and the corresponding signal transmission relationship in the chip design can be analyzed by analyzing the chip design codes, so that a complete signal dependent topology structure of the first chip design and the second chip design is obtained.
S2, simulating based on the first chip design and the second chip design respectively to generate a first waveform file corresponding to the first chip design and a second waveform file corresponding to the second chip design.
In step S2, the simulation of the first chip design and the second chip design may be directly implemented based on an existing chip design simulation tool, and a corresponding waveform file is generated, which is not described herein again. It should be noted that the waveform file includes information of signal values of each signal at each time in the chip design.
And S3, comparing the first waveform file with the second waveform file to obtain a first signal difference set of the first waveform file relative to the second waveform file and a second signal difference set of the second waveform file relative to the first waveform file.
And S4, extracting a first topological difference set from the first topological structure based on the first signal difference set, and extracting a second topological difference set from the second topological structure based on the second signal difference set.
It should be noted that, the set of topological differences of the first chip design with respect to the second chip design, that is, the first topological difference set, and the set of topological differences of the second chip design with respect to the first chip design, that is, the second topological difference set, can be obtained through step S4.
Although the topology difference set of the first chip design relative to the second chip design and the topology difference set of the second chip design relative to the first chip design are clearly obtained in step S4, because of the huge chip scale, there may still be a large number of different topology structures in the first topology difference set and the second topology difference set in general, and therefore, the further processing may be performed through step S5.
And S5, acquiring mapping logic information, wherein the mapping logic information comprises a signal deleting identifier and signal renaming information of the second chip design relative to the first chip design.
It should be noted that, in a general case, from a first chip design to a second chip design, most of the signal identifiers and the signal topology dependency relationship are not changed, only a small part of the signal identifiers are renamed, that is, the signal identifiers are changed, or part of the signal identifiers which do not need to be paid attention again are deleted, or part of the signal identifiers and the signal dependency relationship may be added. Therefore, the mapping logic relationship can be preset, and the first topological difference set and the second topological difference set can be further simplified.
And S6, merging the first topological difference set and the second topological difference set based on the mapping logic information to generate a difference signal topological set.
The collection of the first topological difference set and the second topological difference set can be further simplified through the step S6, so that signal nodes which are possibly in problem can be accurately and clearly positioned, all difference waveforms do not need to be analyzed one by one, the efficiency of waveform analysis is improved, the efficiency of chip design and chip verification is improved, the cost of waveform analysis is reduced, and the cost of chip design and chip verification is reduced.
As an embodiment, the step S6 is followed by:
and S7, generating a logic relation graph of each difference signal topology based on the difference signal topology set for displaying.
Through the step S7, the logic relation graph of each difference signal topology can be visually displayed on a display interface in a schematic drawing rendering mode and the like for a user to analyze.
It should be noted that, although the difference signal usually includes a plurality of difference signals, based on the dependency relationship of the signals, usually the difference in one difference signal topology is caused by the root node in the difference signal topology, and therefore, the corresponding root node may be highlighted, as an embodiment, the step S7 further includes:
and step S70, highlighting the root node in the logic relationship graph of each difference signal topology.
As an embodiment, the first waveform file includes all first signal node identifiers in a first chip design and first waveform information corresponding to each first signal node identifier, and the second waveform file includes all second signal node identifiers in a second chip design and second waveform information corresponding to each second signal node identifier, it should be noted that, because in a normal case, the second chip design is obtained by modifying a part of the first chip design, the first signal node identifiers in the first chip design and the second signal node identifiers in the second chip design are the same, but due to the change of the design, signal values corresponding to the same node signals may be different, where the step S3 includes:
step S31, determining whether each first signal node identifier exists in the second waveform file, if not, storing the first signal node identifier in the first signal difference set, otherwise, executing step S32.
Step S32, determining whether the first waveform information corresponding to the first signal node identifier in the first waveform file is the same as the second waveform information corresponding to the second waveform file, and if not, storing the first signal node identifier in a first signal difference set to generate the first signal difference set.
Step S33, determining whether each second signal node identifier exists in the first waveform file, if not, storing the second signal node identifier in the second signal difference set, otherwise, executing step S34.
Step S34, determining whether the second waveform information corresponding to the second signal node identifier in the second waveform file is the same as the first waveform information corresponding to the first waveform file, and if not, storing the second signal node identifier in a second signal difference set to generate the second signal difference set.
Through the steps S31 to S34, the difference signal identifier of the first chip design relative to the second chip design and the difference signal identifier of the second chip design relative to the first chip design can be quickly and accurately obtained.
As an example, the step S4 includes:
step S41, extracting a signal node corresponding to a first signal node identifier in a first signal difference set from the first topological structure, and generating the first topological difference set according to a topological dependency relationship between the first signal nodes in the first signal difference set.
Step S42, extracting a signal node corresponding to the second signal node identifier in the second signal difference set and a topological dependency relationship between the second signal nodes in the second signal difference set from the second topological structure, and generating the second topological difference set.
The first topological difference set and the second topological difference set are obtained through the steps S41 to S42, so that the difference signals needing to be analyzed can be conveniently positioned through the topological dependency relationship of the difference signals, and the efficiency of waveform analysis is improved.
As an example, the step S6 includes:
and S61, deleting the signal nodes corresponding to the first topology difference set according to the deletion signal identification.
It should be noted that, in the process of updating the first chip design to the second chip design, there are some signals that do not need to be paid attention to any more, so that the corresponding signal nodes in the first topological difference set can be deleted based on the known deleted signal identifiers, thereby filtering out noise and improving the efficiency of waveform analysis.
Step S62, according to the signal renaming information, determining the same signal nodes in the first topological difference set and the second topological difference set, and combining the same topological structures in the first topological difference set and the second topological difference set to generate the difference signal topological set.
It should be noted that, by unifying the renamed signal identifiers, the same topological structures in the first topological difference set and the second topological difference set can be accurately merged, and the efficiency and accuracy of waveform analysis are improved.
The mapping logic information can be well designed in advance according to the change of the design, but the conditions of omission and the like can exist, so the mapping logic information can be updated based on the logic relation graph of the difference signal topology. As an embodiment, in step S31, if the first signal node identifier does not exist in the second waveform file, a first prompt identifier is set for the first signal node identifier; in step S33, if the second signal node identifier does not exist in the first waveform file, a second prompt identifier is set for the second signal node identifier.
The step S6 is followed by:
step S71, generating a logic relation graph of each difference signal topology based on the difference signal topology set for displaying, and labeling a first prompt identifier and a second prompt identifier corresponding to the node on a display interface;
and step S72, updating the mapping logic information based on the first prompt identifier and the second prompt identifier marked on the logic relationship diagram of the difference signal topology, and returning to the step S5.
By updating the mapping logic information, multiple iterations can be performed to obtain an accurate logic relation graph of the topology, and the efficiency and accuracy of waveform analysis are improved.
The present invention is further explained below by a specific example, assuming that the first signal difference set obtained by step S3 is { a2, a11, a12, a40, a41}, the second signal difference set is { a2, a76, a40, a41, a51}, the first topological difference set obtained by step S4 is shown in fig. 2 (a), and the second topological difference set is shown in fig. 2 (b). It should be noted that, for convenience of describing the present invention, the present example simplifies the processing, only a small amount of data is listed for description, and in practical applications, there may be more elements in the first signal difference set, the second signal difference set, the first topology difference set, and the second topology difference set than in the present example. Further, it is assumed that in step S5, the mapping logic information includes "a12 removed", "a11= > a76", and "a12 removed" indicates that a12 is deleted in the process from the first chip design to the second chip design. "a11= > a76", which means that in the process from the first chip design to the second chip design, a11 is renamed to a76, and based on the mapping logic information, merging is performed to generate a difference signal topology set, as shown in fig. 3. It can be understood that when the logical relationship graph of the difference signal topology set is displayed, the root node, the second prompt identification information and the like can be labeled, and the logical relationship graph is displayed more intuitively.
It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
An embodiment of the present invention further provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions configured to perform a method according to an embodiment of the invention.
The embodiment of the invention also provides a computer-readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.
The embodiment of the invention can automatically analyze the difference of the signals according to the signal waveforms and derive the logical relationship diagram based on the signal dependency relationship, can save a large amount of manual time for the chip design or verification process, accurately and clearly display the analysis result for a user, improves the efficiency of waveform analysis, reduces the cost of waveform analysis and further improves the efficiency of chip design or chip verification.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A waveform automatic contrast analysis method based on signal dependency relationship is characterized in that,
the method comprises the following steps:
s1, respectively analyzing a first chip design and a second chip design, and generating a first topological structure corresponding to the first chip design and a second topological structure corresponding to the second chip design, wherein the topological structures comprise signal nodes and topological dependency relations among the signal nodes;
s2, respectively carrying out simulation based on the first chip design and the second chip design to generate a first waveform file corresponding to the first chip design and a second waveform file corresponding to the second chip design;
s3, comparing the first waveform file with the second waveform file to obtain a first signal difference set of the first waveform file relative to the second waveform file and a second signal difference set of the second waveform file relative to the first waveform file;
s4, extracting a first topological difference set from the first topological structure based on the first signal difference set, and extracting a second topological difference set from the second topological structure based on the second signal difference set;
s5, acquiring mapping logic information, wherein the mapping logic information comprises a signal deleting identifier and signal renaming information of the second chip design relative to the first chip design;
and S6, merging the first topological difference set and the second topological difference set based on the mapping logic information to generate a difference signal topological set.
2. The method of claim 1,
the step S6 is followed by:
and S7, generating a logic relation graph of each difference signal topology based on the difference signal topology set for displaying.
3. The method of claim 2,
the step S7 further includes:
and step S70, highlighting the root node in the logic relationship graph of each difference signal topology.
4. The method of claim 1,
the first waveform file includes all first signal node identifiers in a first chip design and first waveform information corresponding to each first signal node identifier, the second waveform file includes all second signal node identifiers in a second chip design and second waveform information corresponding to each second signal node identifier, the step S3 includes:
step S31, judging whether each first signal node identification exists in the second waveform file, if not, storing the first signal node identification in a first signal difference set, otherwise, executing step S32;
step S32, judging whether first waveform information corresponding to the first signal node identifier in a first waveform file is the same as second waveform information corresponding to the first signal node identifier in a second waveform file, if not, storing the first signal node identifier in a first signal difference set to generate the first signal difference set;
step S33, judging whether each second signal node identification exists in the first waveform file, if not, storing the second signal node identification in a second signal difference set, otherwise, executing step S34;
step S34, determining whether the second waveform information corresponding to the second signal node identifier in the second waveform file is the same as the first waveform information corresponding to the first waveform file, and if not, storing the second signal node identifier in a second signal difference set to generate the second signal difference set.
5. The method of claim 4,
the step S4 includes:
step S41, extracting a signal node corresponding to a first signal node identifier in a first signal difference set and a topological dependency relationship among first signal nodes in the first signal difference set from the first topological structure, and generating the first topological difference set;
and S42, extracting signal nodes corresponding to second signal node identifications in a second signal difference set and topological dependency relations among the second signal nodes in the second signal difference set from the second topological structure, and generating the second topological difference set.
6. The method of claim 1,
the step S6 includes:
s61, deleting the corresponding signal nodes in the first topological difference set according to the deleting signal identification;
step S62, according to the signal renaming information, determining the same signal nodes in the first topological difference set and the second topological difference set, and combining the same topological structures in the first topological difference set and the second topological difference set to generate the difference signal topological set.
7. The method of claim 4,
in step S31, if the first signal node identifier does not exist in the second waveform file, setting a first prompt identifier for the first signal node identifier;
in step S33, if the second signal node identifier does not exist in the first waveform file, a second prompt identifier is set for the second signal node identifier.
8. The method of claim 7,
the step S6 is followed by:
step S71, generating a logic relation graph of each difference signal topology based on the difference signal topology set for displaying, and labeling a first prompt identifier and a second prompt identifier corresponding to the node on a display interface;
and step S72, updating the mapping logic information based on the first prompt identifier and the second prompt identifier marked on the logic relationship diagram of the difference signal topology, and returning to the step S5.
9. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-8.
10. A computer-readable storage medium having stored thereon computer-executable instructions for performing the method of any of the preceding claims 1-8.
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