CN114091398A

CN114091398A - Network topology structure design method and device, electronic equipment and storage medium

Info

Publication number: CN114091398A
Application number: CN202111363965.3A
Authority: CN
Inventors: 姚水音; 梁洪昌
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-11-17
Filing date: 2021-11-17
Publication date: 2022-02-25

Abstract

A network topology design method, a device, an electronic device and a computer readable storage medium of an integrated circuit are provided. The network topology structure design method of the integrated circuit comprises the following steps: obtaining at least one network structure model, wherein each network structure model is generated by packaging a network structure in a preset area, the network structure in the preset area is used as a part of an integrated circuit, and each network structure model comprises a plurality of attributes; performing at least one assignment on a plurality of attributes in each network structure model to obtain a plurality of instantiation models; splicing the instantiated models to obtain an overall network model corresponding to the integrated circuit; and converting the overall network model into a simulated netlist of the integrated circuit, the simulated netlist comprising a plurality of physical devices. The method can improve the efficiency of verifying the complex topological structure of the single logic network, shorten the verification period and is suitable for quick verification iteration.

Description

Network topology structure design method and device, electronic equipment and storage medium

Technical Field

Embodiments of the present disclosure relate to a method and apparatus for designing a network topology of an integrated circuit, an electronic device, and a computer-readable storage medium.

Background

After the chip process enters deep submicron level, the design target is continuously improved, for example, the clock frequency is gradually increased on the premise of low delay characteristics brought by the advanced process. To this end, physical designs have also been modified accordingly to meet design goals. For example, low latency is achieved by complex topologies (e.g., mesh network topologies) using a single logic.

Disclosure of Invention

At least one embodiment of the present disclosure provides a method for designing a network topology of an integrated circuit, including: obtaining at least one network structure model, wherein each network structure model is generated by packaging a network structure in a preset area, the network structure in the preset area is used as a part of an integrated circuit, and each network structure model comprises a plurality of attributes; performing at least one assignment on a plurality of attributes in each network structure model to obtain a plurality of instantiation models; splicing the instantiated models to obtain an integral network model corresponding to the integrated circuit; and converting the overall network model into a simulated netlist of the integrated circuit, the simulated netlist comprising a plurality of physical devices.

For example, in a method for designing a network topology provided in an embodiment of the present disclosure, obtaining at least one network structure model includes: acquiring electrical characteristics required by the integrated circuit; and determining at least one network structure model based on the electrical characteristics.

For example, in a method for designing a network topology provided in an embodiment of the present disclosure, each network structure model includes: the module vertex submodel indicates attributes of the feature points of the preset area, and the boundary winding submodel indicates winding attributes for connecting the feature points.

For example, in a method for designing a network topology provided in an embodiment of the present disclosure, attributes of feature points include: feature point identification and coordinate information; the attributes of the windings include: winding mark, starting point and ending point.

For example, in a method for designing a network topology according to an embodiment of the present disclosure, splicing a plurality of instantiated models to obtain an overall network model corresponding to an integrated circuit includes: and splicing the plurality of instantiated models according to the coordinate information of the characteristic points to obtain an integral network model corresponding to the integrated circuit.

For example, in the method for designing a network topology provided in an embodiment of the present disclosure, for two adjacent instantiated models, at least one overlapping edge exists after the two instantiated models are spliced, and a gap area does not exist in the entire network model.

For example, in a method for designing a network topology provided by an embodiment of the present disclosure, converting an overall network model into a simulated netlist of an integrated circuit includes: aiming at each instantiation model in a plurality of instantiation models, acquiring an attribute value of a target attribute in a plurality of attributes in each instantiation model; determining a physical characteristic associated with the target attribute; determining a physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute; and for each instantiated model in the overall network model, representing the corresponding instantiated model by using a physical device to obtain a simulated netlist of the integrated circuit.

For example, in a method for designing a network topology provided in an embodiment of the present disclosure, a routing length is included in a target attribute, a physical characteristic associated with the routing length includes a resistance value of a routing within a unit length, and a physical device is determined based on an attribute value of the target attribute and the physical characteristic associated with the target attribute, including: the target resistance is determined based on the length of the windings and the resistance of the windings per unit length.

For example, in a method for designing a network topology provided in an embodiment of the present disclosure, each network structure model includes: the clock network structure model comprises a clock network topology structure or the power network structure model comprises a power network topology structure.

For example, in the method for designing a network topology provided in an embodiment of the present disclosure, the method further includes: and verifying whether the network topology structure of the integrated circuit meets the evaluation index or not by using the simulation netlist.

At least one embodiment of the present disclosure provides a network topology design apparatus of an integrated circuit, including: an obtaining unit configured to obtain at least one network structure model, each network structure model being generated by encapsulating a network structure of a preset area, the network structure of the preset area being a part of an integrated circuit, each network structure model including a plurality of attributes; the instantiation unit is configured to assign values to the plurality of attributes in each network structure model at least once to obtain a plurality of instantiation models; a splicing unit configured to splice the instantiated models to obtain an overall network model corresponding to the integrated circuit; and a netlist generation unit configured to convert the overall network model into a simulated netlist of the integrated circuit, the simulated netlist comprising a plurality of physical devices.

For example, in a network topology design apparatus provided in an embodiment of the present disclosure, the obtaining unit includes: an electrical characteristic acquisition subunit configured to acquire electrical characteristics required by the integrated circuit; and a model determining subunit configured to determine at least one network structure model from the electrical characteristics.

For example, in a network topology design apparatus provided in an embodiment of the present disclosure, each network structure model includes: the module vertex submodel indicates the attribute of the characteristic points of the preset area, and the boundary winding submodel indicates the attribute of the winding used for connecting the plurality of characteristic points.

For example, in a network topology design apparatus provided in an embodiment of the present disclosure, attributes of feature points include: feature point identification and coordinate information; the attributes of the windings include: winding mark, starting point and ending point.

For example, in the network topology design apparatus provided in an embodiment of the present disclosure, the splicing unit includes a splicing subunit configured to splice a plurality of instantiated models according to the coordinate information of the feature points, so as to obtain an overall network model corresponding to the integrated circuit.

For example, in the network topology design apparatus provided in an embodiment of the present disclosure, for two adjacent instantiated models, at least one overlapping edge exists after the two instantiated models are spliced, and no gap area exists in the entire network model.

For example, in a network topology design apparatus provided in an embodiment of the present disclosure, a netlist generating unit includes: the attribute value acquisition subunit is configured to acquire an attribute value of a target attribute in the plurality of attributes in each instantiated model aiming at each instantiated model in the plurality of instantiated models; a physical characteristic determination subunit configured to determine a physical characteristic associated with the target attribute; a physical device determination subunit configured to determine a physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute; and the simulation netlist generation subunit is configured to represent the corresponding instantiated model by using a physical device for each instantiated model in the whole network model so as to obtain the simulation netlist of the integrated circuit.

For example, in the network topology design apparatus provided by an embodiment of the present disclosure, the target attribute includes a winding length, the physical characteristic associated with the winding length includes a resistance value of the winding in the unit length, and the physical device determination subunit includes a resistance determination subunit configured to determine the target resistance based on the winding length and the resistance value of the winding in the unit length.

For example, in a network topology design apparatus provided in an embodiment of the present disclosure, each network structure model includes: the clock network structure model comprises a clock network topology structure or the power network structure model comprises a power network topology structure.

For example, in the network topology design apparatus provided in an embodiment of the present disclosure, the apparatus further includes a simulation unit configured to verify whether the network topology of the integrated circuit meets the evaluation index by using the simulated netlist.

For example, in some embodiments of the present disclosure, an adjustment unit is further included that is configured to readjust the at least one network structure model in response to the network topology of the integrated circuit not meeting the evaluation criterion.

At least one embodiment of the present disclosure provides an electronic device comprising a processor; a memory including one or more computer program modules; one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for implementing a network topology design method for an integrated circuit provided by any of the embodiments of the present disclosure.

At least one embodiment of the present disclosure provides a computer-readable storage medium for storing non-transitory computer-readable instructions, which when executed by a computer, can implement a method for designing a network topology of an integrated circuit provided in any embodiment of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1 is a flowchart illustrating a method for designing a network topology of an integrated circuit according to at least one embodiment of the present disclosure;

fig. 2A illustrates a schematic diagram of a network architecture model 200 provided by at least one embodiment of the present disclosure.

Fig. 2B illustrates a model structure 210 of the network structure model 200 provided by at least one embodiment of the present disclosure;

FIG. 2C illustrates a mapping relationship between the model structure 210 and the layout 220 provided by at least one embodiment of the present disclosure;

fig. 3A illustrates a flowchart of a method of step S10 in fig. 1 according to at least one embodiment of the present disclosure;

FIG. 3B illustrates a schematic diagram of at least one network fabric model of an integrated circuit provided by at least one embodiment of the present disclosure;

FIG. 3C illustrates instantiated models of network fabric model A and network fabric model B of FIG. 3B as provided by at least one embodiment of the present disclosure;

FIG. 3D is a schematic diagram of an overall network model resulting from stitching the instantiated models shown in FIG. 3C;

fig. 4 shows a flowchart of a method of step S40 provided by at least one embodiment of the present disclosure;

FIG. 5 illustrates a schematic diagram of a simulated netlist 500 obtained by representing an instantiated model with physical devices according to at least one embodiment of the disclosure;

fig. 6 is a flowchart illustrating another method for designing a network topology according to at least one embodiment of the present disclosure;

fig. 7 is a schematic block diagram illustrating a network topology design apparatus of an integrated circuit according to at least one embodiment of the disclosure;

fig. 8A illustrates a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

fig. 8B illustrates a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure; and

fig. 9 illustrates a schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

At present, for a complex topological structure of a single logic network, a plurality of Electronic Design Automation (EDA) tools are required for a complete verification process, the verification period is long, the detail requirement of each EDA tool is high, units in each network topological structure need to be actually placed and accurately connected, the method is not suitable for verifying rapid iteration, and the complex topological structure cannot be efficiently managed.

To this end, at least one embodiment of the present disclosure provides a network topology design method of an integrated circuit, a network topology design apparatus of an integrated circuit, an electronic device, and a computer-readable storage medium. The network topology structure design method of the integrated circuit comprises the following steps: obtaining at least one network structure model, each network structure model being generated by encapsulating a network structure in a preset area, the network structure in the preset area being a part of the integrated circuit, each network structure model including a plurality of attributes; performing at least one assignment on the plurality of attributes in each network structure model to obtain a plurality of instantiation models; splicing the instantiated models to obtain an overall network model corresponding to the integrated circuit; and converting the overall network model into a simulated netlist of the integrated circuit, the simulated netlist comprising a plurality of physical devices. The network topology structure design method of the integrated circuit can improve the efficiency of verifying the complex topology structure of a single logic network, shorten the verification period and is suitable for rapid iteration of verification.

Fig. 1 is a flowchart illustrating a method for designing a network topology of an integrated circuit according to at least one embodiment of the present disclosure.

As shown in FIG. 1, the method may include steps S10-S40.

Step S10: at least one network structure model is obtained, each network structure model is generated by packaging a network structure in a preset area, and each network structure model comprises a plurality of attributes.

Step S20: and performing at least one assignment on the plurality of attributes in each network structure model to obtain a plurality of instantiation models.

Step S30: and splicing the plurality of instantiated models to obtain an overall network model corresponding to the integrated circuit.

Step S40: the overall network model is converted into a simulated netlist of the integrated circuit, the simulated netlist including a plurality of physical devices.

In some embodiments of the present disclosure, the plurality of instantiated models are stitched to obtain an overall network model of the integrated circuit, and a simulated netlist is generated using the overall network model to verify a network topology using the simulated netlist. Because the whole network model is spliced by the plurality of instantiation models, when the verification result of the verification does not meet the evaluation index of the integrated circuit, only one or more instantiation models or network structure models corresponding to the instantiation models need to be modified, the integrated circuit does not need to be redesigned, and the units in each network topology structure do not need to be actually placed and accurately connected, so that the method is easy to rapidly adjust the network topology structure of the integrated circuit, shortens the verification period and facilitates rapid iteration. The method may be applied, for example, in the early trial design phase of chip design.

For example, for step S10, at least one network structure model may be read from the model library.

For example, at least one network fabric model is designed by a designer according to the target requirements of the integrated circuit and stored in a model library. For example, when the method is used to design a clock network topology, then at least one network structure model may be designed according to the clock specification requirements of the integrated circuit.

For example, the at least one network structure model may also be generated according to input instructions or input operations of a designer. The input instruction or input operation includes parameters such as the size and area of the network structure model.

In some embodiments of the present disclosure, each network structure model may include: the boundary winding sub-model indicates attributes of the feature points of the preset region, and the boundary winding sub-model indicates attributes of windings used for connecting the feature points.

Fig. 2B illustrates a model structure 210 of the network structure model 200 provided by at least one embodiment of the present disclosure.

In some embodiments of the present disclosure, the network structure model 200 is encapsulated to the model structure 210 so as to perform the splicing operation in the subsequent step S30.

In some embodiments of the present disclosure, model structure 210 may represent a layout of a preset region. For example, the model structure 210 is obtained by mapping the layout of the preset region. For example, a metal line in a layout is mapped as a straight line, and two metal nodes connected by the metal line are mapped as a circle. The metal nodes are used, for example, to connect different physical devices in the integrated circuit, and may be vias, used to connect physical devices located at different layers, and the like. The following describes a mapping relationship between the model structure 210 and the layout of the preset region with reference to fig. 2C, and details are not repeated here.

As shown in FIG. 2A, the network architecture model 200 may include, among other things, a module vertex submodel 206 and a boundary winding submodel 207. The network architecture model 200 may also include a drive unit vertex sub-model 208.

The module vertex submodel 206 indicates attributes of feature points of a preset region. For example, the feature point of the preset region may be a vertex of the preset region, and the vertex is used as a vertex of the network structure model 200 corresponding to the preset region. For example, four vertices of a preset area in a rectangular shape may be used as the vertices of the network structure model 200.

The boundary winding submodel 207 indicates an attribute of a winding for connecting a plurality of feature points, for example, an attribute of a boundary winding indicating a preset area. For example, four sides of the predetermined area having a rectangular shape may be wound as the boundary of the predetermined area.

The drive unit vertex submodel 208 is used to represent the vertices of the drive units.

As shown in fig. 2B, the network structure model 200 may include a driving unit submodel 201, a load unit submodel 202, a winding submodel 203, and a node submodel 204 in addition to a module vertex submodel 206, a boundary winding submodel 207, and a driving unit vertex submodel 208. Although the drive unit submodel 201, the load unit submodel 202, the winding submodel 203, and the node submodel 204 are not shown in the network architecture model 200 of fig. 2A, since the network architecture model 200 of fig. 2A is obtained by encapsulating the model architecture 210 of fig. 2B, the network architecture model 200 naturally includes the drive unit submodel 201, the load unit submodel 202, the winding submodel 203, and the node submodel 204.

For example, the driving element submodel 201 represents driving elements in a preset area in an integrated circuit. The drive element submodel 201 may include drive attributes such as power consumption of the drive, volume of the drive, and the like. The designer may or may not set the driving attributes of the driving element submodel 201.

For example, load cell submodel 202 represents a load in a predetermined area of an integrated circuit. The load cell submodel 202 may include load attributes, such as electrical characteristics of the load, and the like. The designer may or may not set the load attributes of the load cell submodel 202.

For example, node sub-model 204 represents a node, such as a metal node, in a predetermined area of an integrated circuit. The nodes are used to connect different devices in the integrated circuit.

For example, the attribute of the node may include a node identification, coordinate information of the node, and the like. The node identification may be, for example, the name of the node. The coordinate information may include, for example, coordinates of the node in a two-dimensional coordinate system or a three-dimensional coordinate system. The attributes of the node may include, for example, a name, a node type, and custom attributes of the node in the instantiated model after the node is instantiated, in addition to the node identifier and the coordinate information. The node identification is used to distinguish different nodes.

In some embodiments of the present disclosure, the attribute of a node may be represented by a set T, for example, the set T ═ { id, locX, locY, node type, grid, … … }, where id represents the name of the node, locX represents the X-axis coordinates of the node, locY represents the Y-axis coordinates of the node, node type represents the type of the node, and grid represents the name of the node in the instantiated model after the node is instantiated.

The module vertex submodel 206 in the network structure model 200 may be a node in the node submodel 204 located at a vertex of a predetermined area, and thus the module vertex submodel 206 includes a feature point identification for distinguishing different vertices in the network structure model 200 and coordinate information.

For example, routing submodel 203 represents routing of a predetermined area of an integrated circuit, the routing used to connect a plurality of nodes. The winding submodel 203 includes attributes of the winding, such as winding identification, start and end points, and the like. The winding identification is used to distinguish between different windings in the network fabric model 200. The attributes of the winding may include, in addition to the winding identification, start point and end point, the length of the winding, the type of the winding, the name in the instantiated model after instantiation, the detour mode, custom attributes, and the like. For example, the winding wire can be classified into a plurality of types according to the function of the winding wire. For example, the routing connecting the physical devices located at the same layer is of a first type, the routing connecting the physical devices at two adjacent layers is of a second type, and so on. The meander pattern may refer to the degree of curvature of the winding.

In some embodiments of the present disclosure, the attributes of a winding are represented by a set S, e.g., S ═ from, to, label, net length, net type, grid id, detour mode, user attribute, … … }, from represents a starting point, to represents an ending point, label represents the name of the winding, net length represents the length of the winding, net type represents the type of the winding, grid id represents the name in the instantiated model after being instantiated, detour mode represents the detour mode, user attribute represents the custom attribute.

Custom attributes in this context refer to attributes of the sub-model that the designer defines according to actual requirements. In the embodiment of the present disclosure, the attribute of each sub-model is not limited to the above attribute, and each sub-model in practical application may contain more or less attributes than the above attribute of each sub-model, and a designer may set the attribute of each sub-model according to practical requirements.

Fig. 2C illustrates a mapping relationship between the model structure 210 and the layout 220 of the preset region according to at least one embodiment of the present disclosure.

As shown in FIG. 2C, the load in the layout 220 is mapped to the load in the model structure 210. For example, the loads 302 on both sides of the via 301 in fig. 2C are mapped into two stacked load cell submodels 202 in the model structure 210.

As shown in FIG. 2C, metal nodes 306 that are vertices of the predefined region in layout 220 may be mapped to module vertex submodels 206 in model structure 210.

As shown in FIG. 2C, the metal lines 303 in the layout 220 are mapped to the winding submodels 203 in the model structure 210.

As shown in FIG. 2C, other metal nodes 304 in the layout 220, other than as boundary vertices, may be mapped to node sub-models 204 in the model structure 210.

As shown in fig. 2C, the drive 305 in the layout 220 may be mapped to a drive unit sub-model 201 in the model structure 210.

It should be understood that the mapping relationship shown in fig. 2C is only shown for facilitating understanding of the embodiment of the disclosure, and in an actual design, a designer may define the mapping relationship by himself, and the mapping relationship is not limited to the embodiment shown in fig. 2C. In addition, in an actual design, the layout 220 may not exist, that is, a designer does not need to design the layout in advance, and the designer only needs to determine the mapping relationship to obtain the network structure model, and fig. 2C is only shown for convenience of understanding the embodiment of the present disclosure.

Fig. 3A illustrates a flowchart of a method of step S10 in fig. 1 according to at least one embodiment of the present disclosure.

As shown in fig. 3A, step S10 may include step S11 and step S12.

Step S11: the electrical characteristics required for the integrated circuit are obtained.

Step S12: at least one network structure model is determined from the electrical characteristics.

For step S11, the electrical characteristics may include, for example, capacitance values, resistance values, output waveforms, and the like.

In some embodiments of the present disclosure, the electrical characteristics required of the integrated circuit may be achieved through metal mesh interconnects of a network topology of the integrated circuit. For example, the resistance value of a resistor obtained by interconnecting metal meshes.

For step S12, for example, a plurality of different electrical characteristics required for the integrated circuit are determined, and for each electrical characteristic, a network structure is generated such that the network structure has the electrical characteristic. The network structure is used as a network structure of a preset area in the integrated circuit, and the network structure is packaged to generate a network structure model.

Fig. 3B illustrates a schematic diagram of at least one network architecture model of an integrated circuit provided by at least one embodiment of the present disclosure.

As shown in fig. 3B, the integrated circuit includes 2 network structure models, network structure model a and network structure model B.

The network structure model a and the network structure model B have different attributes, for example, the network structure model a and the network structure model B have different lengths.

It is understood that the network architecture model a and the network architecture model B are only schematic representations of at least one network architecture model of an integrated circuit and do not have a limiting effect on the present disclosure. For example, an integrated circuit may have more (3, 4, … …) network fabric models.

For step S20: the plurality of attributes in each network structure model may or may not be assigned one or more times. And assigning values to a plurality of attributes in the network structure model each time to obtain an instantiated model.

For example, assigning each attribute in the set T once and assigning each attribute in S once results in an instantiated model.

In embodiments of the present disclosure, the number of times different network architecture models are assigned may be different.

Fig. 3C illustrates instantiated models of network structure model a and network structure model B in fig. 3B provided by at least one embodiment of the present disclosure.

As shown in fig. 3C, for example, 2 assignments to network structure model a result in two instantiation models of network structure model a, instantiation model a1 and instantiation model a 2. And 4-time assignment is carried out on the network structure model B to obtain four instantiation models of the network structure model B, namely instantiation model B1, instantiation model B2, instantiation model B3 and instantiation model B4.

For step S30: for example, according to the coordinate information of the feature points, the plurality of instantiated models are spliced to obtain an overall network model corresponding to the integrated circuit. In the embodiment, the instantiated models directly include the coordinate information of the feature points, so that the plurality of instantiated models can be spliced directly according to the coordinate information.

FIG. 3D is a schematic diagram of the entire network model resulting from stitching the instantiated models shown in FIG. 3C.

As shown in fig. 3C and 3D, instantiated model a1 includes coordinate information for module vertex submodels a11, a12, a13, and a14, and instantiated model a2 includes coordinate information for module vertex submodels a21, a22, a23, and a 24. Since the coordinate information of the vertex a13 and the vertex a12 is the same as the coordinate information of the vertex a21 and the vertex a22, respectively, in step S30, the vertex a13 and the vertex a21 overlap to one point, and the vertex a12 and the vertex a22 overlap to one point, thereby stitching the vertices a1 and a 2.

The splicing method between instantiation model B1, instantiation model B2, instantiation model B3 and instantiation model B4 and instantiation model A1 and instantiation model A2 is similar to the splicing method between instantiation model A1 and instantiation model A2, and is not described in detail here.

The integral network model shown in fig. 3D is obtained by splicing a plurality of instantiated models. As shown in fig. 3D, in some embodiments of the present disclosure, for two adjacent instantiated models, there is at least one overlapping edge after the two instantiated models are spliced, and there is no gap area in the entire network model.

In some embodiments of the present disclosure, splicing the instantiated models is not limited to splicing on a plane, but also includes stereo splicing, which may characterize the interconnection relationship between different metal layers.

Fig. 4 shows a flowchart of a method of step S40 provided by at least one embodiment of the present disclosure.

As shown in fig. 4, the method may include steps S41 to S44.

Step S41: and acquiring the attribute value of the target attribute in the attributes in each instantiation model aiming at each instantiation model in the plurality of instantiation models.

Step S42: a physical characteristic associated with the target attribute is determined.

Step S43: the physical device is determined based on the attribute value of the target attribute and the physical characteristic associated with the target attribute.

Step S44: for each instantiated model in the overall network model, representing the corresponding instantiated model by using a physical device to obtain a simulated netlist of the integrated circuit.

For step S41, the target property may be at least one of the plurality of properties that has an impact on the selection of the physical device in the simulated netlist. For example, the simulated netlist includes resistors, and the routing length affects the resistance values in the simulated netlist, so the target property may include the routing length. For another example, the simulated netlist includes parasitic capacitances, and the distances between the two loads that generate the parasitic capacitances have an effect on the parasitic capacitances, so the target property may include coordinate information of each of the two loads.

In some embodiments of the present disclosure, the target attribute may be determined according to an input or selection operation of a user, for example, so that an attribute value of the target attribute is read from the network structure model. In other embodiments of the present disclosure, the target attribute may be predetermined.

For step S42, the physical characteristics associated with the target property may be physical characteristics that work in conjunction with the target property to determine physical devices in the simulated netlist.

For example, the length of the wire and the resistance of the wire per unit length determine the resistance of the wire in the integrated circuit, and thus the physical characteristic associated with the length of the wire includes the resistance of the wire per unit length.

For step S43: for example, the physical device is determined based on a calculated relationship between the attribute value of the target attribute, the physical characteristic associated with the target attribute, and the physical parameter of the physical device. For example, the target resistance is determined based on the length of the windings and the resistance of the windings per unit length. As another example, the parasitic capacitance is determined based on the dielectric constant of the interplate medium, the distance between the two loads, and the facing area of the two loads.

For step S44, for example, for the overall network model shown in FIG. 3D, for each instantiated model, substituting the physical device into the instantiated model obtains a simulated netlist of the integrated circuit. The physical devices may include, for example, resistance-Capacitance (RC), load, drive, and the like.

Fig. 5 illustrates a schematic diagram of a simulated netlist 500 obtained by representing an instantiated model with physical devices according to at least one embodiment of the present disclosure.

For example, fig. 5 shows a simulated netlist 500 obtained by substituting physical devices such as resistance-Capacitance (RC), load, and driver into the instantiated model a 1.

As shown in FIG. 5, simulated netlist 500 includes at least one driver 501, winding 502, and load 503.

In the embodiment shown in fig. 5, since the winding has a resistance, the winding is represented by a physical device resistance in fig. 5, and the resistance value representing the resistance of the winding is determined according to the method of the above-described step S43, that is, the resistance value representing the resistance of the winding is determined according to the length of the winding and the resistance value of the winding per unit length.

As shown in fig. 5, the load 503 may include a capacitor, a transistor, a light emitting element, and the like, and those skilled in the art can set the load according to actual needs.

In some embodiments of the present disclosure, the method for designing a network topology described in any of the above embodiments may be applied to design of a clock network topology or design of a power supply network topology. When the network topology structure design method is applied to the design of a clock network topology structure, each network structure model is a clock network structure model; or, when the network topology design method is applied to the design of the power supply network topology, each network structure model is a power supply network structure model. When the network topology design method is applied to the design of a clock network topology, the driving unit may be a clock signal; alternatively, when the network topology design method is applied to the design of a power supply network topology, the driving unit may be a power supply.

Fig. 6 is a flowchart illustrating another method for designing a network topology according to at least one embodiment of the present disclosure.

As shown in fig. 6, the method may further include a step S50 in addition to the steps S10 to S40 shown in fig. 1.

At step S50: and verifying whether the network topology structure of the integrated circuit meets the evaluation index or not by using the simulation netlist.

For example, when the network topology design method is applied to design of a clock network topology, the evaluation index may include a clock requirement index, such as setup time (setup time) and hold time (hold time).

For example, the simulated netlist is simulated to verify that the clock network topology meets the set-up and hold time requirements.

For example, the network topology of the integrated circuit is verified using an EDA tool to determine whether the network topology of the integrated circuit meets evaluation criteria.

If the network topology structure meets the evaluation index, the wiring can be laid out according to the simulation netlist, and the actual production process is started.

With continued reference to fig. 6, in other embodiments of the present disclosure, the method for designing a network topology of an integrated circuit may further include step S60 in addition to the steps S10 to S50 shown in fig. 1.

Step S60: in response to the network topology of the integrated circuit not meeting the evaluation criterion, the at least one network structure model is readjusted.

If the network topology structure does not meet the evaluation index, one or more network structure models can be adjusted, a simulation netlist is obtained based on at least one adjusted network structure model, and simulation is carried out again until the network topology structure meeting the evaluation index is obtained.

For example, some or all of the network structure model attributes are adjusted to readjust at least one of the network structure models. Namely, the at least one network structure model is adjusted according to the verification result of the overall network topology structure of the integrated circuit obtained by splicing the at least one network structure model.

In other embodiments of the present disclosure, if the network topology does not meet the evaluation index, one or more instantiated models may be adjusted and the simulated netlist is again obtained for simulation.

According to the embodiment of the disclosure, when the verification result of the verification does not meet the evaluation index of the integrated circuit, only one or more instantiation models or network structure models corresponding to the instantiation models need to be modified, the integrated circuit does not need to be redesigned, and the units in each network topology do not need to be actually placed and accurately connected, so that the method is easy to rapidly adjust the network topology of the integrated circuit, shortens the verification period, and facilitates rapid iteration.

Fig. 7 illustrates a schematic block diagram of a network topology design apparatus 700 of an integrated circuit according to at least one embodiment of the present disclosure.

For example, as shown in fig. 7, the network topology design apparatus 700 of the integrated circuit includes an obtaining unit 710, an instantiating unit 720, a splicing unit 730, and a netlist generating unit 740.

The obtaining unit 710 is configured to obtain at least one network structure model, where each network structure model is generated by encapsulating a network structure in a preset area, and the network structure in the preset area is a part of an integrated circuit, and each network structure model includes a plurality of attributes.

The acquisition unit 710 may perform step S10 described in fig. 1, for example.

And the instantiation unit 720 is configured to assign at least one value to the plurality of attributes in each network structure model to obtain a plurality of instantiation models.

The instantiation unit 720 may, for example, perform step S20 described in fig. 1.

A stitching unit 730 configured to stitch the instantiated models to obtain an overall network model corresponding to the integrated circuit.

The splicing unit 730 may, for example, perform step S30 described in fig. 1.

A netlist generation unit 740 configured to convert the overall network model into a simulated netlist of the integrated circuit, the simulated netlist comprising a plurality of physical devices.

Netlist generation unit 740 may, for example, perform step S40 described in fig. 1.

For example, in some embodiments of the present disclosure, the obtaining unit includes: an electrical characteristic acquisition subunit configured to acquire electrical characteristics of a plurality of physical devices in the integrated circuit; and a model determining subunit configured to determine at least one network structure model based on the electrical characteristics of the plurality of physical devices.

For example, in some embodiments of the present disclosure, each network structure model includes: the module vertex submodel indicates the attribute of the characteristic points of the preset area, and the boundary winding submodel indicates the attribute of the winding used for connecting the plurality of characteristic points.

For example, in some embodiments of the present disclosure, the attributes of the feature points include: feature point identification and coordinate information; the attributes of the windings include: winding mark, starting point and ending point.

For example, in some embodiments of the present disclosure, the stitching unit includes a stitching subunit configured to stitch the instantiated models according to the coordinate information of the feature points, so as to obtain an overall network model corresponding to the integrated circuit.

For example, in some embodiments of the present disclosure, for two adjacent instantiated models, there is at least one overlapping edge after the two instantiated models are spliced, and there is no gap area in the entire network model.

For example, in some embodiments of the present disclosure, a netlist generation unit includes: the attribute value acquisition subunit is configured to acquire an attribute value of a target attribute in the plurality of attributes in each instantiated model aiming at each instantiated model in the plurality of instantiated models; a physical characteristic determination subunit configured to determine a physical characteristic associated with the target attribute; a physical device determination subunit configured to determine a physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute; and the simulation netlist generation subunit is configured to represent the corresponding instantiation model by using the physical device for each instantiation model in the whole network model so as to obtain the simulation netlist of the integrated circuit.

For example, in some embodiments of the present disclosure, the target attribute includes a winding length, the physical characteristic associated with the winding length includes a resistance value of the winding per unit length, and the physical device determination subunit includes a resistance determination subunit configured to determine the target resistance based on the winding length and the resistance value of the winding per unit length.

For example, in some embodiments of the present disclosure, each network structure model includes: the clock network structure model comprises a clock network topology structure or the power network structure model comprises a power network topology structure.

For example, in some embodiments of the present disclosure, a simulation unit configured to verify whether a network topology of the integrated circuit satisfies an evaluation index using the simulated netlist is further included.

For example, in some embodiments of the present disclosure, an adjustment unit is further included, configured to readjust the at least one network structure model in response to the network topology of the integrated circuit not satisfying the evaluation criterion.

For example, fetch unit 710, instantiation unit 720, stitching unit 730, and netlist generation unit 740 may be hardware, software, firmware, and any feasible combination thereof. For example, the obtaining unit 710, the instantiating unit 720, the splicing unit 730, and the netlist generating unit 740 may be special or general circuits, chips, devices, or the like, or may be a combination of processors and memories. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.

It should be noted that, in the embodiment of the present disclosure, each unit of the network topology design apparatus 700 corresponds to each step of the foregoing network topology design method, and for specific functions of the network topology design apparatus 700, reference may be made to the related description of the network topology design method, which is not described herein again. The components and structure of the network topology designing apparatus 700 shown in fig. 7 are only exemplary and not restrictive, and the network topology designing apparatus 700 may further include other components and structures as necessary.

At least one embodiment of the present disclosure also provides an electronic device that includes a processor and memory, the memory including one or more computer program modules. One or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for implementing the network topology design method described above. The electronic equipment can improve the efficiency of verifying the complex topological structure of the single logic network, shortens the verification period and is suitable for quick iteration of verification.

Fig. 8A is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. As shown in fig. 8A, the electronic device 800 includes a processor 810 and a memory 820. The memory 820 is used to store non-transitory computer readable instructions (e.g., one or more computer program modules). The processor 810 is configured to execute non-transitory computer readable instructions, which when executed by the processor 810 may perform one or more of the steps of the network topology design method described above. The memory 820 and the processor 810 may be interconnected by a bus system and/or other form of connection mechanism (not shown).

For example, processor 810 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. The processor 810 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 800 to perform desired functions.

For example, memory 820 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), hard disk, Erasable Programmable Read Only Memory (EPROM), portable compact disk read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by processor 810 to implement various functions of electronic device 800. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium.

It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description on the network topology design method for specific functions and technical effects of the electronic device 800, and details are not described here.

Fig. 8B is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 900 is, for example, suitable for implementing the network topology design method provided by the embodiments of the present disclosure. The electronic device 900 may be a terminal device or the like. It should be noted that the electronic device 900 shown in fig. 8B is only one example and does not bring any limitations to the function and scope of the embodiments of the present disclosure.

As shown in fig. 8B, electronic device 900 may include a processing means (e.g., central processing unit, graphics processor, etc.) 910 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)920 or a program loaded from a storage means 980 into a Random Access Memory (RAM) 930. In the RAM930, various programs and data necessary for the operation of the electronic apparatus 900 are also stored. The processing device 910, the ROM 920, and the RAM930 are connected to each other through a bus 940. An input/output (I/O) interface 950 is also connected to bus 940.

Generally, the following devices may be connected to the I/O interface 950: input devices 960 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 970 including, for example, a Liquid Crystal Display (LCD), speaker, vibrator, or the like; storage 980 including, for example, magnetic tape, hard disk, etc.; and a communication device 990. The communication means 990 may allow the electronic device 900 to communicate wirelessly or by wire with other electronic devices to exchange data. While fig. 8B illustrates an electronic device 900 having various means, it is to be understood that not all illustrated means are required to be implemented or provided, and that the electronic device 900 may alternatively be implemented or provided with more or less means.

For example, according to an embodiment of the present disclosure, the above-described network topology design method may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the network topology design method described above. In such embodiments, the computer program may be downloaded and installed from a network through the communication device 990, or installed from the storage device 980, or installed from the ROM 920. When executed by the processing device 910, the computer program may implement the functions defined in the network topology design method provided by the embodiment of the disclosure.

At least one embodiment of the present disclosure also provides a computer-readable storage medium for storing non-transitory computer-readable instructions that, when executed by a computer, can implement the network topology design method described above. By using the computer readable storage medium, the efficiency of verifying the complex topological structure of the single logic network can be improved, the verification period is shortened, and the method is suitable for quick iteration of verification.

Fig. 9 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. As shown in fig. 9, the storage medium 1000 is used to store non-transitory computer readable instructions 1010. For example, the non-transitory computer readable instructions 1010, when executed by a computer, may perform one or more steps in a method of designing a network topology according to the above.

For example, the storage medium 1000 may be applied to the electronic device 800 described above. For example, the storage medium 1000 may be the memory 820 in the electronic device 800 shown in fig. 8A. For example, the related description about the storage medium 1000 may refer to the corresponding description of the memory 820 in the electronic device 800 shown in fig. 8A, and is not repeated here.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A method for designing a network topology of an integrated circuit, comprising:

obtaining at least one network structure model, wherein each network structure model is generated by encapsulating a network structure in a preset area, the network structure in the preset area is used as a part of the integrated circuit, and each network structure model comprises a plurality of attributes;

performing at least one assignment on the plurality of attributes in each network structure model to obtain a plurality of instantiation models;

splicing the instantiated models to obtain an overall network model corresponding to the integrated circuit; and

converting the overall network model to a simulated netlist of the integrated circuit, wherein the simulated netlist comprises a plurality of physical devices.

2. The method of claim 1, wherein obtaining the at least one network architecture model comprises:

acquiring electrical characteristics required by the integrated circuit; and

determining the at least one network structure model from the electrical characteristics.

3. The method of claim 1, wherein each of the network fabric models comprises: a module vertex submodel and a boundary winding submodel,

the module vertex sub-model indicates the attribute of the feature point of the preset area, and the boundary winding sub-model indicates the attribute of a winding used for connecting a plurality of feature points.

4. The method of claim 3, wherein the attributes of the feature points comprise: feature point identification and coordinate information;

the attributes of the winding include: winding mark, starting point and ending point.

5. The method of claim 4, wherein stitching the instantiated models to arrive at the overall network model for the integrated circuit comprises:

and splicing the plurality of instantiated models according to the coordinate information of the feature points to obtain the overall network model corresponding to the integrated circuit.

6. The method of claim 1, wherein, for two adjacent instantiated models, there is at least one overlapping edge after the two instantiated models are spliced,

no void regions exist in the overall network model.

7. The method of claim 1, wherein converting the overall network model to a simulated netlist of the integrated circuit comprises:

aiming at each instantiation model in the multiple instantiation models, acquiring an attribute value of a target attribute in multiple attributes in each instantiation model;

determining a physical characteristic associated with the target attribute;

determining the physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute; and

and for each instantiation model in the overall network model, representing the corresponding instantiation model by using the physical device to obtain a simulation netlist of the integrated circuit.

8. The method of claim 7, wherein the target attribute comprises a wire length, the physical characteristic associated with the wire length comprises a resistance value of the wire per unit length,

determining the physical device based on the attribute value of the target attribute and a physical characteristic associated with the target attribute, comprising:

and determining a target resistance based on the winding length and the resistance value of the winding in the unit length.

9. A method according to any one of claims 1 to 8, wherein each network structure model comprises: a clock network architecture model or a power network architecture model,

the clock network structure model comprises a clock network topology and the power network structure model comprises a power network topology.

10. The method of any of claims 1-8, further comprising:

and verifying whether the network topology structure of the integrated circuit meets evaluation indexes or not by using the simulation netlist.

11. The method of claim 10, further comprising:

readjusting the at least one network fabric model in response to the network topology of the integrated circuit not meeting an evaluation criterion.

12. An apparatus for designing a network topology of an integrated circuit, comprising:

an obtaining unit configured to obtain at least one network structure model, wherein each network structure model is generated by encapsulating a network structure of a preset area, the network structure of the preset area being a part of the integrated circuit, and each network structure model comprises a plurality of attributes;

the instantiation unit is configured to assign values to the plurality of attributes in each network structure model at least once to obtain a plurality of instantiation models;

a splicing unit configured to splice the instantiated models to obtain an overall network model corresponding to the integrated circuit; and

a netlist generation unit configured to convert the overall network model into a simulated netlist of the integrated circuit, wherein the simulated netlist comprises a plurality of physical devices.

13. The apparatus of claim 12, wherein the obtaining unit comprises:

an electrical characteristic acquisition subunit configured to acquire electrical characteristics required by the integrated circuit; and

a model determining subunit configured to determine the at least one network structure model from the electrical characteristics.

14. The apparatus of claim 12, wherein the netlist generation unit comprises:

an attribute value obtaining subunit configured to obtain, for each of the instantiated models, an attribute value of a target attribute of the plurality of attributes in the each instantiated model;

a physical property determination subunit configured to determine a physical property associated with the target attribute;

a physical device determination subunit configured to determine the physical device based on the attribute value of the target attribute and the physical characteristic associated with the target attribute; and

and the simulation netlist generation subunit is configured to represent the corresponding instantiation model by the physical device for each instantiation model in the overall network model so as to obtain the simulation netlist of the integrated circuit.

15. The apparatus of claim 12, further comprising:

and the simulation unit is configured to verify whether the network topology structure of the integrated circuit meets the evaluation index by using the simulation netlist.

16. An electronic device, comprising:

a processor;

a memory comprising one or more computer program instructions;

wherein the one or more computer program instructions are stored in the memory and when executed by the processor implement the method of network topology design of an integrated circuit of any of claims 1-11.

17. A computer-readable storage medium, non-transitory, storing computer-readable instructions, wherein the computer-readable instructions, when executed by a processor, implement the method of designing a network topology for an integrated circuit of any of claims 1-11.