CN115658158A

CN115658158A - PCIE (peripheral component interface express) equipment management method, device, equipment and readable storage medium

Info

Publication number: CN115658158A
Application number: CN202211412203.2A
Authority: CN
Inventors: 郑媛
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2023-01-31

Abstract

The application relates to the field of computers, and discloses a PCIE (peripheral component interface express) equipment management method, a device, equipment and a readable storage medium, wherein when a BIOS (basic input output System) determines that link training of PCIE equipment and an IIO root port is not finished in an IIO initialization stage in a starting process, an auxiliary bus reset value of a bridge control register corresponding to the IIO root port is written with 1 so as to control the IIO root port to trigger hot reset; judging whether the state parameters of a link state register in a PCIE configuration space meet preset conditions or not; the preset conditions are that the link activation value of a data link layer is 1, the current link speed is a preset speed, and the negotiated link bandwidth is a preset bandwidth; if yes, controlling the IIO root port and the PCIE equipment to perform link training again so that the IIO root port can identify the PCIE equipment; if not, sending out early warning information. The BIOS recovers and identifies the lost PCIE equipment in the IIO initialization stage in the starting process.

Description

PCIE (peripheral component interface express) equipment management method, device, equipment and readable storage medium

Technical Field

The present application relates to the field of computers, and in particular, to a PCIE device management method, apparatus, device, and computer-readable storage medium.

Background

The BIOS (Basic Input Output System), as a program solidified on a ROM chip on a computer motherboard, implements initialization of a processor, a memory, a chipset, and various Input/Output devices on a server motherboard in a boot process, provides hardware settings and control of the bottommost layer for the computer, and also provides the most direct information and the fastest repair for fault diagnosis of the server.

An IIO (Integrated Input/Output module) of the processor provides a PCIE (peripheral component interconnect express) interface, and when the BIOS is started to initialize the IIO, the BIOS detects an IIO root port and a link of the PCIE device. When a PCIE device is lost in a starting process, it can be found that the PCIE device is lost before the system is started, at this time, system analysis needs to be performed from hardware and software aspects, such as a motherboard, a PCIE device interface (e.g., a riser card, a backplane, and the like) and signal quality, and analysis needs to be performed from software aspects, such as code defects and writing of debugging codes to assist hardware in performing problem analysis. The loss probability of the PCIE device is low in the starting process, but once the PCIE device appears, the time for reproduction, debugging and analysis is generally long, and the production of the server and the operation and maintenance of the client are greatly affected.

Therefore, how to solve the above technical problems should be a great concern to those skilled in the art.

Disclosure of Invention

The application aims to provide a PCIE equipment management method, a device, equipment and a computer readable storage medium, so as to avoid the problem that the PCIE equipment is lost in the BIOS starting process.

In order to solve the above technical problem, the present application provides a PCIE device management method, including:

when determining that link training of PCIE equipment and an IIO root port is not finished in an IIO initialization stage in a starting process of a BIOS (basic input output System), writing 1 to an auxiliary bus reset value of a bridge control register corresponding to the IIO root port so as to control the IIO root port to trigger hot reset;

judging whether the state parameters of a link state register in a PCIE configuration space meet preset conditions or not; the preset conditions are that the link activation value of a data link layer is 1, the current link speed is a preset speed, and the negotiated link bandwidth is a preset bandwidth;

if the state parameter meets the preset condition, controlling the IIO root port and the PCIE equipment to perform link training again so that the IIO root port identifies the PCIE equipment;

and if the state parameter does not meet the preset condition, sending out early warning information.

Optionally, if the state parameter does not satisfy the preset condition, sending out the warning information includes:

if the state parameter does not meet the preset condition, returning to the step of writing 1 to the auxiliary bus reset value of the bridge control register corresponding to the IIO root port;

judging whether the execution times of writing 1 into the auxiliary bus reset value of the bridge control register corresponding to the IIO root port reaches a preset time threshold value or not; the preset time threshold value is not less than 2;

and if the execution times reach the preset time threshold, sending out early warning information.

Optionally, the sending out the warning information includes:

and sending the identification information of the PCIE equipment corresponding to the IIO root port to a substrate management controller so that the substrate management controller can store the identification information to an SEL log.

Optionally, the sending out the warning information includes:

and sending the identification information of the PCIE equipment corresponding to the IIO root port to display equipment.

Optionally, when the BIOS determines that link training of the PCIE device and the IIO root port is not completed in the IIO initialization stage in the starting process, writing the auxiliary bus reset value of the bridge control register corresponding to the IIO root port to 1 to control the IIO root port to trigger the warm reset, further including:

when the BIOS is started to IIO initialization, reading the state parameters of the link state register in the PCIE configuration space corresponding to the IIO root port;

judging whether the current link speed and the negotiated link bandwidth in the state parameters are 0 or not;

if the current link speed and the negotiated link bandwidth are not 0, judging whether the link activation value of the data link layer is 0;

and if the data link layer link activation value is 0, determining that the link training of the PCIE equipment and the IIO root port is not finished.

Optionally, after determining that the link training of the PCIE device and the IIO root port is not completed, the method further includes:

and sending out early warning information.

Optionally, reading the state parameter of the link state register in the PCIE configuration space corresponding to the IIO root port includes:

and polling and reading the state parameters of the link state register in the PCIE configuration space corresponding to the IIO root port.

The present application further provides a PCIE device management apparatus, including:

the trigger module is used for writing an auxiliary bus reset value of a bridge control register corresponding to the IIO root port into 1 to control the IIO root port to trigger hot reset when the BIOS determines that the link training of the PCIE equipment and the IIO root port is not finished in the IIO initialization stage in the starting process;

the first judgment module is used for judging whether the state parameters of the link state registers in the PCIE configuration space meet preset conditions or not; the preset conditions are that the link activation value of a data link layer is 1, the current link speed is a preset speed, and the negotiated link bandwidth is a preset bandwidth;

the control identification module is configured to control the IIO root port and the PCIE device to perform link training again if the state parameter meets the preset condition, so that the IIO root port identifies the PCIE device;

and the first early warning module is used for sending out early warning information if the state parameter does not meet the preset condition.

a memory for storing a computer program;

and the processor is configured to implement any of the above steps of the PCIE device management method when executing the computer program.

The present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of any one of the PCIE device management methods described above are implemented.

The application provides a PCIE equipment management method, which comprises the following steps: when determining that link training of PCIE equipment and an IIO root port is not finished in an IIO initialization stage in a starting process of a BIOS (basic input output System), writing 1 to an auxiliary bus reset value of a bridge control register corresponding to the IIO root port so as to control the IIO root port to trigger hot reset; judging whether the state parameters of a link state register in a PCIE configuration space meet preset conditions or not; the preset conditions are that the link activation value of a data link layer is 1, the current link speed is a preset speed, and the negotiated link bandwidth is a preset bandwidth; if the state parameter meets the preset condition, controlling the IIO root port and the PCIE equipment to perform link training again so that the IIO root port identifies the PCIE equipment; and if the state parameter does not meet the preset condition, sending out early warning information.

Therefore, in the application, when discovering that the link training between the PCIE device and the IIO root port is abnormal in the IIO initialization stage in the starting process, the BIOS resets the IIO root port, and then determines the state parameter of the link state register in the PCIE configuration space corresponding to the IIO root port to determine. When the state parameter meets the preset parameter, the IIO root port is successfully reset, so that the IIO root port and the PCIE equipment are subjected to link training again, the PCIE equipment is reconnected, and the identification of the PCIE equipment is recovered; and when the state parameters do not meet the preset parameters, carrying out early warning notification so as to notify production and operation and maintenance to check and recover the identification of the PCIE equipment. Therefore, the problem that PCIE equipment is lost in the BIOS starting process can be avoided, and production of a server production line and operation and maintenance of a client are facilitated.

In addition, the application also provides a device, equipment and a computer readable storage medium with the advantages.

Drawings

For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a flowchart of a PCIE device management method provided in an embodiment of the present application;

fig. 2 is a flowchart of another PCIE device management method provided in the embodiment of the present application;

fig. 3 is a flowchart of another PCIE device management method provided in the embodiment of the present application;

fig. 4 is a flowchart of another PCIE device management method provided in the embodiment of the present application;

fig. 5 is a block diagram of a structure of a PCIE device management apparatus provided in the embodiment of the present application;

fig. 6 is a block diagram of a structure of a PCIE device management device provided in the embodiment of the present application.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the following detailed description is given with reference to the accompanying drawings. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As described in the background section, when a PCIE device is lost during BIOS startup, the loss of the PCIE device cannot be found until the system is started, and at this time, system analysis needs to be performed from various aspects of hardware and software. The loss probability of the PCIE device in the starting process is relatively low, but once the PCIE device appears, the time spent in reproduction, debugging and analysis is generally relatively long, and the PCIE device has a great influence on server production and client operation and maintenance.

In view of this, the present application provides a PCIE device management method, please refer to fig. 1, which includes:

step S101: when determining that link training of PCIE equipment and an IIO root port is not finished in an IIO initialization stage in a starting process of a BIOS (basic input output System), writing 1 to an auxiliary bus reset value of a bridge control register corresponding to the IIO root port so as to control the IIO root port to trigger hot reset.

The initialization stage of IIO in the BIOS starting process comprises two stages of IIO early initialization and IIO Late initialization. It is specifically at the IIO Late initialization stage that it is determined that the link training of the PCIE device and the IIO root port is not completed. In the IIO early initialization stage, necessary configuration is mainly performed before IIO PCIE root port link training, and link training is started for an IIO root port (root port, abbreviated as RP). In the IIO Late initialization stage, the main tasks are to configure all PCIE interfaces, initialize IIO DMI (Direct Media Interface) and PCIE root ports before other PCIE enumeration drivers discover and allocate resources to PCIE root ports, and at this stage, the BIOS checks link states of all IIO root ports.

The root port refers to a port on which a link directly connected to the root bridge is located, or a port on which a path to the root bridge is shortest.

By writing a 1 to the Secondary Bus Reset (Secondary Bus Reset) value of the Bridge Control Register (Bridge Control Register), the IIO root port can be made to trigger a warm Reset (Hot Reset) to re-train the link.

Step S102: judging whether the state parameters of the link state registers in the PCIE configuration space meet preset conditions or not; the preset conditions are that the link activation value of the data link layer is 1, the current link speed is a preset speed, and the negotiated link bandwidth is a preset bandwidth.

The Status parameters of the Link Status Register (Link Status Register) include a Data Link Layer Link Active value, a Current Link Speed (Current Link Speed), and a Negotiated Link bandwidth (Negotiated Link Width).

The PCIE configuration space is a configuration space of the PCIE device, and the PCIE device corresponds to the IIO root port. The link status register is located in a PCIE configuration space Capability structure.

It should be noted that, in the present application, the preset speed is not limited, and is determined according to the configuration of the PCIE interface. For example, the preset speeds may be GEN1, GEN2, GEN3, GEN4, GEN5, and the like.

Similarly, the preset bandwidth is not limited in the present application, and is determined according to the configuration of the PCIE interface. For example, the preset bandwidth may be X4, X8, X16, etc.

Step S103: and if the state parameter meets the preset condition, controlling the IIO root port and the PCIE equipment to perform link training again so that the IIO root port identifies the PCIE equipment.

Step S104: and if the state parameter does not meet the preset condition, sending out early warning information.

The state parameter does not satisfy the preset condition, that is, at least one of the three parameters, i.e., the data link layer link activation value, the current link speed and the negotiated link bandwidth, satisfies that the data link layer link activation value is not 1, the current link speed is not the preset speed and the negotiated link bandwidth is not the preset bandwidth.

In this embodiment, when discovering that the link training between the PCIE device and the IIO root port is abnormal in the IIO initialization stage in the starting process, the BIOS performs a warm reset on the IIO root port, and then determines a state parameter of a link state register in a PCIE configuration space corresponding to the IIO root port to perform a determination. When the state parameter meets the preset parameter, the IIO root port is successfully reset, so that the IIO root port and the PCIE equipment are subjected to link training again, the PCIE equipment is reconnected, and the PCIE equipment is recovered to be identified; and when the state parameters do not meet the preset parameters, carrying out early warning notification so as to notify production and operation and maintenance to check and recover the identification of the PCIE equipment. Therefore, the problem that PCIE equipment is lost in the BIOS starting process can be avoided, and production line production and client operation and maintenance of a server are facilitated.

On the basis of the foregoing embodiment, in an embodiment of the present application, please refer to fig. 2, another PCIE device management method provided in the present application includes:

step S201: when the BIOS determines that the link training of the PCIE equipment and the IIO root port is not finished in the IIO initialization stage in the starting process, writing 1 to the auxiliary bus reset value of the bridge control register corresponding to the IIO root port to control the IIO root port to trigger the hot reset.

Step S202: judging whether the state parameters of a link state register in a PCIE configuration space meet preset conditions or not; the preset conditions are that the link activation value of the data link layer is 1, the current link speed is a preset speed, and the negotiated link bandwidth is a preset bandwidth.

Step S203: and if the state parameter meets the preset condition, controlling the IIO root port and the PCIE equipment to perform link training again so that the IIO root port identifies the PCIE equipment.

Step S204: and if the state parameter does not meet the preset condition, returning to the step of writing the auxiliary bus reset value of the bridge control register corresponding to the IIO root port into 1.

And when the state parameters do not meet the preset conditions, returning to the step S201.

Step S205: and judging whether the execution times of writing 1 to the auxiliary bus reset value of the bridge control register corresponding to the IIO root port reaches a preset time threshold value.

Wherein the preset time threshold is not less than 2.

And when the state parameter does not meet the preset condition, returning to the step S201, performing one-time writing of 1 to the auxiliary bus reset value of the bridge control register corresponding to the IIO root port to control the IIO root port to trigger hot reset, continuing to enter the step S202, determining whether the state parameter meets the preset condition again, if so, enabling the IIO root port to recover to identify the PCIE device, and if not, returning to the step S201, and repeating the steps. And writing the auxiliary bus reset value of the bridge control register corresponding to the IIO root port into 1 every time of execution, and adding one to the execution times.

The preset number threshold is more than two times, for example, the preset number threshold may be two times, three times, four times, etc.

Step S206: and if the execution times reach the preset time threshold, sending out early warning information.

When the execution times reach a preset time threshold, the preset time threshold indicates that the hot reset of the IIO root port is triggered by the attempts, and the IIO root port and the PCIE equipment perform link training again, but the link training is not successful, and at the moment, early warning is performed so as to inform production and operation and maintenance to check.

It should be noted that, please refer to the above embodiments for step S201, step S202, and step S203, which are not described in detail herein.

In this embodiment, when the IIO root port and the PCIE device are linked, the IIO root port and the PCIE device are triggered multiple times, so that the IIO root port and the PCIE device perform link training again, the identification of the PCIE device is recovered, and the probability of successful automatic linking of the IIO root port and the PCIE device is improved.

On the basis of any one of the above embodiments, in an embodiment of the present application, sending out the warning information includes:

The identification information of the PCIE device includes a bus (bus), a device (device), and a function (function), and the identification information of the PCIE device corresponds to the PCIE device one to one, and the position of the PCIE device can be located through the identification information.

The BIOS sends the identification information to the BMC through an IPMI (Intelligent Platform Management Interface) command, and the identification information is sent in an OEM format agreed with the BMC so that the BMC can analyze the identification information.

In this embodiment, when a PCIE device is lost, the identification information of the PCIE device is sent to a substrate Management Controller (BMC) and stored in a SEL Log (System Event Log), so that a user can find that the PCIE device is lost by checking the BMC Log, process the loss in time, and recover the identification of the PICE device.

Referring to fig. 3, in an embodiment of the present application, a PCIE device management method includes:

step S301: when determining that link training of PCIE equipment and an IIO root port is not finished in an IIO initialization stage in a starting process of a BIOS (basic input output System), writing 1 to an auxiliary bus reset value of a bridge control register corresponding to the IIO root port so as to control the IIO root port to trigger hot reset.

Step S302: judging whether the state parameters of a link state register in a PCIE configuration space meet preset conditions or not; the preset conditions are that the link activation value of the data link layer is 1, the current link speed is a preset speed, and the negotiated link bandwidth is a preset bandwidth.

Step S303: and if the state parameter meets the preset condition, controlling the IIO root port and the PCIE equipment to perform link training again so that the IIO root port identifies the PCIE equipment.

Step S304: and if the state parameter does not meet the preset condition, returning to the step of writing the auxiliary bus reset value of the bridge control register corresponding to the IIO root port into 1.

Step S305: and judging whether the execution times of writing 1 into the auxiliary bus reset value of the bridge control register corresponding to the IIO root port reaches a preset time threshold value or not.

The preset time threshold is not less than 2.

Step S306: and if the execution times reach the preset time threshold, sending the identification information of the PCIE equipment corresponding to the IIO root port to display equipment.

In this embodiment, the identification information of the lost PCIE device is sent to the display device, so as to notify the position of the PCIE device to the personnel, so that the personnel can perform operation and maintenance check in time, and recover the identification of the PCIE device.

Step S307: and sending the identification information of the PCIE equipment corresponding to the IIO root port to a substrate management controller so that the substrate management controller can store the identification information to an SEL log.

It should be noted that, in the present application, the order of sending the identification information of the PCIE device to the display device and sending the identification information of the PCIE device to the substrate management controller is not limited, and may be exchanged with each other.

Please refer to the above embodiments for steps S301, S302, S303, S304, S305, and S307, which will not be described in detail herein.

Referring to fig. 4, in an embodiment of the present application, a PCIE device management method includes:

step S401: and when the BIOS is started to IIO initialization, reading the state parameters of the link state register in the PCIE configuration space corresponding to the IIO root port.

The status parameters of the link status register in this step include the data link layer link activation value, the current link speed, and the negotiated link bandwidth.

It should be noted that the number of the first no root ports in the present application is not limited. The number of the IIO root ports may be one, or two or more.

As an implementation manner, when the number of IIO root ports is two or more, reading the status parameter of the link status register in the PCIE configuration space corresponding to the IIO root port includes:

Step S402: and judging whether the current link speed and the negotiated link bandwidth in the state parameters are 0 or not.

Step S403: and if the current link speed and the negotiated link bandwidth are not 0, judging whether the link activation value of the data link layer is 0.

It should be noted that, if the current link speed and the negotiated link bandwidth are both 0, it indicates that the IIO root port is not connected to the PCIE device. At this time, if the number of the IIO root ports is two or more, polling of the next IIO root port is continued until all the IIO root ports are polled.

Step S404: and if the data link layer link activation value is 0, determining that the link training of the PCIE equipment and the IIO root port is not finished.

It should be noted that, if the link activation value of the data link layer is not 0, it indicates that the IIO root port and the PCIE device link training are completed. At this time, if the number of the IIO root ports is two or more, the next IIO root port is continuously polled until all IIO root ports are polled.

Step S405: and writing 1 to the reset value of the auxiliary bus of the bridge control register corresponding to the IIO root port so as to control the IIO root port to trigger hot reset.

Step S406: judging whether the state parameters of a link state register in a PCIE configuration space meet preset conditions or not; the preset conditions are that the link activation value of the data link layer is 1, the current link speed is a preset speed, and the negotiated link bandwidth is a preset bandwidth.

Step S407: and if the state parameter meets the preset condition, controlling the IIO root port and the PCIE equipment to perform link training again so that the IIO root port identifies the PCIE equipment.

Step S408: and if the state parameter does not meet the preset condition, returning to the step of writing the auxiliary bus reset value of the bridge control register corresponding to the IIO root port into 1.

Step S409: and judging whether the execution times of writing 1 into the auxiliary bus reset value of the bridge control register corresponding to the IIO root port reaches a preset time threshold value or not.

Wherein the preset time threshold is not less than 2.

Step S410: and if the execution times reach the preset time threshold, sending the identification information of the PCIE equipment corresponding to the IIO root port to display equipment.

Step S411: and sending the identification information of the PCIE equipment corresponding to the IIO root port to a substrate management controller so that the substrate management controller can store the identification information to an SEL log.

It should be noted that, please refer to the above embodiments for steps S405, S406, S407, S408, S409, S410, and S411, which are not repeated herein.

In the method for managing PCIE devices in this embodiment, at the IIO initialization stage in the BIOS startup process, whether PCIE devices are lost is detected, and when a loss occurs, the PCIE devices are further recovered. Namely, the loss of the PCIE equipment is detected and the recovery is carried out at the IIO initialization stage in the BIOS starting process.

In the prior art, when a loss of a PCIE device is found after starting a system, no early warning is given in time in the BIOS starting process or a condition that the PCIE device is lost is reported to a BMC. For timely warning of a PCIE device loss condition, on the basis of the foregoing embodiment, in an embodiment of the present application, after determining that link training between the PCIE device and the IIO root port is not completed, the method further includes:

and sending out early warning information.

The sending out the early warning information in the embodiment comprises:

sending the identification information of the PCIE equipment corresponding to the IIO root port to display equipment; and/or the presence of a gas in the atmosphere,

In this embodiment, when it is detected that the PCIE device is lost, the identification information of the PCIE device may be sent to the display device to notify a person that the PCIE device is lost, or the identification information of the PCIE device may be sent to the BMC, and the identification information of the PCIE device is stored in the SEL log, so that a user queries the SEL log to know that the PCIE device is lost.

In the following, a PCIE device management apparatus provided in the embodiment of the present application is introduced, and a PCIE device management apparatus described below and a PCIE device management method described above may be referred to correspondingly.

Fig. 5 is a block diagram of a structure of a PCIE device management apparatus provided in the embodiment of the present application, and referring to fig. 5, the PCIE device management apparatus may include:

the trigger module 100 is configured to, when determining that link training of a PCIE device and an IIO root port is not completed in an IIO initialization stage in a start process of a BIOS, write 1 to a reset value of an auxiliary bus of a bridge control register corresponding to the IIO root port to control the IIO root port to trigger a warm reset;

a first determining module 200, configured to determine whether a state parameter of a link status register in a PCIE configuration space meets a preset condition; the preset conditions are that the link activation value of a data link layer is 1, the current link speed is a preset speed, and the negotiated link bandwidth is a preset bandwidth;

a control identification module 300, configured to control the IIO root port and the PCIE device to perform link training again if the state parameter meets the preset condition, so that the IIO root port identifies the PCIE device;

the first early warning module 400 is configured to send out early warning information if the state parameter does not satisfy the preset condition.

The PCIE device management apparatus of this embodiment is configured to implement the foregoing PCIE device management method, and therefore specific embodiments in the PCIE device management apparatus may be found in the foregoing embodiment portions of the PCIE device management method, for example, the triggering module 100, the first determining module 200, the control identifying module 300, and the early warning module 400, which are respectively used to implement step S101, step S102, step S103, and step S104 in the PCIE device management method, so that the specific embodiments may refer to descriptions of corresponding embodiments of each portion, and are not described herein again.

In the PCIE device management apparatus in this embodiment, when finding that the link training between the PCIE device and the IIO root port is abnormal in the IIO initialization stage in the start process of the BIOS, the PCIE device management apparatus resets the IIO root port again, and then determines the state parameter of the link state register in the PCIE configuration space corresponding to the IIO root port to determine. When the state parameter meets the preset parameter, the IIO root port is successfully reset, so that the IIO root port and the PCIE equipment are subjected to link training again, the PCIE equipment is reconnected, and the identification of the PCIE equipment is recovered; and when the state parameters do not meet the preset parameters, carrying out early warning notification so as to notify production and operation and maintenance to check and recover the identification of the PCIE equipment. Therefore, the problem that PCIE equipment is lost in the BIOS starting process can be avoided, and production of a server production line and operation and maintenance of a client are facilitated.

Optionally, the early warning module 400 includes:

a returning unit, configured to return to the step of writing the auxiliary bus reset value of the bridge control register corresponding to the IIO root port to 1 if the state parameter does not meet the preset condition;

the judging unit is used for judging whether the execution times of writing 1 into the auxiliary bus reset value of the bridge control register corresponding to the IIO root port reaches a preset time threshold value or not; the preset time threshold value is not less than 2;

and the early warning unit is used for sending out early warning information if the execution times reaches the preset time threshold.

Optionally, the early warning module 400 is specifically configured to send the identification information of the PCIE device corresponding to the IIO root port to the baseboard management controller, so that the baseboard management controller stores the identification information to the SEL log.

Optionally, the early warning module 400 is specifically configured to send the identification information of the PCIE device corresponding to the IIO root port to the display device.

Optionally, the PCIE device management apparatus further includes:

a reading module, configured to read the state parameter of the link state register in the PCIE configuration space corresponding to the IIO root port when the BIOS is started to IIO initialization;

a second determining module, configured to determine whether the current link speed and the negotiated link bandwidth in the status parameter are 0;

a third judging module, configured to judge whether the data link layer link activation value is 0 if both the current link speed and the negotiated link bandwidth are not 0;

a determining module, configured to determine that link training of the PCIE device and the IIO root port is not completed if the data link layer link activation value is 0.

Optionally, the PCIE device management apparatus further includes:

and the second early warning module is used for sending out early warning information.

Optionally, the reading module is specifically configured to poll and read the state parameter of the link state register in the PCIE configuration space corresponding to the IIO root port.

In the following, description is made on the PCIE device management device provided in the embodiment of the present application, and the PCIE device management device described below and the PCIE device management method described above may be referred to correspondingly.

Fig. 6 is a block diagram of a structure of a PCIE device management device provided in the embodiment of the present application, including:

a memory 11 for storing a computer program;

the processor 12 is configured to implement the steps of the PCIE device management method according to any embodiment described above when executing the computer program.

In the PCIE device management apparatus in this embodiment, when finding that the link training between the PCIE device and the IIO root port is abnormal in the IIO initialization stage in the start process of the BIOS, the PCIE device management apparatus resets the IIO root port again, and then determines the state parameter of the link state register in the PCIE configuration space corresponding to the IIO root port to determine. When the state parameter meets the preset parameter, the IIO root port is successfully reset, so that the IIO root port and the PCIE equipment are subjected to link training again, the PCIE equipment is reconnected, and the PCIE equipment is recovered to be identified; and when the state parameters do not meet the preset parameters, carrying out early warning notification so as to notify production and operation and maintenance to check and recover the identification of the PCIE equipment. Therefore, the problem that PCIE equipment is lost in the BIOS starting process can be avoided, and production line production and client operation and maintenance of a server are facilitated.

In the following, a computer-readable storage medium provided in an embodiment of the present application is introduced, and the computer-readable storage medium described below and the PCIE device management method described above may be referred to correspondingly.

A computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the PCIE device management method according to any one of the above embodiments are implemented.

In the computer-readable storage medium in this embodiment, when finding that the link training between the PCIE device and the IIO root port is abnormal in the IIO initialization stage in the startup process of the BIOS, the IIO root port is reset, and then the state parameter of the link state register in the PCIE configuration space corresponding to the IIO root port is determined to be determined. When the state parameter meets the preset parameter, the IIO root port is successfully reset, so that the IIO root port and the PCIE equipment are subjected to link training again, the PCIE equipment is reconnected, and the identification of the PCIE equipment is recovered; and when the state parameters do not meet the preset parameters, carrying out early warning notification so as to notify production and operation and maintenance to check and recover the identification of the PCIE equipment. Therefore, the problem that PCIE equipment is lost in the BIOS starting process can be avoided, and production line production and client operation and maintenance of a server are facilitated.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The PCIE device management method, apparatus, device, and computer-readable storage medium provided in the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, without departing from the principle of the present application, the present application can also make several improvements and modifications, and those improvements and modifications also fall into the protection scope of the claims of the present application.

Claims

1. A PCIE device management method is characterized by comprising the following steps:

when the BIOS determines that the link training of the PCIE equipment and the IIO root port is not finished in the IIO initialization stage in the starting process, writing 1 to an auxiliary bus reset value of a bridge control register corresponding to the IIO root port so as to control the IIO root port to trigger hot reset;

2. The PCIE device management method of claim 1, wherein, if the state parameter does not satisfy the preset condition, sending early warning information comprises:

judging whether the execution times of writing 1 to the auxiliary bus reset value of the bridge control register corresponding to the IIO root port reaches a preset time threshold value or not; the preset time threshold value is not less than 2;

3. The PCIE device management method of claim 1, wherein sending the warning information comprises:

4. The PCIE device management method of claim 1, wherein sending the warning information comprises:

5. The PCIE device management method according to any one of claims 1 to 4, wherein when the BIOS determines that link training of the PCIE device and the IIO root port is not completed in the IIO initialization stage in the start process, writing an auxiliary bus reset value of a bridge control register corresponding to the IIO root port to 1 to control the IIO root port to trigger a warm reset, further comprising:

6. The PCIE device management method of claim 5, wherein after determining that the link training of the PCIE device and the IIO root port is not completed, further comprising:

and sending out early warning information.

7. The PCIE device management method of claim 5, wherein reading the state parameter of the link status register in the PCIE configuration space corresponding to the IIO root port comprises:

8. A PCIE device management apparatus is characterized by comprising:

the control identification module is used for controlling the IIO root port and the PCIE equipment to perform link training again if the state parameter meets the preset condition so that the IIO root port identifies the PCIE equipment;

and the first early warning module is used for sending out early warning information if the state parameters do not meet the preset conditions.

9. A PCIE device management apparatus, comprising:

a memory for storing a computer program;

a processor configured to implement the steps of the PCIE device management method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when executed by a processor, the computer program implements the steps of the PCIE device management method as recited in any one of claims 1 to 7.