CN115642896A - Mass spectrum signal filtering method and device, computer equipment and storage medium - Google Patents
Mass spectrum signal filtering method and device, computer equipment and storage medium Download PDFInfo
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Abstract
The application relates to a method, an apparatus, a computer device and a storage medium for filtering mass spectrum signals. The method comprises the steps of obtaining a digital signal to be processed corresponding to a mass spectrometer through an FPGA chip, determining a normal signal and an overflow signal from the digital signal to be processed according to a preset voltage value classification rule, determining a signal base line corresponding to the digital signal to be processed based on the normal signal and the overflow signal, adjusting the value of the normal signal and the value of the overflow signal according to the signal base line to obtain an adjusted digital signal, enabling the normal signal and the overflow signal to be distributed more uniformly, and filtering noise of the adjusted digital signal through a filter module to obtain the filtered digital signal. Compared with the traditional filtering mode through software, the scheme has the advantages that the filter is formed inside the FPGA chip, and the baseline is adjusted based on the numerical value of the digital signal, so that the signal waveform is smoother, and the processing efficiency of filtering the mass spectrum signal is improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for filtering mass spectrum signals, a computer device, and a storage medium.
Background
In scientific operation process, need use the mass spectrograph to carry out data acquisition, the mass spectrograph carries out data acquisition and needs rely on ADC (Analog-to-digital converter) to go on, when carrying out data acquisition, can receive the interference of noise, and because factors such as device precision, hardware design maturity, equipment precision, artifical installation, the interference of noise is strong and weak differs, can produce great influence to effective signal. Therefore, suppression of noise during signal acquisition is required. At present, the noise suppression mode is usually a mode of processing a filter by using software, however, the filtering mode by using software occupies a large amount of resources of a processor, resulting in a reduction of the overall performance of the system.
Therefore, the existing mass spectrum signal filtering method has the defect of low processing efficiency.
Disclosure of Invention
In view of the above, it is necessary to provide a method, an apparatus, a computer device and a storage medium for filtering a mass spectrum signal, which can improve processing efficiency.
A mass spectrum signal filtering method is applied to an FPGA chip, and comprises the following steps:
acquiring a digital signal to be processed corresponding to a mass spectrometer;
determining a normal signal and an overflow signal in the digital signal to be processed according to a preset voltage value classification rule, and determining a signal baseline corresponding to the digital signal to be processed according to the normal signal and the overflow signal;
according to the signal baseline, adjusting the value of the normal signal and the value of the overflow signal so as to enable the normal signal and the overflow signal to be distributed more uniformly, and obtaining an adjusted digital signal;
and inputting the adjusted digital signal into a filter module, and filtering noise in the adjusted digital signal through the filter module to obtain a filtered digital signal.
In one embodiment, the determining a normal signal and an overflow signal in the digital signal to be processed according to a preset voltage value classification rule includes:
acquiring a preset digital signal lower limit, a preset zero voltage value and a preset digital signal upper limit; the lower limit of the preset digital signal is smaller than the preset zero voltage value, and the preset zero voltage value is smaller than the upper limit of the preset digital signal;
for each digital signal to be processed, comparing the numerical value of the digital signal with the preset digital signal lower limit, the preset zero voltage numerical value and the preset digital signal upper limit respectively;
if the numerical value of the digital signal is greater than or equal to the zero voltage numerical value and less than the preset digital signal upper limit, determining the digital signal as a normal signal;
and if the numerical value of the digital signal is greater than or equal to the preset digital signal lower limit and less than the preset zero pressure numerical value, determining the digital signal as an overflow signal.
In one embodiment, after determining the normal signal and the overflow signal in the digital signal to be processed, and before determining the signal baseline corresponding to the digital signal to be processed according to the normal signal and the overflow signal, the method further includes:
and replacing the numerical value of the overflow signal with the preset digital signal upper limit to obtain the adjusted overflow signal.
In one embodiment, the determining a signal baseline corresponding to the digital signal to be processed according to the normal signal and the overflow signal includes:
acquiring the minimum value of the digital signal values of the normal signal and the adjusted overflow signal, and taking the minimum value as a signal baseline corresponding to the digital signal to be processed;
the adjusting the value of the normal signal and the value of the overflow signal according to the signal baseline to make the normal signal and the overflow signal distributed uniformly to obtain an adjusted digital signal includes:
and for each digital signal comprising the normal signal and/or the adjusted overflow signal, subtracting the minimum value from the value of the digital signal to obtain the adjusted digital signal.
In one embodiment, the method further comprises:
acquiring a low-pass filter to be trained and a plurality of sample digital signals; the plurality of sample digital signals comprise mass spectrum signals and noise signals;
determining a mass spectral signal and a noise signal in the plurality of sample digital signals;
determining the pass band edge frequency, the stop band edge frequency and the filter coefficient of the low-pass filter to be trained according to the frequency range of the mass spectrum signal;
and obtaining the filter module according to the passband edge frequency, the stopband edge frequency and the filter coefficient.
In one embodiment, the inputting the adjusted digital signal into a filter module, and filtering noise in the adjusted digital signal by the filter module to obtain a filtered digital signal includes:
inputting the adjusted digital signal into a filter module;
and filtering, by the filter module, noise in the adjusted digital signal based on the passband edge frequency, the stopband edge frequency, and the filter coefficient to obtain a filtered digital signal.
In one embodiment, after obtaining the filtered digital signal, the method further includes:
converting the filtered digital signal into a digital signal with a preset transmission format;
and transmitting the digital signal with the preset transmission format to an upper computer so that the upper computer displays a corresponding mass spectrogram according to the ion intensity of the digital signal.
A mass spectrum signal filtering device is applied to an FPGA chip, and the device comprises:
the acquisition module is used for acquiring a digital signal to be processed corresponding to the mass spectrometer;
the determining module is used for determining a normal signal and an overflow signal in the digital signal to be processed according to a preset voltage value classification rule, and determining a signal base line corresponding to the digital signal to be processed according to the normal signal and the overflow signal;
the adjusting module is used for adjusting the value of the normal signal and the value of the overflow signal according to the signal baseline so as to enable the normal signal and the overflow signal to be distributed more uniformly and obtain an adjusted digital signal;
and the filtering module is used for inputting the adjusted digital signal into the filter module, and filtering noise in the adjusted digital signal through the filter module to obtain a filtered digital signal.
A computer device comprising a memory storing a computer program and a processor implementing the steps of the method described above when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method.
According to the mass spectrum signal filtering method, the mass spectrum signal filtering device, the computer equipment and the storage medium, the digital signal to be processed corresponding to the mass spectrometer is obtained through the FPGA chip, the normal signal and the overflow signal are determined from the digital signal to be processed according to the preset voltage value classification rule, the signal base line corresponding to the digital signal to be processed is determined based on the normal signal and the overflow signal, the value of the normal signal and the value of the overflow signal are adjusted according to the signal base line, the adjusted digital signal is obtained, the normal signal and the overflow signal are distributed more uniformly, and noise is filtered by the adjusted digital signal through the filter module, so that the filtered digital signal is obtained. Compared with the traditional filtering mode through software, the scheme has the advantages that the filter is formed inside the FPGA chip, and the baseline is adjusted based on the numerical value of the digital signal, so that the signal waveform is smoother, and the processing efficiency of filtering the mass spectrum signal is improved.
Drawings
FIG. 1 is a diagram of an exemplary embodiment of a method for filtering a mass spectrum signal;
FIG. 2 is a schematic flow chart of a method for filtering a mass spectrum signal according to one embodiment;
FIG. 3 is a schematic flow chart of a method for filtering a mass spectral signal according to another embodiment;
FIG. 4 is a schematic flow chart of a method of filtering a mass spectral signal in yet another embodiment;
FIG. 5 is a block diagram of a mass spectral signal filtering apparatus according to an embodiment;
FIG. 6 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The mass spectrum signal filtering method provided by the application can be applied to the application environment shown in fig. 1. The FPGA chip 102 communicates with the upper computer 104 through a network. The FPGA chip 102 can acquire digital signals to be processed corresponding to a mass spectrometer by using an acquisition module arranged in the FPGA chip 102, normal signals and overflow signals are determined from the digital signals, a signal baseline is determined based on the normal signals and the overflow signals, the numerical values of the normal signals and the numerical values of the overflow signals are adjusted based on the signal baseline, the signals are uniformly distributed, the adjusted digital signals are input into a filter module, noise is filtered by the filter module, in addition, the FPGA chip 102 can also send the filtered digital signals to an upper computer 104, and the upper computer 104 can display waveforms through a display device when receiving the filtered digital signals sent by the FPGA chip 102. The upper computer 104 may be, but is not limited to, various personal computers, notebook computers, smart phones, and tablet computers.
In one embodiment, as shown in fig. 2, a method for filtering a mass spectrum signal is provided, which is described by taking the method as an example for being applied to the terminal in fig. 1, and includes the following steps:
step S202, acquiring a digital signal to be processed corresponding to the mass spectrometer.
Among them, the mass spectrometer is also called a mass spectrometer. Apparatus for separating and detecting different isotopes. That is, based on the principle that charged particles can deflect in an electromagnetic field, the instrument separates and detects the composition of substances according to the mass difference of substance atoms, molecules or molecular fragments. The mass spectrometer may be the subject for which signal acquisition by the FPGA chip 102 is required. The FPGA chip 102 can acquire digital signals to be processed corresponding to the mass spectrometer. The signal generated by the mass spectrometer may be an analog signal, and the FPGA chip 102 may perform signal type conversion through corresponding modules arranged in the FPGA chip 102, so as to obtain a digital signal to be acquired. For example, the FPGA chip 102 may acquire an analog signal generated by the mass spectrometer through an ADC signal acquisition module arranged therein, and perform analog-to-digital conversion on the acquired analog signal to obtain a digital signal corresponding to the mass spectrometer. The ADC signal acquisition module can acquire signals of the mass spectrometer according to a set digit and a set sampling rate, for example, the ADC signal acquisition module can continuously acquire 16bit data according to a sampling rate of 250kHz by using an ADC chip, and can also acquire positive and negative voltage values and set a zero voltage value; after the ADC signal acquisition module acquires analog signal data of the mass spectrometer, analog-to-digital conversion may be performed on the analog signal data to obtain the digital signal to be processed.
Step S204, determining a normal signal and an overflow signal in the digital signal to be processed according to a preset voltage value classification rule, and determining a signal baseline corresponding to the digital signal to be processed according to the normal signal and the overflow signal.
The preset voltage value classification rule may be determined based on the value of the digital signal, and may be used as a standard for classifying the digital signal, for example, classifying digital signals in a certain value range into one class, classifying digital signals in another value range into one class, and the like. The result obtained by classifying the digital signals may include a normal signal and an overflow signal, that is, the FPGA chip 102 may determine the normal signal and the overflow signal in the digital signals to be processed based on the preset voltage value rule. The normal signal may be a signal whose voltage value of the digital signal is within a set range, and the overflow signal may be a signal whose intensity is over, for example, a signal whose voltage value of the digital signal is outside the set range. For example, the FPGA chip 102 can localize data that is over-range to overflow data, whereas since the data collected by the mass spectrometer does not include a negative voltage, the FPGA chip 102 can localize data in a negative voltage region to overflow signals.
After the normal signal and the overflow signal are determined, the FPGA chip 102 may further determine a signal baseline corresponding to the digital signal to be processed based on the normal signal and the overflow signal. For example, after replacing the overflow signal with a value in the range of the normal signal, the FPGA chip 102 may obtain a minimum value of the values in the normal signal and the overflow signal after the replacement adjustment, so that the FPGA chip 102 may use the minimum value as a signal baseline. The above replacement may be to treat the value of the overflow signal as a full scale of data, so that the overflow signal can be determined at the final image display end.
Step S206, the value of the normal signal and the value of the overflow signal are adjusted according to the signal baseline, so that the normal signal and the overflow signal are distributed more uniformly, and the adjusted digital signal is obtained.
The signal baseline may be a baseline determined based on the normal signal and the overflow signal, and the FPGA chip 102 may perform baseline-based processing on the digital signals after determining the baseline. For example, the FPGA chip 102 may adjust the values of the normal signal and the overflow signal based on the signal baseline, so that the normal signal and the overflow signal are distributed more uniformly during displaying, and an adjusted digital signal is obtained. The above-mentioned mode of adjusting the value based on the signal baseline can be that after the overflow signal is replaced by the value in the range of the normal signal, the normal value and the overflow value after the replacement adjustment are subtracted from the value of the signal baseline, so that the baseline can be reduced to be near 0, the baseline with a large value is close to 0, the relative ratio of noise and effective signal is improved, the ratio of noise to actual signal is more prominent, the algorithm effect of the later-stage filter is more obvious, and the digital signals of various types are more uniformly distributed.
Step S208, inputting the adjusted digital signal into a filter module, and filtering noise in the adjusted digital signal by the filter module to obtain a filtered digital signal.
The adjusted digital signal may be a digital signal obtained by performing numerical adjustment based on the signal baseline, and the adjusted digital signal has a more prominent effect on a ratio of noise to an actual signal. The FPGA chip 102 may input the adjusted digital signal into a filter module, and filter noise in the adjusted digital signal through the filter module, so as to obtain a filtered digital signal. For example, the FPGA chip 102 may input the adjusted digital signal into a filter module disposed in the FPGA chip 102, and the FPGA chip 102 filters noise in the adjusted digital signal by using a pass band, a stop band, and a preset coefficient in the filter module. The filter module may be a low-pass filter, and the filter module may be obtained by training based on a plurality of sample digital signals, specifically, the FPGA chip 102 may perform simulation design by MATLAB, train based on a plurality of sample digital signals, and program the obtained corresponding low-pass filter into the FPGA chip 102 to form a digital low-pass filter inside the FPGA chip 102.
In addition, after the FPGA chip 102 filters the noise of the adjusted digital signal, the filtered digital signal may be displayed. For example, in one embodiment, after obtaining the filtered digital signal, the method further includes: converting the filtered digital signal into a digital signal with a preset transmission format; and transmitting the digital signals with the preset transmission format to an upper computer so that the upper computer displays a corresponding mass spectrogram according to the ion intensity of the digital signals. In this embodiment, since the FPGA chip 102 needs to send the filtered digital signal to the upper computer 104 for display, the FPGA chip 102 needs to convert the format of the filtered digital signal into a format capable of being transmitted, that is, the FPGA chip 102 can convert the filtered digital signal into a digital signal of a preset transmission format, the FPGA chip 102 can upload the digital signal of the preset transmission format to the display end according to a specified protocol and the format, for example, the FPGA chip 102 can transmit the digital signal of the preset transmission format to the upper computer 104 according to a preset network transmission protocol, so that the upper computer 104 can display a corresponding mass spectrum according to the ion intensity of the filtered digital signal. In addition, the upper computer 104 can also judge whether the displayed spectrogram is correct or not. The transmission interface for uploading the digital signal, the transmission protocol and the display mode of the image can be set according to actual conditions.
According to the method for filtering the mass spectrum signals, the digital signals to be processed corresponding to the mass spectrometer are obtained through the FPGA chip, the normal signals and the overflow signals are determined from the digital signals to be processed according to the preset voltage value classification rule, the signal base lines corresponding to the digital signals to be processed are determined based on the normal signals and the overflow signals, the values of the normal signals and the overflow signals are adjusted according to the signal base lines, the adjusted digital signals are obtained, the normal signals and the overflow signals are enabled to be distributed more uniformly, and the adjusted digital signals are filtered through the filter module to remove noise, so that the filtered digital signals are obtained. Compared with the traditional filtering mode through software, the scheme has the advantages that the filter is formed inside the FPGA chip, and the baseline is adjusted based on the numerical value of the digital signal, so that the signal waveform is smoother, and the processing efficiency of filtering the mass spectrum signal is improved.
In one embodiment, the determining the normal signal and the overflow signal in the digital signal to be processed according to the preset voltage value classification rule comprises: acquiring a preset digital signal lower limit, a preset zero voltage value and a preset digital signal upper limit; the lower limit of the preset digital signal is smaller than a preset zero voltage value, and the preset zero voltage value is smaller than the upper limit of the preset digital signal; aiming at each digital signal to be processed, comparing the numerical value of the digital signal with a preset digital signal lower limit, a preset zero voltage numerical value and a preset digital signal upper limit respectively; if the numerical value of the digital signal is greater than or equal to the zero pressure numerical value and less than the upper limit of the preset digital signal, determining the digital signal as a normal signal; and if the numerical value of the digital signal is greater than or equal to the lower limit of the preset digital signal and less than the preset zero voltage numerical value, determining the digital signal as an overflow signal.
In this embodiment, the preset voltage value classification rule may be formulated based on the voltage value of the digital signal. In the process of classifying the digital signal to be processed by the FPGA chip 102, the FPGA chip 102 may obtain a preset digital lower limit, a preset zero voltage value, and a preset digital signal upper limit. The lower limit of the preset digital signal is smaller than the preset zero voltage value, and the preset zero voltage value is smaller than the upper limit of the preset digital signal. The preset digital lower limit, the preset zero voltage value and the preset digital signal upper limit may be three thresholds in a preset voltage value classification rule. The FPGA chip 102 may perform detection and determination based on the threshold values for each of the digital signals to be processed. For example, the FPGA chip 102 may compare a numerical value of each digital signal to be processed with the preset lower digital signal limit, the preset zero-voltage numerical value, and the preset upper digital signal limit, and if the FPGA chip 102 detects that the comparison result is that the numerical value of the digital signal is greater than or equal to the zero-voltage numerical value and less than the preset upper digital signal limit, the FPGA chip 102 may determine that the digital signal is a normal signal; if the FPGA chip 102 detects that the comparison result is that the digital signal is greater than or equal to the preset digital signal lower limit and less than the preset zero voltage value, the FPGA chip 102 may determine that the digital signal is an overflow signal. The preset digital lower limit, the preset zero voltage value and the preset digital signal upper limit may be one voltage value, and the FPGA chip 102 may use different voltage values as the threshold values. For example, the FPGA chip 102 may have values 0 to 32767 for negative voltage values, 32768 to 65535 for positive voltage values, and 32768 for zero voltage values; the FPGA chip 102 may determine the digital signal with the value of the digital signal between 32768 and 65535 as a normal signal, and determine the data with the value of the digital signal between 0 and 32767 as data with an overflow intensity, and enter an overflow data area as an overflow signal. Specifically, the FPGA chip 102 may be provided with a signal preprocessing module, and the signal preprocessing module may include a data overflow determining module, an overflow data processing module, and a signal baseline calibrating module; the FPGA chip 102 may determine the data exceeding the measurement range as overflow data through the data overflow determining module, and there is no negative voltage in the mass spectrometer collected signal by the FPGA chip 102, so the FPGA chip 102 may determine the data within the negative voltage value range as the overflow signal.
In addition, after determining the normal signal and the overflow signal in the digital signals, the FPGA chip 102 may further perform corresponding adjustment on the overflow signal to meet the subsequent processing requirement on the digital signals. For example, in one embodiment, after determining the normal signal and the overflow signal in the digital signal to be processed, before determining the signal baseline corresponding to the digital signal to be processed according to the normal signal and the overflow signal, the method further includes: and replacing the numerical value of the overflow signal with a preset digital signal upper limit to obtain an adjusted overflow signal. In this embodiment, after the FPGA chip 102 determines the normal signal and the overflow signal in the digital signal through the threshold detection, because the negative voltage value does not meet the requirement of signal processing, the FPGA chip 102 may perform corresponding processing on the digital signal belonging to the overflow signal, for example, the FPGA chip 102 may replace the numerical value of the overflow signal with the preset upper limit of the digital signal, so as to obtain the adjusted overflow signal. The preset upper limit of the digital signal may be a full range of the voltage values. For example, if the digital signal with the numerical value of 32768-65535 is determined as a normal signal by the FPGA chip 102, 65535 is the full scale of the normal signal, the numerical value of the overflow signal may be replaced by a maximum value of 65535 by the FPGA chip 102, and the overflow signal is processed as the full scale, which signals are the overflow signal may be determined when the final image is displayed.
Through the above embodiment, the FPGA chip 102 can determine the normal signal and the overflow signal in the digital signal through a plurality of preset thresholds, and perform corresponding normalization processing on the overflow signal, so that the FPGA chip 102 can screen and process the error data in the digital signal, thereby improving the filtering processing efficiency.
In one embodiment, determining a signal baseline corresponding to a digital signal to be processed according to a normal signal and an overflow signal includes: and acquiring the minimum value of the digital signals of the normal signal and the adjusted overflow signal as a signal baseline corresponding to the digital signal to be processed.
In this embodiment, the FPGA chip 102 may screen out a normal signal and an overflow signal in the digital signals according to a plurality of preset voltage value thresholds, and the FPGA chip 102 may further perform corresponding normalization processing on the overflow signal, for example, replace a value of the overflow signal with a maximum value in a value range of the normal signal, and use the maximum value as the adjusted overflow signal. After determining the normal signal and the overflow signal, the FPGA chip 102 may determine the signal baseline of the digital signal based on the normal signal and the adjusted overflow signal. The signal base line may be a straight line formed by a value closest to a minimum value in the digital signal in the display image of the digital signal. For example, the FPGA chip 102 may use a minimum value of the values in the normal signal and the adjusted overflow signal as a signal baseline corresponding to the to-be-processed digital signal.
In addition, in one embodiment, adjusting the value of the normal signal and the value of the overflow signal according to the signal baseline to make the normal signal and the overflow signal evenly distributed to obtain an adjusted digital signal includes: and for each digital signal comprising the normal signal and/or the adjusted overflow signal, subtracting the minimum value from the value of the digital signal to obtain an adjusted digital signal. In this embodiment, after the FPGA chip 102 determines the signal baseline, other digital signals may be processed based on the signal baseline. For example, the FPGA chip 102 may subtract the value of the signal baseline from the value of each of the digital signals to obtain an adjusted digital signal, where the digital signal may include at least one of a normal signal and an adjusted overflow signal, and the signal baseline may be a minimum value of the values in the normal signal and the adjusted overflow signal. Specifically, when the preset zero pressure value is used as a reference, since the preset zero pressure value is at 32768, the reference line is too high and too strong, the relative ratio of noise and effective signals is very small, and errors can be caused no matter a filter algorithm is used or actual image display is performed, therefore, the FPGA chip 102 can collect and judge the lowest signal value in noise in real time, for example, the minimum value in the digital signals, and use this data as an analog 0 pressure value in a noise stage, and the FPGA chip 102 can subtract this value from each digital signal collected in real time, so that the baseline with a large value is reduced to be close to 0, and baseline calibration reduction is realized.
Through the embodiment, the FPGA chip 102 can determine the signal baseline based on the minimum value in the digital signal values, and can adjust the digital signal values based on the signal baseline, so that the baseline of a large value is reduced to be close to 0, the ratio of noise to an actual signal is more prominent, the algorithm effect of a later-stage filter is more remarkable, and the filtering processing efficiency is further improved.
In one embodiment, further comprising: acquiring a low-pass filter to be trained and a plurality of sample digital signals; the plurality of sample digital signals comprise mass spectrum signals and noise signals; determining a mass spectrum signal and a noise signal in the plurality of sample digital signals; determining the passband edge frequency, the stopband edge frequency and the filter coefficient of the low-pass filter to be trained according to the frequency range of the mass spectrum signal; and obtaining a filter module according to the passband edge frequency, the stopband edge frequency and the filter coefficient.
In this embodiment, the FPGA chip 102 may pre-train the filter module, so as to implement filtering processing on the digital signal by using the trained filter module. In training, the FPGA chip 102 may obtain a plurality of sample digital signals and filters that need to be trained. The plurality of sample digital signals may include a mass spectrum signal and a noise signal, and the filter to be trained may be a low-pass filter. After the FPGA chip 102 acquires the sample digital signals, mass spectrum signals and noise signals in the plurality of sample digital signals may be determined. For example, the FPGA chip 102 may display a plurality of real signals, and distinguish a mass spectrum signal and a noise signal in a frequency domain through a fourier algorithm, where the frequency domain of normal data is in a range of 0-0.5kHz, and most of noise is outside the range of 0.5kHz, so as to distinguish the mass spectrum signal from the noise signal. After the FPGA chip 102 determines the mass spectrum signal and the noise signal, the low-pass band edge frequency, the stop band edge frequency, and the filter coefficient that need to be trained can be determined by using the frequency range of the mass spectrum signal. For example, after the FPGA chip 102 distinguishes the mass spectrum signal and the noise in the frequency domain by using the fourier algorithm, the MATLAB is used to design the low-pass filter, so that the passband is close to the edge frequency of the mass spectrum signal, and the stopband suppresses the noise intensity, so that the FPGA chip 102 can obtain the filter module in the FPGA chip 102 according to the passband edge frequency, the stopband edge frequency, and the filter coefficient. Specifically, the FPGA chip 102 may design a multi-order low-pass filter, for example, a 100-order low-pass filter, according to the resource occupancy rate and the out-of-band rejection ratio, and design a digital low-pass filter module in the FPGA according to a coefficient thereof, where a sampling frequency is a sampling frequency of the ADC signal acquisition module, for example, 250kHz, and a transmission frequency is a system clock frequency of the FPGA, for example, 100MHz. The MATLAB can be used in the fields of data analysis, wireless communication, deep learning, image processing, computer vision, signal processing and the like. After the FPGA chip 102 is simulated by MATLAB, the filter coefficient can be extracted, and the design is programmed into the FPGA engineering to form a digital low-pass filter module inside the FPGA.
Through the above embodiment, the FPGA chip 102 may obtain the low pass filter module designed in the FPGA chip 102 by training the plurality of sample digital signals, so that the FPGA chip 102 may perform filtering processing on the digital signals by using the low pass filter module, thereby improving the efficiency of the filtering processing.
In one embodiment, inputting the adjusted digital signal into a filter module, and filtering noise in the adjusted digital signal by the filter module to obtain a filtered digital signal, includes: inputting the adjusted digital signal into a filter module; and filtering the noise in the adjusted digital signal by a filter module based on the passband edge frequency, the stopband edge frequency and the filter coefficient to obtain the filtered digital signal.
In this embodiment, the FPGA chip 102 may perform filtering processing on each digital signal by using the filter module obtained by the training. For example, the FPGA chip 102 inputs the adjusted digital signal into a filter module disposed in the FPGA chip 102, where the filter module may be a multi-order low-pass filter, and the FPGA chip 102 may invoke the low-pass filter to eliminate noise in the adjusted digital signal based on a pass-band edge frequency, a stop-band edge frequency, and a filter coefficient therein, so as to obtain a filtered digital signal. The adjusted digital signal may be a digital signal obtained by distinguishing a normal signal from an overflow signal, processing the overflow signal, and performing baseline calibration.
Through the embodiment, the FPGA chip 102 can perform filtering processing on the digital signal by using the filter module arranged in the FPGA chip 102, and since the hardware logic generated at the bottom layer by using the FPGA count does not occupy cpu resources, the processing speed and reliability of the processing are far higher than those of software design processing. And the coefficient and the power suppression of the filter are calculated through actual MATLAB simulation, are part of FPGA files, are not dependent on an upper computer, and improve the efficiency of filtering processing.
In one embodiment, as shown in fig. 3, fig. 3 is a schematic flow chart of a mass spectrum signal filtering method in another embodiment. Including a plurality of modules that may be implemented in whole or in part by software, hardware, and combinations thereof. The modules may be embedded in a hardware form or may be independent of a processor in a computer device, or may be stored in a memory in the FPGA chip 102 in a software form, so that the processor calls and executes operations corresponding to the modules. The method comprises the following steps: the ADC signal acquisition module 301 can acquire 16-bit data, acquire positive and negative voltage values, and let 0-32767 be a negative voltage value, 32768-65535 be a positive voltage value, 32768 be a 0 voltage value, and the overflow voltage be in a negative voltage region. After the acquisition is completed, the FPGA chip 102 may preprocess the signal, and, through the signal preprocessing module 302, arrange the overflow voltage and reduce the overall signal baseline to be close to 0 voltage, for example, through the data overflow determining module 303, determine the data exceeding the measurement range as the overflow data, and because the mass spectrometry scan acquired data has no negative voltage, define the data in the negative voltage region as the overflow data; the overflow data processing module 304 is used for replacing overflow data defined by the data overflow judging module with a maximum value 65535 to be used as data full scale processing, so that an overflow signal can be judged at a final image display end; by using the signal baseline calibration module 305, the lowest signal value in the noise is collected and judged in real time in the noise stage, the data is used as the simulated 0-pressure value, and the value is subtracted from the signal collected in real time, so that the purpose of baseline reduction and baseline calibration is achieved, the baseline with a large value can be reduced to be close to 0, the ratio of the noise to the actual signal is more prominent, and the algorithm effect of the later-stage filter is more remarkable. The FPGA chip 102 may further use the digital low-pass filter module 306 to design a training low-pass filter, for example, the FPGA chip 102 extracts a large number of real signals, uses a fourier algorithm to distinguish mass spectrum signals and noise in a frequency domain, uses MATLAB to design the low-pass filter, a passband is close to an edge frequency of the mass spectrum signals, a stopband suppresses noise intensity, extracts filter coefficients after MATLAB simulation, and designs and compiles the filter coefficients into an FPGA project to form a digital low-pass filter module inside the FPGA, specifically, at the beginning of design, the FPGA chip 102 derives actual image data, uses the fourier algorithm to display an entire signal in the frequency domain, a frequency domain of normal data is within a range of 0-0.5kHz, most of noise is outside the range of 0.5kHz, the FPGA chip 102 designs a 100-order low-pass filter according to a resource occupancy rate and an out-of-band signal suppression ratio, a coefficient of the low-pass filter module is designed inside the FPGA, a sampling frequency is 250kHz with adc, and a transmission frequency is 100MHz of a system clock frequency of the FPGA. After the digital signals are filtered by the FPGA chip 102, the processed signals may be uploaded to a display terminal through the data upload display module 307 according to a specified protocol and format to display a spectrogram, and whether the processed signals are correct or not may also be determined, for example, the FPGA chip 102 may use internet access transmission to integrate the data according to a network transmission protocol and transmit the data to the upper computer 104, and the upper computer 104 displays a mass spectrogram according to ion intensity.
Specifically, the process of filtering the digital signal by the FPGA chip 102 may also be as shown in fig. 4, where fig. 4 is a schematic flow chart of a mass spectrum signal filtering method in another embodiment. The method comprises the following steps: step 201, the FPGA chip 102 continuously acquires adc signals and continuously transmits the adc signals to the next module according to the acquisition frequency of 150 kHz; step 202, the FPGA chip 102 judges real-time data, and the judgment standard is that 0-32767 is a negative voltage region and 32768-65535 is a positive voltage region; step 203, if the data is in the interval of 0-32767, the data is negative voltage area data; step 204, the FPGA chip 102 marks the data of the negative voltage area as an overflow signal; step 205, the fpga chip 102 replaces the overflow signal with a full scale signal 65535; step 206, if the data is in the interval of 32768-65535, the data is positive voltage area data; step 207, the FPGA chip 102 marks the positive voltage region data as a normal signal; 208, the FPGA chip 102 monitors the processed signals in real time, and detects the minimum data as a baseline adjustment value; step 209, the FPGA chip 102 subtracts the baseline adjustment value from all the signals to finish the signal baseline calibration; step 210, the FPGA chip 102 passes the calibrated signal through a filter, and the noise of the output signal is suppressed, so that the signal-to-noise ratio is improved, and the noise and the useful signal can be obviously distinguished; step 211, the fpga chip 102 adjusts the processed data into a transmission format; step 212, transmitting the data of the FPGA chip 102; step 213, the FPGA chip 102 caches data to wait for the complete data of the whole image; step 214, displaying the mass spectrum image through the upper computer 104.
Through the embodiment, the filter is formed in the FPGA chip 102, and the baseline is adjusted based on the digital signal value, so that the signal waveform is smoother, and the processing efficiency of filtering the mass spectrum signal is improved. And the displayed mass spectrum image shows that the effect of the filter can obviously show that the noise is suppressed, the waveform of the effective signal is smoother, the effective signal with low intensity is submerged by the noise when not passing through the filter, and the effective signal can be exposed in a mass spectrum after being denoised.
It should be understood that although the various steps in the flowcharts of fig. 2-4 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-4 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternatively with other steps or at least some of the other steps or stages.
In one embodiment, as shown in fig. 5, there is provided a mass spectrum signal filtering apparatus including: an obtaining module 500, a determining module 502, an adjusting module 504, and a filtering module 506, wherein:
the acquiring module 500 is configured to acquire a digital signal to be processed corresponding to a mass spectrometer.
The determining module 502 is configured to determine a normal signal and an overflow signal in the digital signal to be processed according to a preset voltage value classification rule, and determine a signal baseline corresponding to the digital signal to be processed according to the normal signal and the overflow signal.
The adjusting module 504 is configured to adjust a value of the normal signal and a value of the overflow signal according to the signal baseline, so that the normal signal and the overflow signal are distributed more uniformly, and an adjusted digital signal is obtained.
The filtering module 506 is configured to input the adjusted digital signal into the filter module, and filter noise in the adjusted digital signal through the filter module to obtain a filtered digital signal.
In one embodiment, the above apparatus further comprises: the transmission module is used for converting the filtered digital signals into digital signals with a preset transmission format; and transmitting the digital signals with the preset transmission format to an upper computer so that the upper computer displays a corresponding mass spectrogram according to the ion intensity of the digital signals.
In an embodiment, the determining module 502 is specifically configured to obtain a preset digital signal lower limit, a preset zero voltage value, and a preset digital signal upper limit; the lower limit of the preset digital signal is smaller than a preset zero voltage value, and the preset zero voltage value is smaller than the upper limit of the preset digital signal; for each digital signal to be processed, comparing the numerical value of the digital signal with a preset digital signal lower limit, a preset zero voltage numerical value and a preset digital signal upper limit respectively; if the numerical value of the digital signal is greater than or equal to the zero voltage numerical value and less than the upper limit of the preset digital signal, determining the digital signal as a normal signal; and if the numerical value of the digital signal is greater than or equal to the lower limit of the preset digital signal and less than the preset zero voltage numerical value, determining the digital signal as an overflow signal.
In one embodiment, the above apparatus further comprises: and the exception handling module is used for replacing the numerical value of the overflow signal with a preset digital signal upper limit to obtain the adjusted overflow signal.
In an embodiment, the determining module 502 is specifically configured to obtain a minimum value of the digital signal values of the normal signal and the adjusted overflow signal, and use the minimum value as a signal baseline corresponding to the digital signal to be processed.
In an embodiment, the adjusting module 504 is specifically configured to, for each digital signal including the normal signal and/or the adjusted overflow signal, subtract the minimum value from the value of the digital signal to obtain an adjusted digital signal.
In one embodiment, the above apparatus further comprises: the training module is used for acquiring a low-pass filter to be trained and a plurality of sample digital signals; the plurality of sample digital signals comprise mass spectrum signals and noise signals; determining a mass spectrum signal and a noise signal in a plurality of sample digital signals; determining the passband edge frequency, the stopband edge frequency and the filter coefficient of the low-pass filter to be trained according to the frequency range of the mass spectrum signal; and obtaining a filter module according to the passband edge frequency, the stopband edge frequency and the filter coefficient.
In an embodiment, the filtering module 506 is specifically configured to input the adjusted digital signal to a filter module; and filtering the noise in the adjusted digital signal by a filter module based on the passband edge frequency, the stopband edge frequency and the filter coefficient to obtain the filtered digital signal.
For the specific definition of the mass spectrum signal filtering device, reference may be made to the definition of the mass spectrum signal filtering method above, and details are not repeated here. The modules in the mass spectrum signal filtering device can be wholly or partially realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent of a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, and the computer device may be an upper computer, and the internal structure diagram of the computer device may be as shown in fig. 6. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing data such as mass spectrum signals. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of filtering a mass spectrum signal.
Those skilled in the art will appreciate that the architecture shown in fig. 6 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory in which a computer program is stored and a processor which, when executing the computer program, implements the method of filtering a mass spectrum signal as described above.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, is adapted to carry out the method of filtering a mass spectrum signal as described above.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (10)
1. A method for filtering mass spectrum signals is applied to an FPGA chip, and comprises the following steps:
acquiring a digital signal to be processed corresponding to a mass spectrometer;
determining a normal signal and an overflow signal in the digital signal to be processed according to a preset voltage value classification rule, and determining a signal baseline corresponding to the digital signal to be processed according to the normal signal and the overflow signal;
according to the signal baseline, adjusting the value of the normal signal and the value of the overflow signal so as to enable the normal signal and the overflow signal to be distributed more uniformly, and obtaining an adjusted digital signal;
and inputting the adjusted digital signal into a filter module, and filtering noise in the adjusted digital signal through the filter module to obtain a filtered digital signal.
2. The method of claim 1, wherein the determining the normal signal and the overflow signal in the digital signal to be processed according to a preset voltage value classification rule comprises:
acquiring a preset digital signal lower limit, a preset zero voltage value and a preset digital signal upper limit; the lower limit of the preset digital signal is smaller than the preset zero pressure value, and the preset zero pressure value is smaller than the upper limit of the preset digital signal;
for each digital signal to be processed, comparing the numerical value of the digital signal with the preset digital signal lower limit, the preset zero voltage numerical value and the preset digital signal upper limit respectively;
if the numerical value of the digital signal is greater than or equal to the zero voltage numerical value and less than the preset digital signal upper limit, determining the digital signal as a normal signal;
and if the numerical value of the digital signal is greater than or equal to the lower limit of the preset digital signal and less than the preset zero voltage numerical value, determining the digital signal as an overflow signal.
3. The method of claim 2, wherein after determining the normal signal and the overflow signal in the digital signal to be processed, and before determining the signal baseline corresponding to the digital signal to be processed according to the normal signal and the overflow signal, further comprising:
and replacing the numerical value of the overflow signal with the preset digital signal upper limit to obtain the adjusted overflow signal.
4. The method of claim 3, wherein determining a signal baseline corresponding to the digital signal to be processed from the normal signal and the overflow signal comprises:
acquiring the minimum value of the digital signal values of the normal signal and the adjusted overflow signal, and taking the minimum value as a signal baseline corresponding to the digital signal to be processed;
the adjusting the value of the normal signal and the value of the overflow signal according to the signal baseline to make the normal signal and the overflow signal distributed uniformly to obtain an adjusted digital signal includes:
and for each digital signal comprising the normal signal and/or the adjusted overflow signal, subtracting the minimum value from the value of the digital signal to obtain the adjusted digital signal.
5. The method of claim 1, further comprising:
acquiring a low-pass filter to be trained and a plurality of sample digital signals; the plurality of sample digital signals comprise mass spectrum signals and noise signals;
determining a mass spectral signal and a noise signal in the plurality of sample digital signals;
determining the pass band edge frequency, the stop band edge frequency and the filter coefficient of the low-pass filter to be trained according to the frequency range of the mass spectrum signal;
and obtaining the filter module according to the passband edge frequency, the stopband edge frequency and the filter coefficient.
6. The method of claim 5, wherein the inputting the adjusted digital signal into a filter module, and filtering noise in the adjusted digital signal by the filter module to obtain a filtered digital signal comprises:
inputting the adjusted digital signal into a filter module;
and filtering, by the filter module, noise in the adjusted digital signal based on the passband edge frequency, the stopband edge frequency and the filter coefficient to obtain a filtered digital signal.
7. The method of claim 1, wherein after obtaining the filtered digital signal, further comprising:
converting the filtered digital signal into a digital signal with a preset transmission format;
and transmitting the digital signal in the preset transmission format to an upper computer so that the upper computer displays a corresponding mass spectrogram according to the ion intensity of the digital signal.
8. A mass spectrum signal filtering apparatus for use with an FPGA chip, the apparatus comprising:
the acquisition module is used for acquiring a digital signal to be processed corresponding to the mass spectrometer;
the determining module is used for determining a normal signal and an overflow signal in the digital signal to be processed according to a preset voltage value classification rule, and determining a signal base line corresponding to the digital signal to be processed according to the normal signal and the overflow signal;
the adjusting module is used for adjusting the value of the normal signal and the value of the overflow signal according to the signal baseline so as to enable the normal signal and the overflow signal to be distributed more uniformly and obtain an adjusted digital signal;
and the filtering module is used for inputting the adjusted digital signal into the filter module, and filtering noise in the adjusted digital signal through the filter module to obtain a filtered digital signal.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.
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