CN115633251A

CN115633251A - Image processing method, circuit and electronic equipment

Info

Publication number: CN115633251A
Application number: CN202211103477.3A
Authority: CN
Inventors: 单昌鹏
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2022-09-09
Filing date: 2022-09-09
Publication date: 2023-01-20

Abstract

The application provides an image processing method, an image processing circuit and electronic equipment, and belongs to the technical field of image processing. The image processing method is applied to an image processing device, the image processing device comprises a camera module, an image processing chip, a main control chip and a display screen, the image processing chip is respectively connected with the camera module, the main control chip and the display screen, and the method comprises the following steps: under the condition that the image processing chip receives first image data sent by the camera module, controlling the image processing chip to perform first image processing on the first image data to obtain second image data, and sending the second image data to the display screen for displaying; and under the condition that the image processing chip receives the third image data sent by the main control chip, controlling the image processing chip to perform second image processing on the third image data to obtain fourth image data, and sending the fourth image data to the display screen for displaying.

Description

Image processing method, circuit and electronic equipment

Technical Field

The present application belongs to the field of image processing technologies, and in particular, to an image processing method, circuit, and electronic device.

Background

With the development of electronic technology, more and more users use electronic devices to take pictures. The electronic device usually has a main control chip, also called an Application Processor (AP), and an image processing chip, which is used for processing an image accordingly.

Disclosure of Invention

The embodiment of the application aims to provide an image processing method, an image processing circuit and electronic equipment, which can improve the real-time property of image preview.

In a first aspect, an embodiment of the present application provides an image processing method, which is applied to an image processing apparatus, where the image processing apparatus includes a camera module, an image processing chip, a main control chip, and a display screen, and the image processing chip is connected to the camera module, the main control chip, and the display screen, respectively, and the method includes:

under the condition that the image processing chip receives first image data sent by the camera module, controlling the image processing chip to perform first image processing on the first image data to obtain second image data, and sending the second image data to the display screen for displaying;

and under the condition that the image processing chip receives third image data sent by the main control chip, controlling the image processing chip to perform second image processing on the third image data to obtain fourth image data, and sending the fourth image data to the display screen for displaying.

In a second aspect, an embodiment of the present application provides an image processing circuit, where the circuit includes a main control chip and an image processing chip, and the main control chip is connected to the image processing chip;

the image processing chip is used for carrying out first image processing on first image data sent by the camera module to obtain second image data and sending the second image data to the display screen for displaying;

the main control chip is used for sending third image data to the image processing chip;

the image processing chip is further used for carrying out second image processing on the third image data to obtain fourth image data, and sending the fourth image data to the display screen for displaying.

In a third aspect, an embodiment of the present application provides an image processing circuit, where the circuit includes a main control chip and an image processing chip, the main control chip includes a first interface and a second interface, and the image processing chip includes a third interface, a fourth interface, a fifth interface, a sixth interface, a first image processing module, and a second image processing module;

the first interface is connected with the third interface, the second interface is connected with the fourth interface, the first image processing module is respectively connected with the fifth interface and the second image processing module, and the second image processing module is respectively connected with the third interface, the fourth interface and the sixth interface;

the fifth interface is used for receiving first image data output by a camera module, the first image processing module and the second image processing module are used for performing first image processing on the first image data to obtain second image data, and the sixth interface is used for outputting the second image data to a display screen;

the first interface is used for outputting third image data to the image processing chip;

the first image processing module and the second image processing module are used for carrying out second image processing on the third image data to obtain fourth image data, and the sixth interface is further used for outputting the fourth image data to a display screen.

In a fourth aspect, an embodiment of the present application provides an electronic device, which includes an image pickup module, a display screen, and an image processing circuit, where the image processing circuit is connected to the image pickup module and the display screen, respectively, and the image processing circuit is configured as the image processing circuit described in the second aspect above, or configured as the image processing circuit described in the third aspect above.

In a fifth aspect, embodiments of the present application provide a readable storage medium, on which a program or instructions are stored, which when executed by a processor implement the steps of the method according to the first aspect.

In a sixth aspect, embodiments of the present application provide a computer program product, stored on a storage medium, for execution by at least one processor to implement the method according to the first aspect.

In the embodiment of the application, under the condition that the image processing chip receives first image data sent by the camera module, the image processing chip is controlled to perform first image processing on the first image data to obtain second image data, and the second image data is sent to the display screen to be displayed; and under the condition that the image processing chip receives the third image data sent by the main control chip, controlling the image processing chip to perform second image processing on the third image data to obtain fourth image data, and sending the fourth image data to the display screen for displaying. In the image processing process, after the image processing chip is controlled to perform image processing on the image data, the image data after the image processing is directly sent to the display screen to be displayed without being transmitted back to the main control chip, so that the image after the image processing is displayed on the display screen in real time, the real-time property of image preview is improved, and the power consumption of the main control chip can be reduced.

Drawings

Fig. 1 is a flowchart of an image processing method provided in an embodiment of the present application;

FIG. 2 is a flowchart of an application of an image processing method provided in an embodiment of the present application;

fig. 3 is a second flowchart of an application of the image processing method according to the embodiment of the present application;

FIG. 4 is a schematic structural diagram of an image processing circuit provided in an embodiment of the present application;

FIG. 5 is a block diagram of an electronic device provided in an embodiment of the present application;

fig. 6 is a hardware structure diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived from the embodiments in the present application by a person skilled in the art, are within the scope of protection of the present application.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.

The image processing method provided by the embodiment of the present application is described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.

In the related art, the process of image processing on image data is generally: the camera module sends the image data to the main control chip, the main control chip sends the image data to the image processing chip for image processing, the image processing chip transmits the processed image data back to the main control chip, and the main control chip stores the image data and sends the image data to the display screen for displaying.

In the above process, the image data after image processing needs to be transmitted back to the main control chip and then displayed on the display screen, which results in increased time delay and higher power consumption of the main control chip.

In order to solve the above technical problem, an embodiment of the present application provides an image processing method, please refer to fig. 1, and fig. 1 is a flowchart of the image processing method provided in the embodiment of the present application. The image processing method provided by the embodiment of the application is applied to an image processing device, the image processing device comprises a camera module, an image processing chip, a main control chip and a display screen, the image processing chip is respectively connected with the camera module, the main control chip and the display screen, and the method comprises the following steps:

s101, under the condition that an image processing chip receives first image data sent by a camera module, the image processing chip is controlled to carry out first image processing on the first image data to obtain second image data, and the second image data is sent to a display screen to be displayed.

The first image data is image data sent by the camera module, and optionally, the first image data is image data collected by the camera module, in which case, the data format of the first image data is RAW.

In this step, the camera module sends the first image data to the image processing chip, the main control chip controls the image processing chip to perform first image processing on the first image data, determines the image data after the first image processing as second image data, and controls the image processing chip to send the second image data to the display screen for displaying. The first image processing comprises front-end image signal processing, rear-end image signal processing and superposition processing, and the superposition processing is to superpose the image data subjected to the first image processing and user interface data.

S102, under the condition that the image processing chip receives third image data sent by the main control chip, the image processing chip is controlled to perform second image processing on the third image data to obtain fourth image data, and the fourth image data is sent to the display screen to be displayed.

The third image data is image data sent by the main control chip, and optionally, the third image data is video data generated by playing a video, or picture data generated by browsing a picture, or related data generated by using an application program, for example, game image data or game video data generated in the process of starting a game program.

In this step, the main control chip sends the third image data to the image processing chip, and the main control chip controls the image processing chip to perform second image processing on the third image data, determines the image data after the second image processing as fourth image data, and controls the image processing chip to send the third image data to the display screen for displaying. Wherein the second image processing includes the back-end image signal processing.

Optionally, the controlling the image processing chip to perform first image processing on the first image data to obtain second image data includes:

controlling the image processing chip to perform front-end image signal processing on the first image data to obtain image data to be enhanced;

controlling the image processing chip to perform super-resolution processing on the image data to be enhanced under the condition that the resolution of the image data to be enhanced is smaller than a first preset resolution to obtain second image data;

controlling the image processing chip to perform frame interpolation processing on the image data to be enhanced under the condition that the frame rate of the image data to be enhanced is smaller than a first preset frame rate to obtain second image data;

and controlling the image processing chip to perform high dynamic range processing on the image data to be enhanced under the condition that the image data to be enhanced is a high dynamic range video source to obtain second image data.

In this embodiment, after receiving the first image data, the image processing chip performs front-end image signal processing on the first image data to obtain image data to be enhanced, and please refer to the following embodiments for a specific implementation process of front-end image signal processing.

After the image data to be enhanced are obtained, the main control chip controls the image processing chip to perform back-end image signal processing on the image data to be enhanced. It should be understood that the main control chip may send related instructions to the image processing chip to control the image processing chip to perform corresponding operations.

The following specifically explains the process of performing back-end image signal processing on image data to be enhanced:

the main control chip controls the image processing chip to obtain the resolution of the image data to be enhanced, and under the condition that the resolution of the image data to be enhanced is smaller than a first preset resolution, the resolution of the image data to be enhanced is low, the image data to be enhanced is subjected to super-resolution processing, the resolution of the image data to be enhanced is improved, and second image data is obtained. The image super-resolution processing refers to an image processing technology for processing a low-resolution image to obtain a high-resolution image.

The main control chip controls the image processing chip to obtain the frame rate of the image data to be enhanced, and under the condition that the frame rate of the image data to be enhanced is smaller than a first preset frame rate, the frame rate of the image data to be enhanced is low, frame interpolation processing is carried out on the image data to be enhanced, the frame rate of the image data to be enhanced is improved, and second image data are obtained. The frame interpolation processing is to increase the frame rate of the image data so as to make the image clearer.

The main control chip controls the image processing chip to judge whether the image data to be enhanced is a high dynamic range video source or not through metadata information (metadata information) of the image data to be enhanced, and under the condition that the image data to be enhanced is the high dynamic range video source, the image data to be enhanced is subjected to high dynamic range processing to obtain second image data. It should be understood that in the case where the image data to be enhanced is not a high dynamic range video source, then no high dynamic range processing is performed on the image data to be enhanced. The high dynamic range processing is a scene image fusion technology which generates high-quality vivid effects and can provide more dynamic range and image details for images.

In this embodiment, the image processing chip is controlled to perform front-end image signal processing and back-end image signal processing on the first image data, so as to obtain second image data with higher image quality.

The following specifically describes the procedure of performing front-end image signal processing on the first image data:

optionally, the controlling the image processing chip to perform front-end image signal processing on the first image data to obtain image data to be enhanced includes:

controlling the image processing chip to perform automatic focusing, automatic exposure and automatic white balance on the first image data to obtain image data to be processed;

controlling the image processing chip to perform demosaicing processing on the image data to be processed to obtain image data to be denoised;

and controlling the image processing chip to perform noise reduction processing on the image data to be subjected to noise reduction processing to obtain the image data to be enhanced.

In this embodiment, the main control chip controls the image processing chip to perform 3A processing on the first image data to obtain image data to be processed. The 3A processing comprises automatic focusing, automatic exposure and automatic white balance, and the condition of overexposure or underexposure of the main shot object is improved through the 3A processing, so that the chromatic aberration of the image under different light irradiation is compensated.

After the image data to be processed is obtained, the main control chip controls the image processing chip to perform demosaicing processing on the image data to be processed, and image data to be denoised are obtained. Alternatively, demosaicing may be performed using image processing software, such as PS; or demosaicing using a filter.

After the image data to be denoised is obtained, the main control chip controls the image processing chip to denoise the image data to be denoised to obtain the image data to be enhanced. Alternatively, a median filter may be used to perform denoising processing on the image data to be denoised, or a markov random field model may be used to perform denoising processing on the image data to be denoised, or other methods may be used to perform denoising processing, which is not limited in this respect.

In this embodiment, the image processing chip is controlled to perform auto focus, auto exposure, auto white balance, demosaic processing, and noise reduction on the first image data, so as to implement front-end image processing on the first image data, and obtain image data to be enhanced with higher image quality.

Optionally, after obtaining the second image data, the method further includes:

under the condition of receiving a storage instruction, controlling the image processing chip to send the second image data to the main control chip;

storing the second image data.

In this embodiment, the main control chip controls the image processing chip to send the second image data to the main control chip when receiving a storage instruction sent by a user, and the main control chip stores the second image data in the local memory.

In other embodiments, if the main control chip does not receive the storage instruction sent by the user, the second image data is not stored in the local memory.

In this embodiment, the main control chip stores the second image data based on the received storage instruction, so that a user can conveniently query the second image data at any time.

For the sake of understanding the overall technical solution of image processing on the first image data, please refer to fig. 2. As shown in fig. 2, the camera module acquires first image data, sends the first image data to the image processing chip, and the main control chip controls the image processing chip to perform front-end image signal processing on the first image data to obtain image data to be enhanced. The main control chip controls the image processing chip to judge whether the image to be enhanced is subjected to super-resolution processing, frame interpolation processing and high dynamic range processing. And under the condition that the hyper-resolution processing, the frame interpolation processing and the high dynamic range processing are required, controlling the image processing chip to perform the hyper-resolution processing, the frame interpolation processing and the high dynamic range processing on the image data to be enhanced to obtain second image data. And under the condition that the super-resolution processing, the frame interpolation processing and the high dynamic range processing are not required, determining the first image data as second image data, and displaying the second image data on a display screen. Whether the main control chip receives the storage instruction or not, and under the condition that the main control chip receives the storage instruction, controlling the image processing chip to transmit the second image data back to the main control chip, wherein the main control chip stores the second image data; and under the condition that the main control chip does not receive the storage instruction, not storing the second image data.

Optionally, the controlling the image processing chip to perform second image processing on the third image data to obtain fourth image data includes:

controlling the image processing chip to perform super-resolution processing on the third image data under the condition that the resolution of the third image data is smaller than a second preset resolution to obtain fourth image data;

controlling the image processing chip to perform frame interpolation processing on the third image data under the condition that the frame rate of the third image data is smaller than a second preset frame rate to obtain fourth image data;

and under the condition of receiving a high dynamic range processing instruction, controlling the image processing chip to perform high dynamic range processing on the third image data to obtain fourth image data.

As described above, the third image data is the image data sent by the main control chip.

In this embodiment, the main control chip controls the image processing chip to perform back-end image signal processing on the third image data.

Specifically, the main control chip controls the image processing chip to obtain the resolution of the third image data, and when the resolution of the third image data is smaller than a second preset resolution, the third image data is subjected to super-resolution processing to improve the resolution of the third image data and obtain fourth image data, which indicates that the resolution of the third image data is lower. The second preset resolution may be the same as or different from the first preset resolution, and is not specifically limited herein.

The main control chip controls the image processing chip to obtain a frame rate of the third image data, and under the condition that the frame rate of the third image data is smaller than a second preset frame rate, the frame rate of the third image data is lower, frame interpolation processing is carried out on the third image data, the frame rate of the third image data is improved, and fourth image data is obtained. The second preset frame rate may be the same as or different from the first preset frame rate, and is not limited herein.

And under the condition that the main control chip receives a high dynamic range processing instruction sent by a user, the main control chip controls the image processing chip to perform high dynamic range processing on the third image data to obtain fourth image data. An optional implementation scenario is that when the user uses the application program, a high dynamic range processing instruction is sent to the master control chip.

In this embodiment, the image processing chip is controlled to perform back-end image signal processing on the third image data, so as to implement image processing on the third image data sent by the main control chip, and obtain fourth image data with higher image quality.

For the sake of understanding the overall technical solution of image processing on the third image data, please refer to fig. 3. As shown in fig. 3, the main control chip sends the third image data to the image processing chip, and the image processing chip determines whether the third image data is subjected to super-resolution processing, frame interpolation processing, and high dynamic range processing. Under the condition that the third image data needs to be subjected to super-resolution processing, frame interpolation processing and high dynamic range processing, carrying out super-resolution processing, frame interpolation processing and high dynamic range processing on the third image data to obtain fourth image data; and determining the third image data as fourth image data under the condition that the third image data does not need to be subjected to super-resolution processing, frame interpolation processing and high dynamic range processing. Further, the main control chip controls the image processing chip to send the fourth image data to the display screen, and the display screen displays the fourth image data.

The embodiment of the present application further provides an image processing circuit, and the image processing circuit provided in the embodiment of the present application is described in detail through specific embodiments and application scenarios thereof with reference to the accompanying drawings.

As shown in fig. 4, the image processing circuit provided in the embodiment of the present application includes a main control chip 10 and an image processing chip 20, where the main control chip 10 is connected to the image processing chip 20;

the image processing chip 20 is configured to perform first image processing on first image data sent by the camera module 30 to obtain second image data, and send the second image data to the display screen 40 for displaying;

the main control chip 10 is configured to send third image data to the image processing chip 20;

the image processing chip 20 is further configured to perform second image processing on the third image data to obtain fourth image data, and send the fourth image data to the display screen 40 for displaying.

In the embodiment of the application, under the condition that the image processing chip receives first image data sent by the camera module, the image processing chip is controlled to perform first image processing on the first image data to obtain second image data, and the second image data is sent to the display screen to be displayed; and under the condition that the image processing chip receives the third image data sent by the main control chip, controlling the image processing chip to perform second image processing on the third image data to obtain fourth image data, and sending the fourth image data to the display screen for displaying. In the image processing process, after the image processing chip is controlled to perform image processing on the image data, the image data after the image processing is directly sent to the display screen 40 to be displayed without being transmitted back to the main control chip, so that the image after the image processing is displayed on the display screen in real time, the real-time property of image preview is improved, and the power consumption of the main control chip can be reduced.

Optionally, the image processing chip 20 is further configured to perform front-end image signal processing on the first image data to obtain image data to be enhanced;

the image processing chip 20 is further configured to perform a super-resolution processing on the image data to be enhanced to obtain second image data when the resolution of the image data to be enhanced is smaller than a first preset resolution;

the image processing chip 20 is further configured to perform frame interpolation on the image data to be enhanced to obtain second image data when the frame rate of the image data to be enhanced is less than a first preset frame rate;

the image processing chip 20 is further configured to perform high dynamic range processing on the image data to be enhanced to obtain the second image data when the image data to be enhanced is a high dynamic range video source.

In this embodiment, the image processing chip 20 is controlled to perform front-end image signal processing and back-end image signal processing on the first image data, so as to obtain second image data with higher image quality.

Optionally, the image processing chip 20 is further configured to perform auto focusing, auto exposure, and auto white balance on the first image data to obtain image data to be processed;

the image processing chip 20 is further configured to perform demosaicing processing on the image data to be processed to obtain image data to be denoised;

the image processing chip 20 is further configured to perform noise reduction processing on the image data to be subjected to noise reduction processing, so as to obtain the image data to be enhanced.

Optionally, the image processing chip 20 is further configured to send the second image data to the main control chip 10 when receiving a storage instruction;

the main control chip 10 is further configured to store the second image data.

Optionally, the image processing chip 20 is further configured to perform, when the resolution of the third image data is smaller than a second preset resolution, a super-resolution process on the third image data to obtain fourth image data;

the image processing chip 20 is further configured to perform frame interpolation processing on the third image data to obtain fourth image data when the frame rate of the third image data is less than a second preset frame rate;

the main control chip 10 is further configured to control the image processing chip 20 to perform high dynamic range processing on the third image data to obtain the fourth image data when a high dynamic range processing instruction is received.

In this embodiment, the image processing chip 20 is controlled to perform back-end image signal processing on the third image data, so as to implement image processing on the third image data sent by the main control chip 10, and obtain fourth image data with higher image quality.

The embodiment of the present application further provides an image processing circuit, which is described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.

As shown in fig. 4, the image processing circuit provided in the embodiment of the present application includes a main control chip 10 and an image processing chip 20, where the main control chip 10 includes a first interface K1 and a second interface K2, and the image processing chip 20 includes a third interface K3, a fourth interface K4, a fifth interface K5, a sixth interface K6, a first image processing module 21, and a second image processing module 22;

the first interface K1 is connected to the third interface K3, the second interface K2 is connected to the fourth interface K4, the first image processing module 21 is respectively connected to the fifth interface K5 and the second image processing module 22, and the second image processing module 22 is respectively connected to the third interface K3, the fourth interface K4 and the sixth interface K6;

the fifth interface K5 is configured to receive first image data output by the camera module 30, the first image processing module 21 and the second image processing module 22 are configured to perform first image processing on the first image data to obtain second image data, and the sixth interface K6 is configured to output the second image data to the display screen 40;

the first interface K1 is configured to output third image data to the image processing chip 20;

the first image processing module 21 and the second image processing module 22 are configured to perform second image processing on the third image data to obtain fourth image data, and the sixth interface K6 is further configured to output the fourth image data to the display screen 40.

The first Image processing module 21 has a function of a Pre-Image Signal Processor (Pre-ISP) chip, and the second Image processing module 22 has a function of a Post-Image Signal Processor (Post-ISP) chip. The first Interface K1 is a Display Serial Interface (DSI) transmission Interface; the second Interface K2 is a Camera Serial Interface (CSI) receiving Interface; the third interface K3 is a DSI receiving interface; the fourth interface K4 is a CSI transmission interface; the fifth interface K5 is a CSI receiving interface; the sixth interface K6 is a DSI transmission interface.

Optionally, as shown in fig. 4, the camera module 30 includes a seventh interface K7, the camera module 30 is connected to the image processing chip 20 through the seventh interface K7, and the seventh interface K7 is a CSI transmission interface.

Optionally, as shown in fig. 4, the display screen 40 includes an eighth interface K8, the display screen 40 is connected to the image processing chip 20 through the eighth interface K8, and the eighth interface K8 is a DSI receiving interface.

Optionally, the first image processing module 21 is configured to perform front-end image signal processing on the first image data to obtain image data to be enhanced;

the second image processing module 22 is configured to perform a super-resolution processing on the image data to be enhanced to obtain second image data when the resolution of the image data to be enhanced is smaller than a first preset resolution;

the second image processing module 22 is configured to perform frame interpolation on the image data to be enhanced to obtain second image data when the frame rate of the image data to be enhanced is less than a first preset frame rate;

the second image processing module 22 is configured to, when the image data to be enhanced is a high dynamic range video source, perform high dynamic range processing on the image data to be enhanced to obtain the second image data.

In this embodiment, the first image processing module 21 is configured to perform front-end image signal processing on the image data, and the second image processing module 22 is configured to perform back-end image signal processing on the image data.

In this embodiment, the first image processing module 21 is controlled to perform front-end image signal processing on the first image data, and the second image processing module 22 is controlled to perform back-end image signal processing on the image data to be enhanced, so as to obtain second image data with higher image quality.

Optionally, the first image processing module 21 is further configured to perform automatic focusing, automatic exposure, and automatic white balance on the first image data to obtain image data to be processed;

the first image processing module 21 is further configured to perform demosaicing processing on the image data to be processed to obtain image data to be denoised;

the first image processing module 21 is further configured to perform noise reduction processing on the image data to be noise reduced to obtain the image data to be enhanced.

In this embodiment, the first image processing module 21 is controlled to perform auto focus, auto exposure, auto white balance, demosaic processing, and noise reduction on the first image data, so as to implement front-end image processing on the first image data, and obtain image data to be enhanced with higher image quality.

Optionally, the image processing chip 20 is further configured to send the second image data to the main control chip 10 through the fourth interface K4 when receiving a storage instruction;

the image processing circuit further comprises a memory, the memory is connected with the main control chip 10, and the memory is used for storing the second image data.

In this embodiment, the main control chip 10 stores the second image data based on the received storage instruction, so that the user can conveniently query the second image data at any time.

Optionally, the second image processing module 22 is further configured to perform a super-resolution processing on the third image data to obtain fourth image data when the resolution of the third image data is smaller than a second preset resolution;

the second image processing module 22 is further configured to perform frame interpolation processing on the third image data to obtain fourth image data when the frame rate of the third image data is less than a second preset frame rate;

the main control chip 10 is further configured to control the second image processing module 22 to perform high dynamic range processing on the third image data to obtain fourth image data when a high dynamic range processing instruction is received.

In this embodiment, the main control chip 10 controls the second image processing module 22 to perform back-end image signal processing on the third image data.

Optionally, as shown in fig. 5, an electronic device 500 is further provided in an embodiment of the present application, and includes a camera module 501, a display screen 502, and an image processing circuit 503, where the image processing circuit 503 is connected to the camera module 501 and the display screen 502, respectively, and the image processing circuit 503 is configured as the image processing circuit described above. Moreover, the electronic device can implement each process of the image processing method embodiment, and can achieve the same technical effect, and further description is omitted here to avoid repetition.

The electronic Device may be, for example, a Mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic Device, a Mobile Internet Device (MID), an Augmented Reality (AR)/Virtual Reality (VR) Device, a robot, a wearable Device, an ultra-Mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and may also be a server, a Network Attached Storage (Network Attached Storage, NAS), a personal computer (NAS), a Television (TV), an assistant, a teller machine, a self-service machine, and the like, and the embodiments of the present application are not limited in particular.

Fig. 6 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.

The electronic device 600 includes, but is not limited to: a radio frequency unit 601, a network module 602, an audio output unit 603, an input unit 604, a sensor 605, a display unit 606, a user input unit 607, an interface unit 608, a memory 609, a processor 610, and the like. The processor 610 may be a main control chip, and the electronic device 600 further includes an image processing chip, where the main control chip is in communication connection with the image processing chip.

Those skilled in the art will appreciate that the electronic device 600 may further comprise a power source (e.g., a battery) for supplying power to the various components, and the power source may be logically connected to the processor 610 through a power management system, so as to implement functions of managing charging, discharging, and power consumption through the power management system. The electronic device structure shown in fig. 6 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than those shown, or combine some components, or arrange different components, and thus, the description is omitted here.

The processor 610 is configured to, when the image processing chip receives first image data sent by a camera module, control the image processing chip to perform first image processing on the first image data to obtain second image data, and send the second image data to the display screen for displaying;

and under the condition that the image processing chip receives third image data sent by the processor 610, controlling the image processing chip to perform second image processing on the third image data to obtain fourth image data, and sending the fourth image data to the display screen for displaying.

The processor 610 is further configured to control the image processing chip to perform front-end image signal processing on the first image data to obtain image data to be enhanced;

and controlling the image processing chip to perform high dynamic range processing on the image data to be enhanced under the condition that the image data to be enhanced is a high dynamic range video source to obtain the second image data.

The processor 610 is further configured to control the image processing chip to perform auto focus, auto exposure, and auto white balance on the first image data to obtain image data to be processed;

controlling the image processing chip to demosaic the image data to be processed to obtain image data to be denoised;

The processor 610 is further configured to control the image processing chip to send the second image data to the main control chip when receiving a storage instruction;

storing the second image data.

The processor 610 is further configured to control the image processing chip to perform a super-resolution processing on the third image data to obtain fourth image data when the resolution of the third image data is smaller than a second preset resolution;

controlling the image processing chip to perform frame interpolation processing on the third image data to obtain fourth image data under the condition that the frame rate of the third image data is smaller than a second preset frame rate;

It is to be understood that, in the embodiment of the present application, the input Unit 604 may include a Graphics Processing Unit (GPU) 6041 and a microphone 6042, and the Graphics Processing Unit 6041 processes image data of a still picture or a video obtained by an image capturing apparatus (such as a camera) in a video capturing mode or an image capturing mode. The display unit 606 may include a display panel 6061, and the display panel 6061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 606 includes at least one of a touch panel 6061 and other input devices 6062. A touch panel 6061, also referred to as a touch screen. The touch panel 6061 may include two portions of a touch detection device and a touch controller. Other input devices 6062 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which are not described in detail herein.

The memory 609 may be used to store software programs as well as various data. The memory 609 may mainly include a first storage area storing a program or an instruction and a second storage area storing data, wherein the first storage area may store an operating system, an application program or an instruction (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 609 may include volatile memory or nonvolatile memory, or the memory 609 may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. The volatile Memory may be a Random Access Memory (RAM), a Static Random Access Memory (Static RAM, SRAM), a Dynamic Random Access Memory (Dynamic RAM, DRAM), a Synchronous Dynamic Random Access Memory (Synchronous DRAM, SDRAM), a Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate SDRAM, ddr SDRAM), an Enhanced Synchronous SDRAM (ESDRAM), a Synchronous Link DRAM (SLDRAM), and a Direct Memory bus RAM (DRRAM). The memory 609 in the embodiments of the subject application include, but are not limited to, these and any other suitable types of memory.

Processor 610 may include one or more processing units; optionally, the processor 610 integrates an application processor, which primarily handles operations involving the operating system, user interface, and applications, etc., and a modem processor, which primarily handles wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 610.

The embodiments of the present application further provide a readable storage medium, where a program or an instruction is stored, and when the program or the instruction is executed by a processor, the program or the instruction implements the processes of the embodiment of the image processing method, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.

The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic or optical disk, and the like.

Embodiments of the present application provide a computer program product, where the program product is stored in a storage medium, and the program product is executed by at least one processor to implement each process of the foregoing image processing method embodiments, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatuses in the embodiments of the present application is not limited to performing the functions in the order illustrated or discussed, but may include performing the functions in a substantially simultaneous manner or in a reverse order based on the functions recited, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

Through the description of the foregoing embodiments, it is clear to those skilled in the art that the method of the foregoing embodiments may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application may be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present application.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An image processing method is applied to an image processing device, and is characterized in that the image processing device comprises a camera module, an image processing chip, a main control chip and a display screen, wherein the image processing chip is respectively connected with the camera module, the main control chip and the display screen, and the method comprises the following steps:

2. The method according to claim 1, wherein the controlling the image processing chip to perform the first image processing on the first image data to obtain the second image data comprises:

3. The method according to claim 2, wherein the controlling the image processing chip to perform front-end image signal processing on the first image data to obtain image data to be enhanced comprises:

4. The method of any of claims 1-3, wherein after obtaining the second image data, the method further comprises:

storing the second image data.

5. The method according to claim 1, wherein the controlling the image processing chip to perform the second image processing on the third image data to obtain fourth image data comprises:

6. The image processing circuit is characterized by comprising a main control chip and an image processing chip, wherein the main control chip is connected with the image processing chip;

7. The image processing circuit of claim 6, wherein the image processing chip is further configured to perform front-end image signal processing on the first image data to obtain image data to be enhanced;

the image processing chip is further used for carrying out super-resolution processing on the image data to be enhanced under the condition that the resolution of the image data to be enhanced is smaller than a first preset resolution, so that second image data are obtained;

the image processing chip is further used for performing frame interpolation processing on the image data to be enhanced under the condition that the frame rate of the image data to be enhanced is smaller than a first preset frame rate to obtain second image data;

the image processing chip is further configured to perform high dynamic range processing on the image data to be enhanced to obtain the second image data when the image data to be enhanced is a high dynamic range video source.

8. The image processing circuit of claim 7, wherein the image processing chip is further configured to perform auto focus, auto exposure, and auto white balance on the first image data to obtain image data to be processed;

the image processing chip is also used for demosaicing the image data to be processed to obtain image data to be denoised;

the image processing chip is further used for carrying out noise reduction processing on the image data to be subjected to noise reduction processing to obtain the image data to be enhanced.

9. The image processing circuit according to any of claims 6-8, wherein the image processing chip is further configured to send the second image data to the master control chip if a storage instruction is received;

the main control chip is also used for storing the second image data.

10. The image processing circuit according to claim 6, wherein the image processing chip is further configured to perform a super-resolution process on the third image data to obtain the fourth image data when a resolution of the third image data is smaller than a second preset resolution;

the image processing chip is further configured to perform frame interpolation processing on the third image data to obtain fourth image data when the frame rate of the third image data is less than a second preset frame rate;

and the main control chip is also used for controlling the image processing chip to perform high dynamic range processing on the third image data under the condition of receiving a high dynamic range processing instruction to obtain the fourth image data.

11. An image processing circuit is characterized by comprising a main control chip and an image processing chip, wherein the main control chip comprises a first interface and a second interface, and the image processing chip comprises a third interface, a fourth interface, a fifth interface, a sixth interface, a first image processing module and a second image processing module;

the first image processing module and the second image processing module are used for performing second image processing on the third image data to obtain fourth image data, and the sixth interface is further used for outputting the fourth image data to a display screen.

12. The image processing circuit of claim 11, wherein the first image processing module is configured to perform front-end image signal processing on the first image data to obtain image data to be enhanced;

the second image processing module is used for performing super-resolution processing on the image data to be enhanced under the condition that the resolution of the image data to be enhanced is smaller than a first preset resolution to obtain second image data;

the second image processing module is used for performing frame interpolation processing on the image data to be enhanced under the condition that the frame rate of the image data to be enhanced is smaller than a first preset frame rate to obtain second image data;

and the second image processing module is used for carrying out high dynamic range processing on the image data to be enhanced under the condition that the image data to be enhanced is a high dynamic range video source to obtain the second image data.

13. The image processing circuit of claim 12, wherein the first image processing module is further configured to perform auto-focusing, auto-exposure, and auto-white balance on the first image data to obtain image data to be processed;

the first image processing module is further configured to perform demosaicing processing on the image data to be processed to obtain image data to be denoised;

the first image processing module is further configured to perform noise reduction processing on the image data to be noise reduced to obtain the image data to be enhanced.

14. The image processing circuit according to any of claims 11-13, wherein the image processing chip is further configured to send the second image data to the master control chip through the fourth interface if a storage instruction is received;

the image processing circuit further comprises a memory, the memory is connected with the main control chip, and the memory is used for storing the second image data.

15. The image processing circuit of claim 11, wherein the second image processing module is further configured to perform a super-resolution process on the third image data to obtain the fourth image data when the resolution of the third image data is smaller than a second preset resolution;

the second image processing module is further configured to perform frame interpolation processing on the third image data to obtain fourth image data when the frame rate of the third image data is less than a second preset frame rate;

the main control chip is further configured to control the second image processing module to perform high dynamic range processing on the third image data to obtain the fourth image data when a high dynamic range processing instruction is received.

16. An electronic device comprising a camera module, a display screen, and image processing circuitry, the image processing circuitry being connected to the camera module and the display screen, respectively, the image processing circuitry being configured as the image processing circuitry of any of claims 6-10, or as the image processing circuitry of any of claims 11-15.