CN115632856B - Verification system and verification method - Google Patents
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- CN115632856B CN115632856B CN202211288430.9A CN202211288430A CN115632856B CN 115632856 B CN115632856 B CN 115632856B CN 202211288430 A CN202211288430 A CN 202211288430A CN 115632856 B CN115632856 B CN 115632856B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/08—Network architectures or network communication protocols for network security for authentication of entities
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- H—ELECTRICITY
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- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/20—Network architectures or network communication protocols for network security for managing network security; network security policies in general
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The application provides a verification system and a verification method, wherein the verification system comprises a control layer, a data receiving and transmitting layer and a result comparison layer, the data receiving and transmitting layer comprises an auxiliary test component and a storage unit component, after an interface of the auxiliary test component is connected with the test component, the control layer writes original data into the storage unit component, the test component reads the original data of the storage unit component through the auxiliary test component, and the test component writes first result data obtained by calculation according to the original data into the storage unit component through the auxiliary test component. The result comparison layer is used for implanting a reference module, such as an ESL model, and the reference module can calculate second result data according to the original data, so that consistency comparison is carried out according to the first result data and the second result data, and a verification result is output after the comparison is completed. The verification system can be accessed to a test component to be verified and a corresponding reference model is implanted, so that comprehensive multiplexing of the verification structure in a specific scene is completed.
Description
Technical Field
The application relates to the technical field of verification, in particular to a verification system and a verification method.
Background
Verification platforms built based on System Verilog language+UVM verification methodology have become the mainstream of technology in the field of digital chip verification at present. On the one hand, the System Verilog language is compatible with the advantages of the hardware language description of Verilog, and meanwhile, the object-oriented and generic programming concepts in the C++ software ideas are absorbed, so that the System Verilog can be used as hardware design and can be used for software engineering. Compared with C++, the System Verilog is greatly enhanced on the random constraint level, and the randomization capability required by chip verification is improved. The reusable and standardized verification structural members are defined in the UVM standard library, verification environments built by different engineers are unified to a certain extent in style in a standard verification structural member mode, the development efficiency of the verification environments is improved, and the difficulty in building the verification environments is reduced.
UVM is a general verification methodology and verification environments built by different engineers can vary widely, and UVM does not provide a verification structure for a specific scenario. The verification structure in the specific scene is usually basically fixed, so that a unified verification structure based on the specific scene can be provided, so that the verification structure in the specific scene can be comprehensively multiplexed.
However, the existing verification environment has low expansibility, so that the verification environment is difficult to adapt to the change of the demand in the later period of project development, and the verification environment needs to be reconstructed.
Disclosure of Invention
The embodiment of the application aims to provide a verification system and a verification method, which are used for solving the problems that the existing verification environment is low in expansibility, so that the verification environment is difficult to adapt to the change of the requirement in the later period of project development, and the verification environment needs to be reconstructed.
The verification system comprises a control layer, a data receiving and transmitting layer and a result comparison layer;
the data receiving and transmitting layer comprises at least one auxiliary test component and at least one storage unit component; the auxiliary test assembly is used for being connected with the test assembly through an interface, and the test assembly is configured to be connected with at least one design module to be verified;
the control layer is used for writing the original data into the storage unit assembly;
the test assembly is used for reading the original data from the storage unit assembly through the auxiliary test assembly; calculating the original data to obtain first result data, and writing the first result data into the storage unit component through the auxiliary test component;
the result comparison layer is used for acquiring the original data in the storage unit assembly, calculating the original data by utilizing a reference model module of the result comparison layer, and obtaining second result data; the reference model module is used for implanting a reference model corresponding to the test component;
the result comparison layer is also used for comparing the first result data with the second result data and outputting a verification result after the comparison is completed.
In the above technical scheme, the verification system comprises a control layer, a data receiving and transmitting layer and a result comparison layer, wherein the data receiving and transmitting layer comprises an auxiliary test component and a storage unit component, after an interface of the auxiliary test component is connected with the test component, the control layer writes original data into the storage unit component, the test component reads the original data of the storage unit component through the auxiliary test component, and the test component writes first result data obtained by calculation according to the original data into the storage unit component through the auxiliary test component. The result comparison layer is used for implanting a reference module, such as an ESL model, and the reference module can calculate second result data according to the original data, so that consistency comparison is carried out according to the first result data and the second result data, and a verification result is output after the comparison is completed. The verification system can be connected with a test component to be verified and is implanted with a corresponding reference model, so that comprehensive multiplexing of a verification structure in a specific scene is completed.
Each component of the data receiving and transmitting layer is responsible for realizing the functions of data reading, calculating and data writing. The design module (RTL) reads the original data from the storage unit assembly through the auxiliary test assembly, and writes the first result data into the storage unit assembly through the auxiliary test assembly after the calculation is finished, so that the reading, calculation and writing of the data are realized once.
In some alternative embodiments, the control layer includes: a master control component and a register model module;
the main control assembly is used for:
the control register model module configures registers of the design module;
writing the original data into the storage unit assembly;
the control reference model module calculates the raw data.
In the above technical solution, the control layer mainly plays a role of scheduling, controls the execution sequence of the overall simulation, firstly, the main control component writes the original data into the storage unit component, then, the configuration of the register is performed, the read, calculate and write functions of the design module (RTL) are started through the configuration register, after the design module finishes data operation and writes out data, the main control component sends a memory copy instruction, copies the data from the System Verilog memory to the c++ memory for use by a reference model (such as an ESL model), and after the reference model finishes calculation and output, the main control component starts the bisection model to perform result comparison.
In some alternative embodiments, the result alignment layer comprises: the storage unit component copy module, the bisection model module and the reference model module;
the main control component is also used for controlling the storage unit component copy module and the bisection model module to start working;
the storage unit component copying module is used for copying the original data from the storage unit component in the first language to the storage unit component in the second language so as to provide the original data for the reference model module; copying the first result data from the memory cell assembly in the first language to the memory cell assembly in the second language for use by the split model module;
the bisection model module is used for comparing the first result data with the second result data, and outputting a verification result after the comparison is completed.
In the above technical solution, the result comparison layer function is to perform result comparison on the first result data output by the test component and the second result data output by the reference model module.
In some alternative embodiments, the storage unit assembly copy module includes at least one of a DPI interface, a PLI interface, and a VPI interface.
In the above technical solution, the DPI (Direct Programming Interface) interface is an interface called by the System Verilog and other programming languages, especially the C/c++. Through the DPI interface, the C function can be conveniently called in the System Verilog program, and the System Verilog function can be called in the C program. In addition, the interface between Verilog and C language is PLI (Verilog Programming Language Interface) interface and VPI (Verilog Procedural Interface) interface.
In some alternative embodiments, the test assembly includes n design modules, n being a positive integer greater than 1; the first design module and the n design module comprise at least one universal standard interface or custom interface for connecting with the auxiliary test assembly, and the n design modules are connected through an internal interface.
In the above technical scheme, the test assembly includes n design modules, the design module of the outermost layer of the test assembly is the first design module and the nth design module, the outermost layer design module is used for being connected with the auxiliary test assembly, and the interface between the outermost layer design module and the auxiliary test assembly is designed to at least include a universal standard interface or a custom interface, so as to ensure the expansibility of the verification system.
In some alternative embodiments, the test assembly includes a single design module; the single design module includes at least one generic standard interface or custom interface for interfacing with the auxiliary test component.
In the above technical solution, the test component is a single design module, and the single design module is used for being connected with the auxiliary test component, and the interface between the single design module and the auxiliary test component is designed to at least include a universal standard interface or a custom interface, so as to ensure the expansibility of the verification system.
In some alternative embodiments, the control layer further comprises:
and the simulation starting component is used for starting the main control component.
The verification method provided by the embodiment of the application comprises the following steps:
building a verification system as described above;
taking the chip design module as a test component and accessing the test component into a verification system through an interface;
implanting a reference model into a reference model module of the verification system;
simulation is performed using a verification system that includes a chip design module and a reference model.
In the technical scheme, the built verification system is a verification structure of a high-expansion implantable reference model with three abstract layers, the verification structure provides a fixed verification environment structure in a scene of implanting an ESL model in a UVM environment, the test assembly is connected to the verification structure and the reference model is implanted, so that comprehensive multiplexing of the verification structure in a specific scene is completed, and horizontal multiplexing and vertical multiplexing among similar projects can be realized by the method.
In some alternative embodiments, the verification method further comprises setting the number of storage unit assemblies and auxiliary test assemblies at the time of building the verification system.
In the above technical solution, the built verification system supports one or more storage single components to store the original data, the first result data and the second result data.
In some alternative embodiments, the simulation is performed using a verification system comprising a chip design module and a reference model, comprising:
transmitting a verification system comprising a chip design module and a reference model to a hardware accelerator;
and running the hardware accelerator, and generating a chip simulation report when the running is finished.
An electronic device provided in an embodiment of the present application includes: a processor and a memory storing machine-readable instructions executable by the processor, which when executed by the processor, perform a method as any one of the above.
A computer readable storage medium provided by an embodiment of the present application, on which a computer program is stored, which when executed by a processor performs a method as described in any of the above.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a functional module of an authentication system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of functional modules of an authentication system according to another embodiment of the present application;
FIG. 3 is a flowchart illustrating steps of a verification method according to an embodiment of the present application;
fig. 4 is a schematic diagram of a possible structure of an electronic device according to an embodiment of the present application.
Icon: 1-control layer, 2-data transceiver layer, 21-memory cell assembly, 22-auxiliary test assembly, 23-test assembly, 3-result comparison layer, 41-processor, 42-memory, 43-communication interface, 44-communication bus.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Referring to fig. 1, fig. 1 is a schematic diagram of functional modules of an authentication system according to an embodiment of the present application, including a control layer 1, a data transceiver layer 2, and a result comparison layer 3.
Wherein the data transceiver layer 2 comprises at least one auxiliary test component 22 and at least one storage unit component 21; wherein the auxiliary test assembly 22 is configured to interface with the test assembly 23, and the test assembly 23 is configured to interface with at least one design module to be verified. The control layer 1 is used to write raw data to the memory cell assembly 21. The test assembly 23 is used for reading the original data from the storage unit assembly 21 through the auxiliary test assembly 22; the raw data is calculated and first result data is obtained, and the first result data is written into the memory cell assembly 21 through the auxiliary test assembly 22. The result comparison layer 3 is used for acquiring the original data in the storage unit assembly 21, calculating the original data by utilizing a reference model module of the result comparison layer 3, and obtaining second result data; wherein the reference model module is for implanting a reference model corresponding to the test assembly 23. The result comparison layer 3 is further configured to compare the first result data with the second result data, and output a verification result after the comparison is completed.
In this embodiment, the verification system includes a control layer 1, a data transceiver layer 2 and a result comparison layer 3, where the data transceiver layer 2 includes an auxiliary test component 22 and a storage unit component 21, after an interface of the auxiliary test component 22 is connected with a test component 23, the control layer 1 writes original data into the storage unit component 21, the test component 23 reads the original data of the storage unit component 21 through the auxiliary test component 22, and the test component 23 calculates first result data according to the original data and writes the first result data into the storage unit component 21 through the auxiliary test component 22. The result comparison layer 3 is used for implanting a reference module, such as an ESL model, and the reference module can calculate second result data according to the original data, so that consistency comparison is carried out according to the first result data and the second result data, and a verification result is output after the comparison is completed. The verification system can be connected with the test assembly 23 to be verified and is implanted with a corresponding reference model, so that comprehensive multiplexing of the verification structure in a specific scene is completed.
Wherein, each component of the data receiving and transmitting layer 2 is responsible for realizing the functions of data reading, calculating and data writing. The design module (RTL) reads the original data from the storage unit assembly 21 through the auxiliary test assembly 22, and writes the first result data into the storage unit assembly 21 through the auxiliary test assembly 22 after the calculation is completed, so that the reading, calculation and writing of the data are realized once.
Referring to fig. 2, fig. 2 is a schematic functional block diagram of an authentication system according to another embodiment of the present application. In this embodiment, the control layer 1 includes: a master control component and a register model module.
Correspondingly, the main control component is used for: the control register model module configures registers of the design module; writing the original data to the memory cell assembly 21; the control reference model module calculates the raw data.
In this embodiment of the present application, the control layer 1 mainly plays a role of scheduling, controls the execution sequence of the overall simulation, firstly, the main control component writes the original data into the storage unit component 21, then performs the configuration of the register, starts the reading, calculating and writing functions of the design module (RTL) through the configuration register, after the design module completes the data operation and writes out the data, the main control component sends a memory copy instruction, copies the data from the System Verilog memory to the c++ memory for use by a reference model (such as an ESL model), and after the reference model completes the calculation and output, the main control component starts the bisection model to perform the result comparison.
In some alternative embodiments, the result alignment layer 3 comprises: the system comprises a storage unit component copying module, a bisection model module and a reference model module. The main control component is also used for controlling the storage unit component copying module and the bisection model module to start working. The storage unit assembly copying module is used for copying the original data from the storage unit assembly 21 in the first language to the storage unit assembly 21 in the second language so as to provide the original data for the reference model module to use; the first result data is copied from the memory cell assembly 21 in the first language to the memory cell assembly 21 in the second language for use by the split model module. The bisection model module is used for comparing the first result data with the second result data, outputting a verification result after the comparison is completed, if the first result data and the second result data are consistent, the verification is passed, and if the first result data and the second result data are inconsistent, the verification is not passed.
In this embodiment, the result comparison layer 3 is configured to perform result comparison on the first result data output by the test component 23 and the second result data output by the reference model module. For example, the reference model is an ESL model, and because the ESL model is generally realized by adopting a C++ language, the components of the result comparison layer 3 are uniformly constructed by adopting a C++, and the interaction between the System Verilog and the C++ uses a storage unit component copy module; the storage unit component copying module copies the original data from the System Verilog memory to the C++ memory for the ESL model to calculate, the ESL model completes calculation and writes out a result, and the bisection model compares the first result data with the second result data output by the ESL model.
In some alternative embodiments, the storage unit assembly copy module includes at least one of a DPI interface, a PLI interface, and a VPI interface.
In the embodiment of the application, the DPI (Direct Programming Interface) interface is an interface called by the System Verilog and other programming languages, in particular, C/C++. Through the DPI interface, the C function can be conveniently called in the System Verilog program, and the System Verilog function can be called in the C program. In addition, the interface between Verilog and C language is PLI (Verilog Programming Language Interface) interface and VPI (Verilog Procedural Interface) interface.
In some alternative embodiments, the test assembly 23 includes n design modules, n being a positive integer greater than 1; the first design module and the n design module include at least one universal standard interface or custom interface for connecting with the auxiliary test assembly 22, and the n design modules are connected through internal interfaces.
In this embodiment, the test component 23 includes n design modules, and the design module of the outermost layer of the test component 23, that is, the first design module and the n design module, is used for being connected with the auxiliary test component 22, and designs the interface between the outermost layer design module and the auxiliary test component 22 to at least include a universal standard interface or a custom interface, so as to ensure the expansibility of the verification system.
It should be noted that in some embodiments, the test assembly 23 may also be a single design module; the single design module includes at least one generic standard interface or custom interface for interfacing with the auxiliary test component 22.
In this embodiment, the test module 23 is a single design module, and the single design module is used for connecting with the auxiliary test module 22, and the interface between the single design module and the auxiliary test module 22 is designed to at least include a universal standard interface or a custom interface, so as to ensure the expansibility of the verification system.
In some alternative embodiments, the control layer 1 further comprises: and the simulation starting component is used for starting the main control component.
In this embodiment, the workflow of the verification system shown in fig. 2 is specifically as follows:
first, the simulation start component controls the main control component to start. The main control component plays a role in scheduling each module and controls the sequence of overall simulation.
The main control unit writes the original data to one or more memories Mem (i.e., the memory cell unit 21).
The main control module performs configuration of a register of a design module (RTL) in the test module 23 through a register model module, and starts reading, calculating and writing functions of the design module (RTL) through the configuration register. The test assembly 23 of the present embodiment includes three design modules connected by internal interfaces.
The configured test component 23 reads the raw data in the one or more memories Mem through the auxiliary test component 22. And calculating to obtain first result data according to the original data by utilizing the calculation function of the design module to be verified. The test component 23 then writes the first result data into one or more memories Mem through the auxiliary test component 22.
In this embodiment, the reference model module adopts an ESL model, and the main control component controls the storage unit component copy module to copy the original data from the System Verilog memory to the c++ memory for use in computation of the ESL model, and copy the first result data from the System Verilog memory to the c++ memory for use in the bisection model module. In this embodiment, system Verilog and c++ interactions use DPI.
The main control component controls ESL model calculation of the reference model module, namely, second result data is obtained by using ESL model calculation according to the original data in the C++ memory.
And uniformly constructing the components of the result comparison layer 3 by adopting C++, and comparing and analyzing the first result data and the second result data to obtain a verification result.
Therefore, the verification system of the embodiment is a verification structure of a high-expansion implantable ESL based on three abstract layers, which provides a fixed verification environment structure under the condition that the ESL is implanted in a UVM environment, and provides a simple, fixed and reliable verification environment building template for the special scene. In addition, the verification structure is explicitly layered, a three-abstract-layer verification structure is provided, further decoupling among the control layer 1, the data receiving and transmitting layer 2 and the result comparison layer 3 is achieved, the verification environment is clearer, and maintainability is improved. The verification structure has extremely strong expandability in a specific scene, and is convenient for horizontal multiplexing and vertical multiplexing among similar projects.
More, the verification system of the embodiment supports the outermost design module to adopt 1 or more universal standard interfaces or custom interfaces, supports the embedding of single or multiple identical or different design modules for verification, and supports the use of one or more memories for storing data.
Referring to fig. 3, fig. 3 is a flowchart of steps of a verification method according to an embodiment of the present application, including:
step 100, building a verification system according to any one of the above steps;
step 200, taking a chip design module as a test component 23, and accessing the test component into a verification system through an interface;
step 300, implanting a reference model into a reference model module of the verification system;
step 400, performing simulation by using a verification system comprising a chip design module and a reference model.
In the embodiment of the application, the built verification system is a verification structure of a high-expansion implantable reference model with three abstract layers, the verification structure provides a fixed verification environment structure under the condition that an ESL model is required to be implanted in a UVM environment, the test assembly 23 is connected to the verification structure, the reference model is implanted, and therefore comprehensive multiplexing of the verification structure under a specific scene is completed, and horizontal multiplexing and vertical multiplexing among similar projects can be achieved through the method.
In some alternative embodiments, the verification method further comprises setting the number of storage unit assemblies 21 and auxiliary test assemblies 22 when the verification system is set up. In the embodiment of the application, the built verification system supports one or more storage single components for storing the original data, the first result data and the second result data.
In some alternative embodiments, the simulation is performed using a verification system comprising a chip design module and a reference model, comprising: transmitting a verification system comprising a chip design module and a reference model to a hardware accelerator; and running the hardware accelerator, and generating a chip simulation report when the running is finished.
Fig. 4 shows a possible structure of the electronic device provided in the embodiment of the present application. Referring to fig. 4, the electronic device includes: processor 41, memory 42, and communication interface 43, which are interconnected and communicate with each other by a communication bus 44 and/or other forms of connection mechanisms (not shown).
The Memory 42 includes one or more (Only one is shown in the figure), which may be, but is not limited to, a random access Memory (Random Access Memory, RAM), a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable programmable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable programmable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), and the like. The processor 41 and possibly other components may access the memory 42, read and/or write data therein.
The processor 41 comprises one or more (only one shown) which may be an integrated circuit chip having signal processing capabilities. The processor 41 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a micro control unit (Micro Controller Unit, MCU), a network processor (Network Processor, NP), or other conventional processor; but may also be a special purpose processor including a Neural Network Processor (NPU), a graphics processor (Graphics Processing Unit GPU), a digital signal processor (Digital Signal Processor DSP), an application specific integrated circuit (Application Specific Integrated Circuits ASIC), a field programmable gate array (Field Programmable Gate Array FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. Also, when the number of processors 41 is plural, some of them may be general-purpose processors, and the other may be special-purpose processors.
The communication interface 43 includes one or more (only one shown) that may be used to communicate directly or indirectly with other devices for data interaction. Communication interface 43 may include an interface for wired and/or wireless communication.
One or more computer program instructions may be stored in memory 42 that may be read and executed by processor 41 to implement the verification methods provided by embodiments of the present application.
It will be appreciated that the configuration shown in fig. 4 is merely illustrative, and that the electronic device may also include more or fewer components than shown in fig. 4, or have a different configuration than shown in fig. 4. The components shown in fig. 4 may be implemented in hardware, software, or a combination thereof. The electronic device may be a physical device such as a PC, a notebook, a tablet, a cell phone, a server, an embedded device, etc., or may be a virtual device such as a virtual machine, a virtualized container, etc. The electronic device is not limited to a single device, and may be a combination of a plurality of devices or a cluster of a large number of devices.
The embodiment of the application also provides a computer readable storage medium, and the computer readable storage medium stores computer program instructions, which when read and run by a processor of a computer, execute the verification method provided by the embodiment of the application. For example, the computer readable storage medium may be implemented as memory 42 in the electronic device of FIG. 4.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (8)
1. The verification system is characterized by comprising a control layer, a data receiving and transmitting layer and a result comparison layer;
the data receiving and transmitting layer comprises at least one auxiliary test component and at least one storage unit component; the auxiliary test assembly is used for being connected with the test assembly through an interface, and the test assembly is configured to be connected with at least one design module to be verified;
the control layer is used for writing original data into the storage unit component; the control layer includes: a master control component and a register model module; the main control assembly is used for: controlling the register model module to configure registers of the design module; writing the original data to the storage unit assembly; the control reference model module calculates the original data;
the test assembly is used for reading the original data from the storage unit assembly through the auxiliary test assembly; calculating the original data to obtain first result data, and writing the first result data into the storage unit component through the auxiliary test component;
the result comparison layer is used for acquiring the original data in the storage unit assembly, calculating the original data by utilizing a reference model module of the result comparison layer, and obtaining second result data; wherein the reference model module is used for implanting a reference model corresponding to the test component;
the result comparison layer is also used for comparing the first result data with the second result data and outputting a verification result after the comparison is completed; the result comparison layer comprises: a storage unit component copy module, a bisection model module and the reference model module; the main control component is also used for controlling the storage unit component copy module and the bisection model module to start working; the storage unit component copying module is used for copying the original data from the storage unit component in the first language to the storage unit component in the second language so as to provide the original data for the reference model module; copying the first result data from the memory cell assembly in the first language to the memory cell assembly in the second language for use by the split model module; the bisection model module is used for comparing the first result data with the second result data, and outputting a verification result after the comparison is completed.
2. The system of claim 1, wherein the storage unit assembly copy module comprises at least one of a DPI interface, a PLI interface, and a VPI interface.
3. The system of claim 1, wherein the test assembly comprises n design modules, n being a positive integer greater than 1; the first design module and the n design module comprise at least one universal standard interface or custom interface for connecting with the auxiliary test assembly, and the n design modules are connected through an internal interface.
4. The system of claim 1, wherein the test assembly comprises a single design module; the single design module includes at least one universal standard interface or custom interface for interfacing with the auxiliary test component.
5. The system of claim 1, wherein the control layer further comprises:
and the simulation starting component is used for starting the main control component.
6. A verification method, characterized in that the verification method is implemented based on a verification system according to any one of claims 1-5, the method comprising:
taking the chip design module as a test component of the verification system, and accessing the chip design module into the verification system through an interface;
implanting a reference model into a reference model module of the verification system;
and performing simulation by using a verification system comprising the chip design module and a reference model.
7. The method of verification of claim 6, further comprising setting the number of memory cell components and auxiliary test components when the verification system is built.
8. The method of verification of claim 7, wherein the simulating using a verification system including the chip design module and a reference model comprises:
transmitting a verification system comprising a chip design module and a reference model to a hardware accelerator; and operating the hardware accelerator, and generating a chip simulation report when the operation is finished.
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