CN115632628A - Filter structure and manufacturing method thereof, filter chip and electronic equipment - Google Patents
Filter structure and manufacturing method thereof, filter chip and electronic equipment Download PDFInfo
- Publication number
- CN115632628A CN115632628A CN202211213857.2A CN202211213857A CN115632628A CN 115632628 A CN115632628 A CN 115632628A CN 202211213857 A CN202211213857 A CN 202211213857A CN 115632628 A CN115632628 A CN 115632628A
- Authority
- CN
- China
- Prior art keywords
- conductive layer
- conductive
- filter structure
- filter
- peripheral side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02535—Details of surface acoustic wave devices
- H03H9/02543—Characteristics of substrate, e.g. cutting angles
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02535—Details of surface acoustic wave devices
- H03H9/02637—Details concerning reflective or coupling arrays
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/64—Filters using surface acoustic waves
Abstract
The application provides a filter structure, and the filter structure includes the piezoelectric wafer, and the piezoelectric wafer includes relative first surface and the second surface that sets up and connects the week side between first surface and the second surface. The filter structure further comprises a first conducting layer, a second conducting layer and a conducting pattern, wherein the first conducting layer is arranged on the first surface, and the second conducting layer is arranged on the peripheral side face and is connected with the first conducting layer. The conductive pattern is arranged on the second surface and is electrically connected with the second conductive layer. The first conductive layer and the second conductive layer are used for leading out the charges gathered on the conductive pattern through the wafer bearing platform in contact with the first conductive layer, and electrostatic damage to the conductive pattern in the process of manufacturing the filter is avoided. The application also provides a manufacturing method of the filter structure, a filter chip and electronic equipment.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a filter structure, a method for manufacturing the filter structure, a filter chip, and an electronic device having the filter chip.
Background
A surface acoustic wave filter is an electronic device made of a piezoelectric material, and the surface acoustic wave filter can process an acoustic signal propagating on the surface of the piezoelectric material. The surface acoustic wave filter has the advantages of low cost, small volume, multiple functions and the like, so that the surface acoustic wave filter is widely applied to the fields of radar, communication, navigation, identification and the like.
Along with the development of the surface acoustic wave filter towards high frequency and miniaturization, the surface acoustic wave filter is smaller and smaller in size, and the electrostatic damage risk is higher and higher, so that higher requirements are provided for electrostatic elimination in the manufacturing process of the surface acoustic wave filter.
Therefore, how to eliminate the static electricity in the process of manufacturing the surface acoustic wave filter is an urgent problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, it is an object of the present application to provide a filter structure, a method of manufacturing the filter structure, a filter chip and an electronic device having the filter chip, which are intended to eliminate static electricity during the manufacturing process of a surface acoustic wave filter.
In order to solve the above technical problem, the present application provides a filter structure, the filter structure includes a piezoelectric wafer, the piezoelectric wafer includes a first surface and a second surface that are arranged oppositely and a peripheral side surface connected between the first surface and the second surface. The filter structure further comprises a first conducting layer, a second conducting layer and a conducting pattern, wherein the first conducting layer is arranged on the first surface, the second conducting layer is arranged on the peripheral side face and is connected with the first conducting layer, and the conducting pattern is arranged on the second surface and is electrically connected with the second conducting layer. The first conductive layer and the second conductive layer are used for leading out the charges gathered on the conductive pattern through the wafer bearing platform in contact with the first conductive layer.
To sum up, piezoelectric wafer, first conducting layer, second conducting layer and conducting pattern that this application embodiment provided, first conducting layer with the second conducting layer be used for will assemble in electric charge on the conducting pattern is derived through with the wafer bearing platform that first conducting layer contacted, has avoided the in-process static damage conducting pattern of making the wave filter.
In an exemplary embodiment, the first conductive layer is disposed over the first surface; or, the first conducting layer is arranged on part of the first surface.
In an exemplary embodiment, the first conductive layer includes a plurality of first conductive segments spaced apart from and disposed on a portion of the first surface.
In an exemplary embodiment, the second conductive layer is provided around the peripheral side surface; or, the second conductive layer is disposed on a portion of the peripheral side surface.
In an exemplary embodiment, the second conductive layer includes a plurality of second conductive segments spaced apart on a portion of the peripheral side surface.
In an exemplary embodiment, the first conductive layer has a thickness of 50nm to 1000nm; and/or the thickness of the second conducting layer is 50nm to 1000nm.
In an exemplary embodiment, the first conductive layer is integrally formed with the second conductive layer.
In an exemplary embodiment, the conductive pattern includes an interdigital transducer, a pad, and a trace, and the second conductive layer is electrically connected to at least one of the interdigital transducer, the pad, and the trace.
In an exemplary embodiment, the filter chip further includes a third conductive layer disposed on the second surface, one side of the third conductive layer is connected to the second conductive layer, and the other side of the third conductive layer is connected to at least one of the interdigital transducer, the bonding pad, and the trace.
In an exemplary embodiment, the third conductive layer is provided around a peripheral side of the conductive pattern; or, the third conductive layer is arranged on the partial periphery of the conductive pattern.
In an exemplary embodiment, the third conductive layer includes a plurality of third conductive segments, and the plurality of third conductive segments are disposed at intervals on a peripheral side of the conductive pattern.
Based on the same inventive concept, the present application further provides a method for manufacturing a filter structure, wherein the method for manufacturing a filter is applied to a piezoelectric wafer, the piezoelectric wafer includes a first surface and a second surface which are oppositely arranged, and a peripheral side surface connected to the first surface and the second surface, and the method includes:
forming a first conductive layer on the first surface, wherein the first conductive layer is in contact with a wafer bearing platform;
forming a second conductive layer on the peripheral side, wherein the second conductive layer is connected to the first conductive layer;
forming a conductive pattern on the second surface, wherein the conductive pattern is electrically connected to the second conductive layer.
In summary, the method for manufacturing a filter provided by the embodiment of the present application is applied to a piezoelectric wafer, where the piezoelectric wafer includes a first surface and a second surface that are oppositely disposed, and a peripheral side surface connected to the first surface and the second surface, and the method includes: forming a first conductive layer on the first surface, wherein the first conductive layer is used for contacting with a wafer bearing table; forming a second conductive layer on the peripheral side, wherein the second conductive layer is connected to the first conductive layer; forming a conductive pattern on the second surface, wherein the conductive pattern is electrically connected to the second conductive layer. Therefore, the first conductive layer and the second conductive layer are used for leading out the charges gathered on the conductive pattern through the bearing platform in contact with the first conductive layer, and the conductive pattern is prevented from being damaged by static electricity in the process of manufacturing the filter.
In an exemplary embodiment, the first conductive layer is formed on the first surface by a sputtering process; and/or forming the second conductive layer on the peripheral side surface by a sputtering process.
In an exemplary embodiment, the first conductive layer and the second conductive layer are integrally formed through a sputtering process.
In an exemplary embodiment, an angle between a sputtering direction of the sputtering process for forming the first conductive layer and the second conductive layer and a normal line of the piezoelectric wafer is 30 to 60 degrees.
Based on the same inventive concept, the embodiment of the present application further provides a filter chip, where the filter chip includes at least one filter formed by cutting the filter structure prepared by the above method.
In summary, the filter chip provided by the embodiments of the present application includes at least one filter formed by cutting a filter structure prepared by a filter manufacturing method. Therefore, the filter structure can lead out the charges gathered on the conductive pattern through the first conductive layer and the second conductive layer through the wafer bearing table in contact with the first conductive layer, and avoids electrostatic damage to the conductive pattern in the process of manufacturing the filter. Moreover, the conductive pattern of the filter structure formed by the filter preparation method is not damaged, so that the quality and the product integrity of the filter chip are ensured, and the service life of the filter chip is prolonged.
Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which includes at least one filter chip as described above.
In summary, the electronic device provided by the embodiment of the present application includes at least one filter chip as described above, where the filter chip includes at least one filter formed by cutting a filter structure prepared by a filter manufacturing method. Therefore, the filter structure can lead out the charges gathered on the conductive pattern through the first conductive layer and the second conductive layer through the wafer bearing table in contact with the first conductive layer, and avoids electrostatic damage to the conductive pattern in the process of manufacturing the filter. Moreover, the conductive pattern of the filter structure formed by the filter preparation method is not damaged, so that the quality and the product integrity of the filter chip are ensured, and the service life of the filter chip is prolonged.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic perspective view of a filter structure disclosed in an embodiment of the present application;
FIG. 2 is a schematic bottom view of the filter structure of FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along line III-III of the filter structure shown in FIG. 1;
fig. 4 is a schematic flowchart of a method for manufacturing a filter structure according to an embodiment of the present disclosure;
fig. 5 is a schematic sputtering direction diagram of a manufacturing method of a filter structure disclosed in the embodiment of the present application.
Description of the reference numerals:
1-a filter structure; 10-a piezoelectric wafer; 11-a first surface; 13-a second surface; 15-peripheral flank; 30-a first conductive layer; 31-a first conductive segment; 50-a second conductive layer; 51-a second conductive segment; 70-a conductive pattern; 71-interdigital transducers; 73-a pad; 75-routing; 90-a third conductive layer; 91-a third conductive segment; S10-S30-filter structure manufacturing method.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments in which the application may be practiced. The ordinal numbers used herein for the components, such as "first," "second," etc., are used merely to distinguish between the objects described, and do not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). Directional phrases used in this application, such as, for example, "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings and are, therefore, used herein for better and clearer illustration and understanding of the application and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the application.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art. It should be noted that the terms "first", "second", and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprises," "comprising," "includes," "including," or "can include" when used in this application, specify the presence of stated features, operations, elements, and the like, and do not limit one or more other features, operations, elements, and the like. Furthermore, the terms "comprises" or "comprising" indicate the presence of the respective features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and are intended to cover non-exclusive inclusions. It is also to be understood that the meaning of "at least one" as described herein is one and more than one, such as one, two or three, etc., and the meaning of "a plurality" is at least two, such as two or three, etc., unless explicitly specified otherwise.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
As surface acoustic wave filters in electronic devices are increasingly miniaturized, the risk of electrostatic damage to the surface acoustic wave filters is also increasing during the manufacturing process of the surface acoustic wave filters. Therefore, the electrostatic charge on the surface acoustic wave filter is discharged in the process of manufacturing and forming the surface acoustic wave filter. In order to solve the above problem, an electrostatic discharge jig is generally used for conducting electricity, and electric charges are conducted by contacting a contact point on the electrostatic discharge jig with a conductive pattern of a surface acoustic wave filter. However, the electrostatic discharge jig described above is complicated to manufacture and high in processing cost, and the electrostatic discharge jig may damage the conductive pattern of the surface acoustic wave filter in the process of holding the conductive pattern.
Referring to fig. 1 to 3, fig. 1 is a schematic perspective view of a filter structure disclosed in an embodiment of the present application, fig. 2 is a schematic bottom view of the filter structure shown in fig. 1, and fig. 3 is a schematic cross-sectional view of the filter structure shown in fig. 1 along III-III. The filter structure 1 provided by the embodiment of the present application may include at least a piezoelectric wafer 10, a first conductive layer 30, and a second conductive layer 50. The piezoelectric wafer 10 includes a first surface 11 and a second surface 13 disposed opposite to each other, and a peripheral side surface 15 connected between the first surface 11 and the second surface 13, the first conductive layer 30 is disposed on the first surface 11, and the second conductive layer 50 is disposed on the peripheral side surface 15 and connected to the first conductive layer 30. The filter structure 1 further comprises a conductive pattern 70, wherein the conductive pattern 70 is disposed on the second surface 13 and electrically connected to the second conductive layer 50. The first conductive layer 30 and the second conductive layer 50 are used for guiding out the charges collected on the conductive pattern 70 through a stage in contact with the first conductive layer 30. Specifically, a ground line is provided on the stage, the ground line is connected to a ground terminal, and the charge on the conductive pattern 70 is led out through the second conductive layer 50, the first conductive layer 30, and the ground line of the stage.
In an exemplary embodiment, the stage does not belong to the filter structure 1, and the piezoelectric wafer 10 is placed on the stage when the filter structure 1 is formed.
In summary, the filter structure 1 provided in the embodiment of the present application includes a piezoelectric wafer 10, a first conductive layer 30, and a second conductive layer 50. The piezoelectric wafer 10 includes a first surface 11 and a second surface 13 which are oppositely disposed and a peripheral side surface 15 connected between the first surface 11 and the second surface 13, the first conductive layer 30 is disposed on the first surface 11, the second conductive layer 50 is disposed on the peripheral side surface 15 and connected to the first conductive layer 30. The filter structure 1 further comprises a conductive pattern 70, wherein the conductive pattern 70 is disposed on the second surface 13 and electrically connected to the second conductive layer 50. Therefore, the filter structure 1 can lead out the charges accumulated on the conductive pattern 70 through the first conductive layer 30 and the second conductive layer 50 through the stage contacting with the first conductive layer 30, thereby avoiding electrostatic damage to the conductive pattern 70 during the filter manufacturing process.
In the present embodiment, the first conductive layer 30 is disposed on the first surface 11, that is, the peripheral side of the surface of the first conductive layer 30 facing the first surface 11 is flush with the peripheral side of the first surface 11, or the peripheral side of the surface of the first conductive layer 30 facing the first surface 11 extends beyond the peripheral side of the first surface 11.
In an exemplary embodiment, the first conductive layer 30 is disposed on a portion of the first surface 11, i.e., the first conductive layer 30 does not completely cover the first surface 11.
In the embodiment of the present application, the first conductive layer 30 includes a plurality of first conductive segments 31, and the first conductive segments 31 are disposed at intervals on a portion of the first surface 11. The first conductive segments 31 may be distributed in a scattering manner, that is, each of the first conductive segments 31 extends and diverges from the middle of the first surface 11 toward the peripheral side. The first conductive segments 31 may also be arranged in a plurality of rows and columns in a crossed manner, so that the first conductive segments 31 are in a grid shape.
In an exemplary embodiment, the number of the first conductive segments 31 may be 2 to 50, for example, 2, 10, 25, 30, 45, 50, or other numbers, which are not specifically limited in this application.
In the present embodiment, the second conductive layer 50 is disposed around the peripheral side surface 15, that is, the peripheral side surface 15 is completely covered by the second conductive layer 50.
In an exemplary embodiment, the second conductive layer 50 may also be disposed on a portion of the peripheral side surface 15, that is, a portion of the peripheral side surface 15 is covered by the second conductive layer 50, and another portion of the peripheral side surface 15 is exposed from the second conductive layer 50.
In the embodiment of the present application, the second conductive layer 50 includes a plurality of second conductive segments 51, and the second conductive segments 51 are disposed at intervals on a portion of the peripheral side surface 15.
In an exemplary embodiment, a plurality of the second conductive segments 51 are disposed on a portion of the peripheral side surface 15 at regular intervals, that is, the intervals between adjacent second conductive segments 51 may be equal, and the intervals between adjacent second conductive segments 51 may also be different.
In an exemplary embodiment, one second conductive segment 51 is connected to one first conductive segment 31, or a plurality of second conductive segments 51 are connected to one first conductive segment 31, or one second conductive segment 51 is connected to a plurality of first conductive segments 31, which is not limited in this application.
In the present embodiment, the thickness of the first conductive layer 30 is 50nm to 1000nm; and/or the thickness of the second conductive layer 50 is 50nm to 1000nm. For example, 50nm, 200nm, 500nm, 750nm, 900nm, 1000nm, or other values, which are not specifically limited by this application.
In an exemplary embodiment, the first conductive layer 30 and the second conductive layer 50 may be formed by integral molding.
In an exemplary embodiment, the conductive pattern 70 may include at least an interdigital transducer 71, a pad 73, and a trace 75 disposed on the second surface 13. The second conductive layer 50 is electrically connected to at least one of the interdigital transducer 71, the bonding pad 73, and the trace 75.
In an exemplary embodiment, the interdigital transducer 71, the pad 73, and the trace 75 may be multiple in number, which is not particularly limited in the present application.
In the present embodiment, the interdigital transducer 71 includes a first bus bar and a second bus bar that are disposed opposite to each other, a plurality of first electrode fingers, and a plurality of second electrode fingers. The plurality of first electrode fingers are connected with the first bus bar and extend towards the second bus bar, the plurality of second electrode fingers are connected with the second bus bar and extend towards the first bus bar, and the plurality of first electrode fingers and the plurality of second electrode fingers are sequentially and alternately arranged at intervals. The interdigital transducer 71 is used to convert an electric signal into an acoustic wave signal or convert an acoustic wave signal into an electric signal.
In the present embodiment, the second conductive layer 50 further includes a plurality of reflectors provided on opposite sides of the interdigital transducer 71, that is, on both ends in the longitudinal direction of the first bus bar and the second bus bar. The reflector is used for reflecting the acoustic wave signal, so that the acoustic wave signal is confined between the two reflecting structures.
In an exemplary embodiment, the interdigital transducers 71 can be electrically connected with the pads 73 through the traces 75, the interdigital transducers 71 can be electrically connected with each other through the traces 75, and the pads 73 can be electrically connected with each other through the traces 75.
In an exemplary embodiment, the number of the interdigital transducer 71, the pad 73, and the trace 75 may be multiple, and the application is not particularly limited thereto.
In an exemplary embodiment, a component indicated by reference numeral 71 in fig. 1 is used for adaptively indicating a plurality of the interdigital transducers, a component indicated by reference numeral 73 in fig. 1 is used for schematically indicating a plurality of the pads, a component indicated by reference numeral 75 in fig. 1 is used for schematically indicating a part of the trace, and the rest of the trace is disposed between a plurality of the interdigital transducers or between a plurality of the pads.
In the embodiment of the present application, the filter chip further includes a third conductive layer 90, the third conductive layer 90 is disposed on the second surface 13, one side of the third conductive layer 90 is connected to the second conductive layer 50, and the other side of the third conductive layer 90 is connected to at least one of the interdigital transducer 71, the bonding pad 73, and the trace 75.
In an exemplary embodiment, the third conductive layer 90 is disposed around the periphery of the conductive pattern 70.
In an exemplary embodiment, the third conductive layer 90 is disposed on a partial circumferential side of the conductive pattern 70.
In an exemplary embodiment, the third conductive layer 90 includes a plurality of third conductive segments 91, and the plurality of third conductive segments 91 are disposed at intervals on the peripheral side of the conductive pattern 70, i.e., the second surface 13 exposes the plurality of third conductive segments 91.
In an exemplary embodiment, one third conductive segment 91 is connected to one second conductive segment 51, or a plurality of third conductive segments 91 are connected to one second conductive segment 51, or one third conductive segment 91 is connected to a plurality of second conductive segments 51, which is not limited in this application.
In the exemplary embodiment, a plurality of the third conductive segments 91 are directed toward the conductive pattern 70 from a peripheral side of the second surface 13.
In an exemplary embodiment, the first conductive layer 30, the second conductive layer 50, and the third conductive layer 90 may be made of any one of aluminum, titanium, nickel, and chromium, or may be an alloy formed of at least any two of aluminum, titanium, nickel, and chromium.
In an exemplary embodiment, the materials of the first conductive layer 30, the second conductive layer 50, and the third conductive layer 90 may be the same or different, and the present application is not limited thereto.
In summary, the filter structure 1 provided in the embodiment of the present application includes the piezoelectric wafer 10, the first conductive layer 30, and the second conductive layer 50. The piezoelectric wafer 10 includes a first surface 11 and a second surface 13 disposed opposite to each other, and a peripheral side surface 15 connected between the first surface 11 and the second surface 13, the first conductive layer 30 is disposed on the first surface 11, and the second conductive layer 50 is disposed on the peripheral side surface 15 and connected to the first conductive layer 30. The filter structure 1 further comprises a conductive pattern 70, wherein the conductive pattern 70 is disposed on the second surface 13 and electrically connected to the second conductive layer 50. Therefore, the filter structure 1 of the present application can be used for guiding out the charges accumulated on the conductive pattern 70 through the first conductive layer 30 and the second conductive layer 50 through the stage contacting with the first conductive layer 30, thereby avoiding electrostatic damage to the conductive pattern 70 during the process of manufacturing the filter.
Based on the same inventive concept, the embodiment of the present application further provides a manufacturing method of a filter structure, where the manufacturing method is applied to a piezoelectric wafer, and the piezoelectric wafer includes a first surface 11 and a second surface 13 that are oppositely arranged, and a peripheral side surface 15 connected to the first surface 11 and the second surface 13. The manufacturing method of the filter structure of the present embodiment is similar to the descriptions of the filter structures shown in fig. 1 to fig. 3, please refer to the related descriptions of the filter structures, and the details are not repeated herein.
Referring to fig. 4, fig. 4 is a schematic flow chart illustrating a manufacturing method of a filter structure according to an embodiment of the present disclosure. The method of fabricating the waver structure includes at least:
s10, forming a first conducting layer 30 on the first surface 11, wherein the first conducting layer 30 is used for being in contact with a wafer bearing table;
specifically, the first conductive layer 30 may be formed on the first surface 11 by a sputtering process.
S20, forming a second conductive layer 50 on the peripheral side surface 15, wherein the second conductive layer 50 is connected to the first conductive layer 30;
specifically, the second conductive layer 50 may be formed on the peripheral side surface 15 by a sputtering process.
S30, forming a conductive pattern 70 on the second surface 13, wherein the conductive pattern 70 is electrically connected to the second conductive layer 50.
Specifically, the conductive pattern 70 may be formed by using a photolithography process, an electron beam evaporation process, a lift-off process, or the like.
In an exemplary embodiment, the conductive pattern 70 includes an interdigital transducer 71, a pad 73, and a trace 75 disposed on the second surface 13.
In an exemplary embodiment, the first conductive layer 30 and the second conductive layer 50 may be integrally formed through a sputtering process.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a sputtering direction of a manufacturing method of a filter structure according to an embodiment of the disclosure. In the embodiment of the present application, an angle α between a sputtering direction of the sputtering process for forming the first conductive layer 30 and the second conductive layer 50 and a normal line of the piezoelectric wafer is 30 degrees to 60 degrees, for example, 30 degrees, 40 degrees, 45 degrees, 50 degrees, 60 degrees, or other angle values, which is not particularly limited in the present application. It will be appreciated that the first conductive layer 30 is formed on the first surface 11 and the second conductive layer 50 is formed on the second surface 13 at the same time by facilitating such formation.
To sum up, the method for manufacturing a filter structure provided by the embodiment of the present application includes: forming a first conductive layer 30 on the first surface 11, the first conductive layer 30 being used for contacting with a wafer stage; forming a second conductive layer 50 on the peripheral side surface 15, wherein the second conductive layer 50 is connected to the first conductive layer 30; a conductive pattern 70 is formed on the second surface 13, wherein the conductive pattern 70 is electrically connected to the second conductive layer 50. Therefore, the first conductive layer 30 and the second conductive layer 50 can lead out the charges accumulated on the conductive pattern 70 through the stage in contact with the first conductive layer 30, thereby avoiding electrostatic damage to the conductive pattern 70 during the process of manufacturing the filter.
Based on the same inventive concept, the embodiment of the present application further provides a filter chip, where the filter chip includes at least one filter cut from the filter structure 1 prepared by the above method. Each of the filters includes a piezoelectric wafer element and a conductive sub-pattern disposed on the piezoelectric wafer element, the conductive sub-pattern being a portion of the conductive pattern 70.
It will be appreciated that the filter structure 1 is divided into a plurality of filters by a dicing process, each of the filters including a piezoelectric wafer element and a conductive subpattern disposed on the piezoelectric wafer element. And cutting the piezoelectric wafer to form a plurality of piezoelectric wafer elements, and cutting the conductive pattern to form a plurality of conductive subpatterns. The filter formed after cutting may have a portion of the first conductive layer or no portion of the first conductive layer, may have a portion of the second conductive layer or no portion of the second conductive layer, may have a portion of the third conductive layer or no portion of the third conductive layer. The number of filters formed by the cutting process is not particularly limited.
In an exemplary embodiment, at least one of the filters may be used to form the filter chip, which may further include a circuit board or the like.
In summary, the filter chip provided by the embodiment of the present application includes at least one filter formed by cutting the filter structure 1 prepared by the filter manufacturing method. The conductive pattern 70 of the filter structure 1 formed by the filter preparation method is not damaged, the quality and the product integrity of the filter chip are ensured, and the service life of the filter chip is prolonged.
Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which includes at least one filter chip as described above.
In summary, the electronic device provided by the embodiment of the present application includes at least one filter chip, where the filter chip includes at least one filter formed by cutting the filter structure 1 prepared by the filter manufacturing method. The conductive pattern 70 of the filter structure 1 formed by the filter preparation method is not damaged, the quality and the product integrity of the filter chip are ensured, and the service life of the filter chip is prolonged.
In an exemplary embodiment, the electronic device includes, but is not limited to: any electronic device or component with a PCBA board assembly, such as an LED panel, a tablet computer, a notebook computer, a navigator, a mobile phone, and an electronic watch, is not particularly limited in this application.
It is understood that the electronic device may also include an electronic device such as a Personal Digital Assistant (PDA) and/or a music player, such as a mobile phone, a tablet computer, a wearable electronic device with wireless communication function (e.g., a smart watch), and the like. The electronic device may also be other electronic apparatuses such as a Laptop computer (Laptop) with a touch sensitive surface (e.g. a touch panel) or the like. In some embodiments, the electronic device may have a communication function, that is, may establish communication with a network through a 2G (second generation mobile phone communication specification), a 3G (third generation mobile phone communication specification), a 4G (fourth generation mobile phone communication specification), a 5G (fifth generation mobile phone communication specification), a 6G (sixth generation mobile phone communication specification) or a W-LAN (wireless local area network) or a communication mode that may appear in the future. For the sake of brevity, no further limitations are imposed on this embodiment of the present application.
In the description of the present specification, reference to the description of "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that the application of the present application is not limited to the above examples, and that modifications or changes may be made by those skilled in the art based on the above description, and all such modifications and changes are intended to fall within the scope of the appended claims. Those skilled in the art will recognize that all or a portion of the above-described embodiments can be practiced without departing from the scope of the present disclosure, which is encompassed by the claims.
Claims (17)
1. A filter structure, comprising:
the piezoelectric chip comprises a first surface, a second surface and a peripheral side surface, wherein the first surface and the second surface are oppositely arranged, and the peripheral side surface is connected between the first surface and the second surface;
a first conductive layer disposed on the first surface;
the second conducting layer is arranged on the peripheral side surface and is connected with the first conducting layer;
the conductive pattern is arranged on the second surface and is electrically connected with the second conductive layer; the first conductive layer and the second conductive layer are used for leading out the electric charges gathered on the conductive patterns through the bearing platform in contact with the first conductive layer.
2. The filter structure according to claim 1, wherein the first conductive layer is disposed over the first surface; or, the first conducting layer is arranged on part of the first surface.
3. The filter structure of claim 1, wherein the first conductive layer comprises a plurality of first conductive segments spaced apart on a portion of the first surface.
4. The filter structure of claim 1, wherein the second conductive layer is disposed around the peripheral side; or, the second conductive layer is disposed on a portion of the peripheral side surface.
5. The filter structure of claim 1, wherein the second conductive layer comprises a plurality of second conductive segments spaced apart on a portion of the peripheral side surface.
6. The filter structure of claim 1, wherein the first conductive layer has a thickness of 50nm to 1000nm; and/or the thickness of the second conducting layer is 50nm to 1000nm.
7. The filter structure of claim 1, wherein the first conductive layer is integrally formed with the second conductive layer.
8. The filter structure of claim 1, wherein the conductive pattern includes an interdigital transducer, a pad, and a trace, the second conductive layer being electrically connected to at least one of the interdigital transducer, the pad, and the trace.
9. The filter structure of claim 8, further comprising a third conductive layer disposed on the second surface, one side of the third conductive layer being connected to the second conductive layer, another side of the third conductive layer being connected to at least one of the interdigital transducer, the bonding pad, and the trace.
10. The filter structure according to claim 9, wherein the third conductive layer is provided around a peripheral side of the conductive pattern; or, the third conductive layer is arranged on the partial periphery of the conductive pattern.
11. The filter structure of claim 10, wherein the third conductive layer comprises a plurality of third conductive segments, the plurality of third conductive segments being spaced apart on a peripheral side of the conductive pattern.
12. A method of fabricating a filter structure, the method being applied to a piezoelectric wafer, the piezoelectric wafer including a first surface and a second surface disposed opposite to each other and a peripheral side surface connected to the first surface and the second surface, the method comprising:
forming a first conductive layer on the first surface, the first conductive layer being in contact with a stage;
forming a second conductive layer on the peripheral side, wherein the second conductive layer is connected to the first conductive layer;
forming a conductive pattern on the second surface, wherein the conductive pattern is electrically connected to the second conductive layer.
13. The method of fabricating a filter structure according to claim 12, wherein the first conductive layer is formed on the first surface by a sputtering process; and/or forming the second conductive layer on the peripheral side surface by a sputtering process.
14. The method of claim 12, wherein the first conductive layer and the second conductive layer are integrally formed by a sputtering process.
15. The method of claim 14, wherein the sputtering direction of the sputtering process for forming the first conductive layer and the second conductive layer forms an angle of 30 to 60 degrees with the normal to the piezoelectric wafer.
16. A filter chip comprising at least one filter cut from a filter structure prepared by the method of any one of claims 12-15.
17. An electronic device comprising at least one filter chip according to claim 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211213857.2A CN115632628A (en) | 2022-09-30 | 2022-09-30 | Filter structure and manufacturing method thereof, filter chip and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211213857.2A CN115632628A (en) | 2022-09-30 | 2022-09-30 | Filter structure and manufacturing method thereof, filter chip and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115632628A true CN115632628A (en) | 2023-01-20 |
Family
ID=84904960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211213857.2A Pending CN115632628A (en) | 2022-09-30 | 2022-09-30 | Filter structure and manufacturing method thereof, filter chip and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115632628A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11163669A (en) * | 1997-09-24 | 1999-06-18 | Toyo Commun Equip Co Ltd | Piezoelectric vibrator to suppress lower order higher harmonic vibration |
| CN1236505A (en) * | 1997-07-28 | 1999-11-24 | 东芝株式会社 | Surface acoustic wave device and method of producing the same |
| CN1237829A (en) * | 1998-06-02 | 1999-12-08 | 株式会社村田制作所 | Chip-type resonator comprising |
| JP2001102898A (en) * | 1999-09-30 | 2001-04-13 | Kyocera Corp | Surface acoustic wave device |
| US20020053958A1 (en) * | 2000-11-09 | 2002-05-09 | Yoshihiro Takahashi | Saw filter device and package for accommodating the same |
| JP2004080771A (en) * | 2002-07-31 | 2004-03-11 | Matsushita Electric Ind Co Ltd | Surface acoustic wave element, surface acoustic wave device, and manufacturing method thereof |
| CN1705227A (en) * | 2004-06-02 | 2005-12-07 | 富士通媒体部品株式会社 | Elastic wave apparatus |
-
2022
- 2022-09-30 CN CN202211213857.2A patent/CN115632628A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1236505A (en) * | 1997-07-28 | 1999-11-24 | 东芝株式会社 | Surface acoustic wave device and method of producing the same |
| JPH11163669A (en) * | 1997-09-24 | 1999-06-18 | Toyo Commun Equip Co Ltd | Piezoelectric vibrator to suppress lower order higher harmonic vibration |
| CN1237829A (en) * | 1998-06-02 | 1999-12-08 | 株式会社村田制作所 | Chip-type resonator comprising |
| JP2001102898A (en) * | 1999-09-30 | 2001-04-13 | Kyocera Corp | Surface acoustic wave device |
| US20020053958A1 (en) * | 2000-11-09 | 2002-05-09 | Yoshihiro Takahashi | Saw filter device and package for accommodating the same |
| JP2004080771A (en) * | 2002-07-31 | 2004-03-11 | Matsushita Electric Ind Co Ltd | Surface acoustic wave element, surface acoustic wave device, and manufacturing method thereof |
| CN1705227A (en) * | 2004-06-02 | 2005-12-07 | 富士通媒体部品株式会社 | Elastic wave apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9270252B2 (en) | Acoustic wave device and method for manufacturing same | |
| CN100559710C (en) | Elastic boundary wave device | |
| EP1296454B1 (en) | SAW element and SAW device | |
| CN109257027B (en) | Hybrid acoustic wave resonator and preparation method thereof | |
| US8502621B2 (en) | Ladder filter and duplexer | |
| WO2007105469A1 (en) | Card type information device and method for manufacturing same | |
| US8188812B2 (en) | Elastic wave device and ladder filter device | |
| JPWO2005011114A1 (en) | Surface acoustic wave device | |
| US20020158708A1 (en) | Surface acoustic wave filter, package for surface acoustic wave filter and surface acoustic wave filter module | |
| JP2007259430A (en) | Surface acoustic wave filter, antenna duplexer, high frequency module using the same, and communication device | |
| JPH0998056A (en) | Surface acoustic wave device | |
| US11637543B2 (en) | Acoustic wave device and acoustic wave module | |
| CN115632628A (en) | Filter structure and manufacturing method thereof, filter chip and electronic equipment | |
| EP2099130A1 (en) | Surface acoustic wave filter device | |
| JPH07154201A (en) | Surface acoustic wave filter | |
| KR100371857B1 (en) | Surface acoustic wave filter, duplexer and communication apparatus | |
| JP3981590B2 (en) | Surface acoustic wave device including surface acoustic wave filter element, base substrate for surface acoustic wave filter element, and surface acoustic wave filter element | |
| CN116248073A (en) | Surface acoustic wave filter and radio frequency chip | |
| US7474034B2 (en) | Surface acoustic wave element and surface acoustic wave device using the same | |
| JP3310132B2 (en) | Surface acoustic wave device and antenna duplexer using the same | |
| JPH0832402A (en) | Surface acoustic wave device, branching filter for mobile radio equipment and mobile radio equipment | |
| US6023204A (en) | Packaged surface acoustic wave filter chips utilizing an on-chip relay terminal | |
| EP2068443A1 (en) | Boundary acoustic wave filter | |
| CN116318043B (en) | Elastic wave filter device, radio frequency front-end module and electronic equipment | |
| CN220067386U (en) | Bulk acoustic wave resonator and filter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |