CN115621140A - Embedded leadless bonding packaging method and packaging structure - Google Patents
Embedded leadless bonding packaging method and packaging structure Download PDFInfo
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- CN115621140A CN115621140A CN202211241641.7A CN202211241641A CN115621140A CN 115621140 A CN115621140 A CN 115621140A CN 202211241641 A CN202211241641 A CN 202211241641A CN 115621140 A CN115621140 A CN 115621140A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
Abstract
The invention provides an embedded leadless bonding packaging method and a packaging structure, wherein the packaging method comprises the following steps: providing an insulating substrate, forming an upper conductive pattern and a lower conductive pattern on the upper surface and the lower surface of the insulating substrate respectively, forming a through hole and a groove which penetrate through the insulating substrate in the insulating substrate, exposing the lower conductive pattern out of the through hole and the groove, and forming an upper conductive pattern on the tops of the side walls of the through hole and the groove; embedding the chip into the groove, wherein the bottom of the chip is connected with the lower conductive pattern; forming a conductive cover plate, wherein the conductive cover plate fills the grooves and the through holes and covers the upper conductive patterns on the tops of the side walls of the grooves and the through holes; the top of the chip is connected with the conductive cover plate and the upper conductive pattern; the conductive cover plate in the through hole is used as a conductive channel to realize the electrical interconnection between adjacent chips. The packaging method provided by the invention has the advantages that no lead is bonded, the fatigue effect generated by a bonding wire process is eliminated, and the packaging reliability is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an embedded type leadless bonding packaging method and a packaging structure.
Background
In the existing chip packaging technology, a chip is connected with an upper conductive layer of a substrate in a surface mount manner, the chip is connected with the chip in a wire bonding manner, and the upper surface of the chip is also connected with the upper conductive layer in the wire bonding manner.
However, under the impact of thermo-mechanical stress, the bonding wire must be subjected to fatigue phenomena, such as breakage of the root of the bonding wire and detachment of the root of the bonding wire, thereby causing failure of the bonding wire. In a high current power module, a plurality of bonding wires are generally used for separationWhen the current is carried, the failure of a single bonding wire can cause other bonding wires connected in parallel to bear larger current. Calculation formula P = I according to power 2 R, the loss on the other bond wires will also increase, resulting in greater thermomechanical stress and consequently failure of the other bond wires. Also, another failure consequence of bond wire fatigue is that as contact resistance and loss increase, the chip can overheat and fail.
Disclosure of Invention
The invention aims to provide an embedded leadless bonding packaging method and a packaging structure, which adopt leadless bonding to eliminate fatigue failure caused by a bonding wire process and improve the packaging reliability.
In order to solve the above technical problem, the present invention provides an embedded leadless bonding packaging method, comprising the following steps:
providing an insulating substrate, forming a plurality of upper conductive patterns and a plurality of lower conductive patterns on the upper surface and the lower surface of the insulating substrate respectively, and forming a plurality of through holes and a plurality of grooves which penetrate through the insulating substrate in the insulating substrate, wherein the lower conductive patterns are exposed out of the through holes and the grooves, and the upper conductive patterns are formed on the tops of the side walls of the through holes and the grooves;
embedding a chip into the groove, wherein the bottom of the chip is connected with the lower conductive pattern; and
forming a conductive cover plate, wherein the conductive cover plate fills the groove and the through hole and covers the upper conductive pattern on the top of the side wall of the groove and the through hole; the top of the chip is connected with the conductive cover plate and the upper conductive pattern; the conductive cover plate in the through hole is used as a conductive channel to realize the electrical interconnection between the adjacent chips.
Optionally, the chip is embedded in the groove, the front surface of the chip is connected to the lower conductive pattern, and the back surface of the chip is connected to the conductive cover plate and the upper conductive pattern.
Optionally, the connection mode between the front surface of the chip and the lower conductive pattern includes welding, sintering or crimping; the connection mode of the back surface of the chip and the conductive cover plate comprises welding, sintering or crimping.
Optionally, a first solder layer is disposed between the front surface of the chip and the lower conductive pattern; or/and a second solder layer is arranged between the back surface of the chip and the conductive cover plate.
Optionally, a source and a gate are disposed on the front surface of the chip, and the source and the gate are connected to different lower conductive patterns.
Optionally, the insulating substrate is left at a part of the bottom of the groove, and the remaining insulating substrate is used for isolating the source and the gate of the chip.
Optionally, the back surface of the chip is provided with a drain, and the conductive cover plates connected to the drains of different chips are isolated from each other.
Optionally, the conductive channel is located between adjacent chips, and the source of one of the chips is connected to the drain of the other chip through the conductive channel.
Correspondingly, the invention also provides an embedded leadless bonding package structure, which comprises:
the circuit board comprises an insulating substrate, wherein a plurality of through holes and a plurality of grooves penetrating through the insulating substrate are formed in the insulating substrate;
the upper conductive patterns are formed on the tops of the through holes and the side walls of the grooves;
the lower conductive patterns are arranged on the lower surface of the insulating substrate, and the lower conductive patterns are arranged at the bottoms of the through holes and the grooves;
the chip is embedded in the groove, and the bottom of the chip is connected with the lower conductive pattern;
the conductive cover plate covers the top of the chip and the upper conductive patterns on the tops of the groove and the side wall of the through hole; and
and the conductive channel is positioned in the through hole so as to connect the adjacent chips.
Optionally, the front surface of the chip is connected to the lower conductive pattern, and the back surface of the chip is connected to the conductive cover plate and the upper conductive pattern.
In summary, in the packaging method and the packaging structure of the embedded leadless bonding provided by the present invention, a plurality of upper conductive patterns and a plurality of lower conductive patterns are respectively formed on the upper surface and the lower surface of an insulating substrate, and a plurality of through holes and a plurality of grooves penetrating through the insulating substrate are also formed in the insulating substrate, the lower conductive patterns are exposed from the through holes and the grooves, and the upper conductive patterns are formed on the top of the side walls of the through holes and the grooves; then embedding a chip into the groove, wherein the bottom of the chip is connected with the lower conductive pattern; then forming a conductive cover plate, wherein the conductive cover plate fills the groove and the through hole and covers the groove and the upper conductive pattern on the top of the side wall of the through hole; the top of the chip is connected with the conductive cover plate and the upper conductive pattern; the conductive cover plate in the through hole is used as a conductive channel to realize the electrical interconnection between the adjacent chips. The embedded leadless bonding packaging method provided by the invention has the advantages that the leadless bonding is realized, the fatigue effect caused by a bonding wire process is eliminated, and the packaging reliability is improved.
Lead bonding is not needed, stray inductance introduced by a bonding wire can be eliminated, vibration is reduced, voltage spikes are reduced, electromagnetic interference is reduced, and chip switching loss is reduced. In addition, because the adjacent chips are electrically interconnected only through the conductive channel, the interconnection channel among the chips is shortened, and the interconnection channel between the chips and the power terminal is also shortened, so that the inductance, the resistance and the capacitance are reduced, the signal delay is reduced, and the high-frequency characteristic is better. Meanwhile, since no bonding wire is needed, the size of the packaging structure is reduced. In addition, the upper surface and the lower surface of the insulating substrate in the packaging structure are provided with the conductive patterns, so that the heat dissipation capability of the packaging structure is improved.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:
fig. 1 is a flowchart of an embedded leadless bonding packaging method according to an embodiment of the present invention.
Fig. 2 to fig. 6 are schematic structural diagrams of steps of an embedded leadless bonding packaging method according to an embodiment of the present invention.
In the drawings:
10-an insulating substrate; 11-an upper conductive pattern; 12-a lower conductive pattern; 13-a through hole; 14-a groove; 15-a first solder layer; 16-a chip; 17-a second solder layer; 18-a conductive cover plate; 19-conductive path.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in simplified form and are not to scale, but are provided for the purpose of facilitating and clearly illustrating embodiments of the present invention. Further, the structures illustrated in the drawings are intended to be part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first", "second", "third" may explicitly or implicitly include one or at least two of such features, the term "proximal" is typically the end near the operator, the term "distal" is typically the end near the patient, "end" with "another end" and "proximal" with "distal" are typically the corresponding two parts, which include not only end points, the terms "mounted", "connected" and "connected" are to be understood broadly, e.g., they may be fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. Furthermore, as used in the present invention, the disposition of an element with another element generally only means that there is a connection, coupling, fit or driving relationship between the two elements, and the connection, coupling, fit or driving relationship between the two elements may be direct or indirect through intermediate elements, and cannot be understood as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation inside, outside, above, below or to one side of another element, unless the content clearly indicates otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Fig. 1 is a flowchart of an embedded leadless bonding packaging method according to an embodiment of the present invention. As shown in fig. 1, the method for encapsulating the embedded leadless bonding comprises the following steps:
s1: providing an insulating substrate, forming a plurality of upper conductive patterns and a plurality of lower conductive patterns on the upper surface and the lower surface of the insulating substrate respectively, and forming a plurality of through holes and a plurality of grooves which penetrate through the insulating substrate in the insulating substrate, wherein the lower conductive patterns are exposed out of the through holes and the grooves, and the upper conductive patterns are formed on the tops of the side walls of the through holes and the grooves;
s2: embedding a chip into the groove, wherein the bottom of the chip is connected with the lower conductive pattern;
s3: forming a conductive cover plate, wherein the conductive cover plate fills the groove and the through hole and covers the upper conductive pattern on the top of the side wall of the groove and the through hole; the top of the chip is connected with the conductive cover plate and the upper conductive pattern; the conductive cover plate in the through hole is used as a conductive channel to realize the electrical interconnection between the adjacent chips.
Fig. 2 to fig. 6 are schematic structural diagrams of steps of an embedded leadless bonding packaging method according to an embodiment of the present invention. Next, a method for packaging an embedded leadless bonding provided by an embodiment of the present invention will be described in detail with reference to fig. 1 and fig. 2 to 6.
In step S1, please refer to fig. 2, an insulating substrate 10 is provided, a plurality of upper conductive patterns 11 and a plurality of lower conductive patterns 12 are respectively formed on an upper surface and a lower surface of the insulating substrate 10, a plurality of through holes 13 and a plurality of grooves 14 penetrating through the insulating substrate 10 are further formed in the insulating substrate 10, the lower conductive patterns 12 are exposed from the through holes 13 and the grooves 14, and the upper conductive patterns 11 are formed on top portions of sidewalls of the through holes 13 and the grooves 14.
For example, an upper conductive material layer is formed on the upper surface of the insulating substrate 10, a patterned mask layer (e.g., a patterned photoresist layer) is formed on the upper conductive material layer, the upper conductive material layer is etched using the patterned mask layer as a mask until the insulating substrate 10 is exposed, a plurality of upper conductive patterns 11 are formed, and finally the patterned mask layer is removed.
Similarly, a lower conductive material layer may be formed on the lower surface of the insulating substrate 10, a patterned mask layer (e.g., a patterned photoresist layer) may be formed on the lower conductive material layer, the lower conductive material layer may be etched with the patterned mask layer as a mask until the insulating substrate 10 is exposed, a plurality of lower conductive patterns 12 may be formed, and finally the patterned mask layer may be removed.
Forming a mask layer (such as a photoresist layer) on the upper surface of the insulating substrate 10, wherein the mask layer covers the insulating substrate 10 and the upper conductive pattern 11, and patterning the mask layer to form a patterned mask layer, wherein the patterned mask layer exposes a region where the through hole 13 and the groove 14 are to be formed; then, etching the insulating substrate 10 by using the patterned mask layer as a mask until the lower conductive pattern 12 is exposed, and forming the through hole 13 and the groove 14; and finally, removing the patterned mask layer. The cross-sectional shape of the through-hole 13 may be circular, elliptical or rectangular, but is not limited thereto; the cross-sectional shape of the groove 14 may be rectangular or trapezoidal, but is not limited thereto.
The above description is only exemplary of the forming method of the upper conductive pattern 11, the lower conductive pattern 12, the through hole 13 and the groove 14, and other methods known to those skilled in the art may be used, and the present invention is not limited thereto. Also, the order of forming the upper conductive pattern 11, the lower conductive pattern 12, the via hole 13, and the groove 14 is not limited in the present invention.
Referring to fig. 2, preferably, the through holes 13 are located between adjacent grooves 14. In this embodiment, 2 through holes 13 and two grooves 14 are formed in the insulating substrate 10, the two grooves 14 are used for embedding two chips, and the two through holes 13 are located between the two adjacent grooves 14. Of course, the number of the grooves 14 is not limited thereto, and the number of the through holes 13 between the adjacent grooves 14 is also not limited thereto.
The insulating substrate 10 is remained at a part of the bottom of the groove 14, the remaining insulating substrate 10 is used for isolating the source and the gate of the chip embedded subsequently, the remaining insulating substrate 10 divides the bottom of the groove 14 into two parts, and the bottoms of the two parts are respectively exposed out of the different lower conductive patterns 12, so that the source and the gate of the chip are connected to the different lower conductive patterns 12.
In the present embodiment, the material of the insulating substrate 10 is preferably ceramic, but is not limited thereto.
In step S2, please refer to fig. 4, a chip 16 is embedded in the groove 14, and the bottom of the chip 16 is connected to the lower conductive pattern 12.
In this embodiment, the chip 16 is embedded in the groove 14, and the front surface of the chip 16 is connected to the lower conductive pattern 12. The bottom of the chip 16 mentioned later is the front surface of the chip 16, and the top of the chip 16 is the back surface of the chip 16.
The connection of the front surface of the chip 16 to the lower conductive pattern 12 includes, but is not limited to, soldering, sintering, or crimping. The following are exemplary: referring to fig. 3, a first solder layer 15 is disposed between the front surface of the chip 16 and the lower conductive pattern 12, and the connection between the front surface of the chip 16 and the lower conductive pattern 12 is realized through the first solder layer 15. The front surface of the chip 16 is provided with a source and a gate, which need to be connected to different lower conductive patterns 12, so that two first solder layers 15 are provided at the bottom of the groove 14, and the two first solder layers 15 are separated by the insulating substrate 10 remaining at the bottom of the groove 14. Two first solder layers 15 are connected to the two lower conductive patterns 12, respectively.
Next, referring to fig. 4, the front surface of the chip 16 is embedded in the groove 14, the chip 16 is connected to the lower conductive patterns 12 through the first solder layer 15, the source of the chip 16 is connected to one of the lower conductive patterns 12 (labeled as S in the figure), and the gate of the chip 16 is connected to the other of the lower conductive patterns 12 (labeled as G in the figure). Of course, the lower conductive patterns 12 to which different chips 16 are connected are isolated from each other. And the lower conductive pattern 12 exposed by the via 13 may be the conductive pattern 12 connected to one of the chips 16. For example, in fig. 4, the lower conductive pattern 12 exposed by the via 13 is the lower conductive pattern 12 connected to the source of the chip 16 on the right side adjacent thereto.
The connection of the backside of the chip 16 to the subsequently formed conductive cover plate may also include soldering, sintering or crimping. Specifically, referring to fig. 5, the second solder layer 17 is disposed in the groove 14, and the second solder layer 17 is located on the back surface of the chip 16 and is used for connecting with a subsequent conductive cover plate.
In step S3, please refer to fig. 6, a conductive cover 18 is formed, and the conductive cover 18 fills the groove 14 and the through hole 13 and covers the upper conductive pattern 11 on the top of the sidewall of the groove 14 and the through hole 13; the top of the chip 16 is connected to the conductive cover plate 18 and the upper conductive pattern 11; the conductive cover plates in the through holes 13 serve as conductive paths 19 to electrically interconnect adjacent chips 16.
In an embodiment of the present invention, the cover plate 18 and the conductive vias 19 may be integrally formed and then covered on the structure shown in fig. 5, so as to form the structure shown in fig. 6.
In another embodiment of the present invention, a conductive material may be formed to cover the top of the chip 16 and the upper conductive pattern 11 on the top of the sidewall of the groove 14 and the via 13 to form a conductive cover plate 18; while the conductive material also fills the through-hole 13 to form a conductive path 19.
The conductive cover plate 18 covers the top of the chip 16, and in particular, is connected to the back side of the chip 16 by the second solder layer 17. The back side of the chip 16 is provided with a drain, and the conductive cover 18 is connected to the drain on the back side of the chip 16 (labeled D in the figure). The conductive cover 18 also covers the upper conductive pattern 11 at the top of the sidewall of the groove 14, so that the top (specifically, the back) of the chip 16 is connected to the conductive cover 18 and the conductive pattern 11.
Referring to fig. 6, the conductive caps 18 connected to the drains of different chips 16 are isolated from each other to isolate the drains of adjacent chips 16. As described above, the lower conductive pattern 12 exposed at the bottom of the through hole 13 is integrated with the lower conductive pattern 12 to which the source of the chip 16 on the right side is connected, and the conductive channel 19 formed in the through hole 13 is connected to the conductive cap 18 to which the drain of the chip 16 on the left side is connected, thereby achieving electrical connection between the adjacent chips 16. Specifically, the lower conductive pattern 12 connected to the source of the chip 16 on the right side in fig. 6 is connected to the conductive cap 18 connected to the drain of the chip 16 on the left side through a conductive channel 19, that is, the source of one chip 16 is connected to the drain of the other chip 16 through the conductive channel 19.
In the packaging method of the embedded leadless bonding, the bottom of the chip 16 is connected with the lower conductive pattern 12, the top of the chip is connected with the conductive cover plate 18 and the upper conductive pattern 11, and the adjacent chips 16 are electrically interconnected through the conductive channel 19 without the need of the lead bonding, thereby eliminating the fatigue effect generated by the bonding wire process and improving the packaging reliability.
In the prior art, a chip package by wire bonding simulates the AC stray inductance L =3.64nH, and a package structure formed by the packaging method provided by the embodiment of the invention simulates the AC stray inductance L =0.6nH, which is obviously reduced compared with the prior art. Therefore, compared with the packaging method by wire bonding in the prior art, the packaging method provided by the embodiment of the invention does not need wire bonding, eliminates stray inductance introduced by a bonding wire, reduces oscillation, reduces voltage spike, reduces electromagnetic interference and reduces switching loss of the chip 16. In addition, because the adjacent chips 16 are electrically interconnected only through the conductive channels 19, the interconnection channels between the chips 16 are shortened, and the interconnection channels between the chips 16 and the power terminals are also shortened, so that the inductance, the resistance and the capacitance are reduced, the signal delay is reduced, and the high-frequency characteristics are better.
Also, in the present embodiment, since a bonding wire is not required, the size of the package structure is reduced, compared to the packaging method by wire bonding in the related art. In addition, since the upper and lower surfaces of the insulating substrate 10 in the package structure have the conductive patterns, the heat dissipation capability of the package structure is increased.
Correspondingly, the invention also provides an embedded leadless bonding packaging structure which is packaged by adopting the embedded leadless bonding packaging method. Referring to fig. 6, the embedded leadless bonded package structure includes:
an insulating substrate 10, wherein a plurality of through holes 13 and a plurality of grooves 14 penetrating through the insulating substrate 10 are formed in the insulating substrate 10;
a plurality of upper conductive patterns 11 on the upper surface of the insulating substrate 10, wherein the upper conductive patterns 11 are formed on the tops of the sidewalls of the through holes 13 and the grooves 14;
a plurality of lower conductive patterns 12 located on the lower surface of the insulating substrate 10, wherein the lower conductive patterns 12 are disposed at the bottoms of the through holes 13 and the grooves 14;
a chip 16 embedded in the groove 14, wherein the bottom of the chip 16 is connected to the lower conductive pattern 12;
a conductive cap 18 covering the top of the chip 16 and the upper conductive pattern 11 on the top of the sidewall of the groove 14 and the via 13; and
and the conductive channel 19 is positioned in the through hole 13 so as to connect the adjacent chips 16.
Further, the chip 16 is embedded in the groove 14, the front surface of the chip 16 is connected to the lower conductive pattern 12, and the back surface of the chip 16 is connected to the conductive cover plate 18 and the upper conductive pattern 11.
A source electrode and a gate electrode are disposed on the front surface of the chip 16, and are respectively connected to the different lower conductive patterns 12, and a drain electrode is disposed on the back surface of the chip 16, and is connected to the conductive cap plate 18 and the upper conductive pattern 11.
The through holes 13 are located between adjacent grooves 14, so that the conductive vias 19 are located between adjacent chips 16. In two adjacent chips 16, the source of one chip 16 is connected to the drain of the other chip 16 through the lower conductive pattern 12 and the conductive channel 19, so as to realize the electrical connection between the adjacent chips 16.
In summary, in the method for encapsulating an embedded leadless bonding provided by the present invention, a plurality of upper conductive patterns and a plurality of lower conductive patterns are respectively formed on the upper surface and the lower surface of an insulating substrate, and a plurality of through holes and a plurality of grooves penetrating through the insulating substrate are also formed in the insulating substrate, the lower conductive patterns are exposed from the through holes and the grooves, and the upper conductive patterns are formed on the top of the sidewalls of the through holes and the grooves; then embedding a chip into the groove, wherein the bottom of the chip is connected with the lower conductive pattern; then forming a conductive cover plate and a conductive channel, wherein the conductive cover plate fills the groove and the through hole and covers the upper conductive pattern on the top of the side wall of the groove and the through hole; the top of the chip is connected with the conductive cover plate and the upper conductive pattern; the conductive cover plate in the through hole is used as a conductive channel to realize the electrical interconnection between the adjacent chips. The packaging structure formed by the embedded leadless bonding packaging method provided by the invention has the advantages of leadless bonding, elimination of fatigue effect caused by a bonding wire process and improvement of packaging reliability.
Lead bonding is not needed, stray inductance introduced by a bonding wire can be eliminated, vibration is reduced, voltage spikes are reduced, electromagnetic interference is reduced, and chip switching loss is reduced. In addition, because the adjacent chips are electrically interconnected only through the conductive channel, the interconnection channel between the chips is shortened, and the interconnection channel between the chip and the power terminal is also shortened, so that the inductance, the resistance and the capacitance are reduced, the signal delay is reduced, and the high-frequency characteristic is better. Meanwhile, since no bonding wire is needed, the size of the packaging structure is reduced. In addition, the upper surface and the lower surface of the insulating substrate in the packaging structure are provided with the conductive patterns, so that the heat dissipation capability of the packaging structure is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (10)
1. An embedded leadless bonding packaging method is characterized by comprising the following steps:
providing an insulating substrate, forming a plurality of upper conductive patterns and a plurality of lower conductive patterns on the upper surface and the lower surface of the insulating substrate respectively, and forming a plurality of through holes and a plurality of grooves which penetrate through the insulating substrate in the insulating substrate, wherein the lower conductive patterns are exposed out of the through holes and the grooves, and the upper conductive patterns are formed on the tops of the side walls of the through holes and the grooves;
embedding a chip into the groove, wherein the bottom of the chip is connected with the lower conductive pattern; and
forming a conductive cover plate, wherein the conductive cover plate fills the groove and the through hole and covers the groove and the upper conductive pattern on the top of the side wall of the through hole; the top of the chip is connected with the conductive cover plate and the upper conductive pattern; the conductive cover plate in the through hole is used as a conductive channel to realize the electrical interconnection between the adjacent chips.
2. The method of claim 1, wherein the chip is embedded in the recess, a front surface of the chip is connected to the lower conductive pattern, and a back surface of the chip is connected to the conductive cover plate and the upper conductive pattern.
3. The method for encapsulating embedded leadless bonding according to claim 2, wherein the connection manner of the front surface of the chip and the lower conductive pattern comprises soldering, sintering or crimping; the connection mode of the back surface of the chip and the conductive cover plate comprises welding, sintering or crimping.
4. The method of claim 3, wherein a first solder layer is disposed between the front surface of the chip and the lower conductive pattern; or/and a second solder layer is arranged between the back surface of the chip and the conductive cover plate.
5. The method of claim 2, wherein a source and a gate are disposed on the front side of the chip, and the source and the gate are connected to different lower conductive patterns.
6. The method of claim 5, wherein the insulating substrate remains at a portion of the bottom of the recess, and the remaining insulating substrate is used to isolate the source and the gate of the chip.
7. The method of claim 5, wherein the back side of the chip is provided with a drain, and the conductive cover plates connected to the drains of different chips are isolated from each other.
8. The method of claim 7, wherein the conductive vias are located between adjacent chips, the adjacent chips having the source of one chip connected to the drain of another chip via the conductive vias.
9. An embedded leadless bonded package, comprising:
the circuit board comprises an insulating substrate, wherein a plurality of through holes and a plurality of grooves penetrating through the insulating substrate are formed in the insulating substrate;
the upper conductive patterns are formed on the tops of the through holes and the side walls of the grooves;
the lower conductive patterns are arranged on the lower surface of the insulating substrate, and the lower conductive patterns are arranged at the bottoms of the through holes and the grooves;
the chip is embedded in the groove, and the bottom of the chip is connected with the lower conductive pattern;
the conductive cover plate covers the top of the chip and the upper conductive patterns on the tops of the groove and the side wall of the through hole; and
and the conductive channel is positioned in the through hole so as to connect the adjacent chips.
10. The embedded leadless bonded package structure of claim 9, wherein the front surface of the chip is connected to the lower conductive pattern, and the back surface of the chip is connected to the conductive cover plate and the upper conductive pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211241641.7A CN115621140A (en) | 2022-10-11 | 2022-10-11 | Embedded leadless bonding packaging method and packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211241641.7A CN115621140A (en) | 2022-10-11 | 2022-10-11 | Embedded leadless bonding packaging method and packaging structure |
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| CN115621140A true CN115621140A (en) | 2023-01-17 |
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| CN202211241641.7A Pending CN115621140A (en) | 2022-10-11 | 2022-10-11 | Embedded leadless bonding packaging method and packaging structure |
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