CN115620773A - Semiconductor structure and memory - Google Patents

Semiconductor structure and memory Download PDF

Info

Publication number
CN115620773A
CN115620773A CN202211244265.7A CN202211244265A CN115620773A CN 115620773 A CN115620773 A CN 115620773A CN 202211244265 A CN202211244265 A CN 202211244265A CN 115620773 A CN115620773 A CN 115620773A
Authority
CN
China
Prior art keywords
read
write control
data lines
odd
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211244265.7A
Other languages
Chinese (zh)
Inventor
常小卫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202211244265.7A priority Critical patent/CN115620773A/en
Publication of CN115620773A publication Critical patent/CN115620773A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a memory, the semiconductor structure including: a memory cell array including a first memory cell sub-array and a second memory cell sub-array arranged in a first direction; a first data line group including a plurality of first data lines connected to the first memory cell sub-arrays; a second data line group including a plurality of second data lines connected to the second memory cell sub-array; the plurality of read-write control circuits comprise a plurality of odd read-write control circuits and a plurality of even read-write control circuits, and the odd read-write control circuits and the even read-write control circuits are alternately arranged in sequence; the odd read-write control circuits are respectively connected with first odd data lines in the first data lines and second odd data lines in the second data lines in a one-to-one corresponding manner, and the even read-write control circuits are respectively connected with first even data lines in the first data lines and second even data lines in the second data lines in a one-to-one corresponding manner.

Description

Semiconductor structure and memory
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a memory.
Background
Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and high transmission speed. The dynamic random access memory generally includes a core memory area and a peripheral circuit area, wherein the core memory area is used for arranging a plurality of memory cells for storing data information, and the peripheral circuit area is electrically connected with the memory cells through data lines, so that the memory cells complete storage or reading of the data information.
With the development of semiconductor technology, the integration level of the memory unit is higher and higher, the connection line between the peripheral circuit and the memory unit is more and more complex, the difficulty of the preparation process of the memory is increased, and meanwhile, the power consumption of the memory is higher and higher, so that the performance of the memory is reduced.
Disclosure of Invention
Embodiments of the present disclosure provide a semiconductor structure and a memory.
In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, including:
a memory cell array including a first memory cell sub-array and a second memory cell sub-array arranged in a first direction;
a first data line group including a plurality of first data lines connected to the first memory cell sub-arrays;
a second data line group including a plurality of second data lines, the second data lines being connected to the second memory cell sub-arrays, the first data lines and the second data lines being arranged at intervals;
the plurality of read-write control circuits comprise a plurality of odd read-write control circuits and a plurality of even read-write control circuits, and the odd read-write control circuits and the even read-write control circuits are sequentially and alternately arranged; wherein the content of the first and second substances,
the odd read-write control circuits are respectively connected with first odd data lines in the first data lines and second odd data lines in the second data lines in a one-to-one corresponding mode, and the even read-write control circuits are respectively connected with first even data lines in the first data lines and second even data lines in the second data lines in a one-to-one corresponding mode.
In some embodiments, the semiconductor structure further comprises:
a buffer circuit, the buffer circuit comprising: and each buffer sub-circuit is connected with one read-write control circuit and is used for transmitting a control signal to the read-write control circuit.
In some embodiments, the plurality of buffer sub-circuits comprises: a plurality of odd buffer sub-circuits and a plurality of even buffer sub-circuits; wherein the content of the first and second substances,
the odd buffer sub-circuit is connected with the odd read-write control circuit; the even number buffer sub-circuit is connected with the even number read-write control circuit.
In some embodiments, the number of odd buffer sub-circuits is equal to the number of even buffer sub-circuits;
the number of the odd read-write control circuits is equal to that of the even read-write control circuits.
In some embodiments, the semiconductor structure further comprises:
the first control signal line is connected with the plurality of odd buffer sub-circuits and used for transmitting control signals of the odd read-write control circuit;
and the second control signal line is connected with the plurality of even buffer sub-circuits and is used for transmitting control signals to the even read-write control circuit.
In some embodiments, the read-write control circuit is located on one side of the memory cell array in the second direction; the second direction is perpendicular to the first direction.
In some embodiments, the buffer circuit is located on a side of the read-write control circuit away from the memory cell array in the second direction.
In some embodiments, the plurality of buffer sub-circuits are spaced along the first direction.
In some embodiments, the semiconductor structure further comprises:
and a control line connected between the plurality of read/write control circuits.
In a second aspect, an embodiment of the present disclosure further provides a memory, including:
a plurality of semiconductor structures as described in any of the above embodiments.
In the semiconductor structure provided by the embodiment of the disclosure, a first memory cell sub-array and a second memory cell sub-array arranged along a first direction are respectively connected with a first data line in a first data line group and a second data line in a second data line group; the read-write control circuits corresponding to each memory cell sub-array are arranged in an odd-even alternating mode and are respectively connected with the first data lines and the second data lines in a one-to-one correspondence mode according to the odd-even arrangement. Therefore, each storage unit sub-array is correspondingly connected with the read-write control circuit one by one through the data lines, so that the jumper wires in wiring can be reduced, the circuit layout design is simplified, and the power loss caused by a large number of data lines is reduced.
Drawings
FIG. 1 is a basic architecture of a layout of a read/write control circuit of a DRAM in an embodiment;
FIG. 2 is a layout of a circuit layout in an embodiment;
FIG. 3 is a diagram illustrating an embodiment of read/write control circuit distribution and connection with data lines;
FIG. 4 is a schematic distribution diagram of a read/write control circuit and a memory cell array according to an embodiment of the disclosure;
fig. 5 is a schematic diagram illustrating distribution of a read/write control circuit and a connection relationship between the read/write control circuit and a data line according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram of a circuit layout according to an embodiment of the disclosure;
FIG. 7 is a schematic diagram illustrating a portion of a trace of the second metal layer M2 according to an embodiment;
fig. 8 is a schematic diagram of a partial trace of a second metal layer M2 according to an embodiment of the disclosure.
Detailed Description
To facilitate an understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the associated drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In some embodiments, some technical features that are well known in the art are not described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment may be described herein, and well-known functions and structures may not be described in detail.
In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending at least in part on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on the context.
Unless otherwise defined, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be set forth in the following description in order to explain the technical aspects of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.
A semiconductor memory is a memory accessed using a semiconductor circuit, in which a DRAM is widely used in various fields with its fast storage speed and high integration. The disclosed embodiments are described with reference to the circuit layout of a DRAM as an example.
In some embodiments, fig. 1 is a basic architecture of a read/write control circuit layout (RWBnk) of a DRAM, and each read/write control circuit RW2B (e.g., RW2B _0, RW2B _1, … … RW2B _ 15) is connected to a memory cell Array (Array) through a data signal line YIO.
In the layout of the circuit layout, as shown in fig. 2, the read-write control circuit (odd read-write control circuit 11) corresponding to the first memory cell sub-array and the read-write control circuit (even read-write control circuit 12) corresponding to the second memory cell sub-array are respectively arranged in two regions: a first region 21 and a second region 22. Here, the first memory cell sub-array and the second memory cell sub-array are alternately arranged, and the correspondingly connected data lines YIO are also alternately arranged, that is, yio <0>, yio <1>, yio <2> and Yio <3> are alternately arranged in odd-even, and memory cells of odd-numbered bits in the first memory cell sub-array 111 are connected, yio <4>, yio <5>, yio <6> and Yio <7> are connected to memory cells of even-numbered bits in the first memory cell sub-array 111, and memory cells of even-numbered bits in the second memory cell sub-array 112 are connected, yio <8>, yio <9>, yio <10> and Yio <11> are connected to memory cells of odd-numbered 5384, 4225, 42xft 4284 > and 425623 > of odd-numbered bit 6223, 425623 and 425623 in the second memory cell sub-array 111. However, since the odd read-write control circuits 11 and the even read-write control circuits 12 are separately arranged in two adjacent regions, that is, the odd read-write control circuits 11 are arranged in the first region 21 in sequence, and the even read-write control circuits 12 are arranged in the second region 22 in sequence, the read-write control circuits and the memory cell sub-arrays are not arranged in a one-to-one corresponding positional relationship.
Illustratively, as shown in fig. 3, the odd read-write control circuit 11 includes 8 parallel circuit units W _ bit0 to W _ bit7, and the even read-write control circuit 12 also includes 8 parallel circuit units E _ bit0 to E _ bit 7. These circuit cells need to be alternately connected to data lines Yio _ < X > (where X denotes the number of data lines) respectively corresponding to memory cell sub-arrays alternately arranged in odd and even, and thus a large number of X-direction jumper lines are required (only some of the connection lines are schematically marked in fig. 3). That is, the data lines connecting the read/write control circuit and the memory cell sub-arrays need to be connected not only by a large number of metal wires extending in the Y direction but also by jumper lines in the X direction connected to other metal layers through vias. For example, the metal lines extending in the Y direction are located in the first metal layer M1, and the metal lines extending in the X direction are located in the second metal layer M2. The connection method may cause the second metal layer M2 to include a large number of metal line segments, thereby increasing the complexity of circuit layout, increasing the power consumption of the circuit, and easily causing data transmission errors due to too long data wires.
The embodiment of the present disclosure provides a semiconductor structure 100, as shown in fig. 4, including:
a memory cell array 110 including a first memory cell sub-array 111 and a second memory cell sub-array 112 arranged in a first direction;
a first data line group 120 including a plurality of first data lines 121, the first data lines 121 connecting the first memory cell sub-arrays 111;
a second data line group 130 including a plurality of second data lines 131, the second data lines 131 being connected to the second memory cell sub-array 112, the first data lines 121 and the second data lines 131 being arranged at intervals;
the plurality of read-write control circuits 140 include a plurality of odd read-write control circuits 141 and a plurality of even read-write control circuits 142, and the odd read-write control circuits 141 and the even read-write control circuits 142 are alternately arranged in sequence; wherein the content of the first and second substances,
the odd read/write control circuits 141 are respectively connected to first odd data lines 121a of the first data lines 121 and second odd data lines 131a of the second data lines 131 in a one-to-one correspondence manner, and the even read/write control circuits 142 are respectively connected to first even data lines 121b of the first data lines 121 and second even data lines 131b of the second data lines 131 in a one-to-one correspondence manner.
It is understood that the first memory cell sub-array 111 and the second memory cell sub-array 112 are arranged in parallel, and the data lines connected to the respective memory cell sub-arrays are arranged in sequence along a first direction, such as the X direction shown in fig. 4, and the data lines connected to the respective memory cell sub-arrays are also arranged at intervals in the X direction.
A first odd data line 121a of the first data lines 121 and a second odd data line 131a of the second data lines 131, which are data lines located at odd positions among all sequentially arranged data lines, the first odd data line 121a of the first data lines 121 receiving data of odd-bit memory cells of the first memory cell sub-array 111, and the second odd data line 131a of the second data lines 131 receiving data of odd-bit memory cells of the second memory cell sub-array 112; similarly, the first even data line 121b in the first data line 121 and the second even data line 131b in the second data line 131 are data lines located at even positions in all the sequentially arranged data lines, the first even data line 121b in the first data line 121 receives data of even bit memory cells of the first memory cell sub-array 111, and the second even data line 131b in the second data line 131 receives data of even bit memory cells of the second memory cell sub-array 112.
In the embodiment of the present disclosure, the read/write control circuit 140 is divided into an odd read/write control circuit 141 and an even read/write control circuit 142, which are alternately arranged in sequence and are connected to the data lines in a one-to-one correspondence. In this manner, a connection relationship as shown in fig. 5 can be formed: the odd read-write control circuits W _ bit0-7 (141) and the even read-write control circuits E _ bit0-7 (142) are alternately arranged in sequence and are correspondingly connected with the data lines Yio _ < x > one by one. It can be seen that, since the read/write control circuit 140 corresponds to the memory cell sub-arrays one to one, a large number of circuit traces extending in the X direction can be reduced. Illustratively, in the structure shown in fig. 5, each memory cell array and the read-write control circuit can be connected only by the data line Yio _ < x > extending in the Y direction. It should be noted that the sequence of Yio _ < x > numbering shown in fig. 5 is only an example, the odd-numbered data lines and the even-numbered data lines only represent the parity distribution of the locations of the data lines, and specifically, yio <0>, yio <1>, yio <2> and Yio <3> receive the data of the odd-numbered bit storage units in the first storage unit sub-array 111, yio <4>, yio <5>, yio <6> and Yio <7> receive the data of the even-numbered bit storage units in the first storage unit sub-array 111, yio <8>, 3424 zxft 5224 <9>, 3535 < 3535 > and 3584 < 353584 > receive the data of the even-numbered storage units in the second storage unit sub-array 6223, 4254 zxft 3272 <8>, 4224 zxft 3214, 4235 > and 3584 > receive the data of the odd-numbered units of the even-numbered 6212 and 42xzft sub-numbered sub-array 4223.
If the data line Yio _ < X > is partially laid out in the first metal layer M1 along the Y direction and partially laid out in the second metal layer M2 along the X direction, then the number of wirings in the second metal layer M2 can be reduced by the above-described embodiment, thereby reducing the complexity of the whole circuit and saving the layout space. Moreover, even if the data line Yio _ < x > is short, power consumption can be effectively reduced and the probability of data transmission errors can be reduced.
In some embodiments, as shown in fig. 6, the semiconductor structure 100 further comprises:
a buffer circuit 210, the buffer circuit 210 comprising: and each buffer sub-circuit is connected with one read-write control circuit 140, and the buffer sub-circuits are used for transmitting control signals to the read-write control circuit 140.
In some embodiments, the plurality of buffer sub-circuits are spaced along the first direction.
The first direction here is the X direction as shown in fig. 6.
In some embodiments, the plurality of buffer sub-circuits comprises: a plurality of odd buffer sub-circuits 211 and a plurality of even buffer sub-circuits 212; the odd buffer sub-circuit 211 is connected to the odd read-write control circuit 141; the even buffer sub-circuit 212 is connected to the even read/write control circuit 142.
In contrast to the manner of disposing the odd buffer sub-circuit 211 and the even buffer sub-circuit 212 in two regions at intervals as shown in fig. 3, the alternate disposition as shown in fig. 6 is adopted in the embodiment of the present disclosure.
This may cause a part of the line to grow because of the interconnection between the plurality of odd buffer sub-circuits 211 and the interconnection between the plurality of even buffer sub-circuits 212. However, considering that this approach facilitates the connection of the read/write control circuit 140, the growth of this small part of the circuit is also acceptable.
It should be noted that the connecting lines of the circuits shown in fig. 6 are only schematic lines showing the interaction relationship among the circuits, and do not represent the structure of the actual circuit traces, and the actual circuit may include more traces, or may include bent portions or additional devices or circuits.
In some embodiments, the number of odd buffer subcircuits 211 is equal to the number of even buffer subcircuits 212; the number of the odd read/write control circuits 141 is equal to the number of the even read/write control circuits 141.
Thus, each read-write control circuit is connected with one buffer sub-circuit in a one-to-one correspondence mode. Moreover, each odd buffer sub-circuit 211 can be connected to an odd read-write control circuit 141; each even buffer subcircuit 212 may be connected to an even read write control circuit 142.
In some embodiments, the semiconductor structure further comprises:
a first control signal line 221, connected to the plurality of odd buffer sub-circuits 211, for transmitting a control signal to the odd read/write control circuit 141;
the second control signal line 222 is connected to the plurality of even buffer sub-circuits 212, and is used for transmitting a control signal to the even read/write control circuit 142.
The first control signal line 221 is connected to the plurality of odd buffer sub-circuits 211 and can transmit a control signal to the plurality of odd read/write control circuits 141 through the plurality of odd buffer sub-circuits 211, so as to control the odd read/write control circuits 141, that is, the first control signal line 221 is used for connecting the plurality of odd buffer sub-circuits 211 together and transmitting a control signal corresponding to the plurality of odd buffer sub-circuits 211. Similarly, the second control signal line 222 is connected to the plurality of even buffer sub-circuits 212, and transmits a control signal to the plurality of even read/write control circuits 142 through the even buffer sub-circuits 212, thereby controlling the even read/write control circuits 142. Illustratively, these control signals may include an enable signal to the odd read/write control circuit 141 or the even read/write control circuit 142, a read/write state switching signal, and the like.
In some embodiments, the read-write control circuit 140 is located on one side of the memory cell array 110 in the second direction; the second direction is perpendicular to the first direction.
In some embodiments, the buffer circuit 210 is located on a side of the read/write control circuit 140 away from the memory cell array 110 in the second direction.
Here, the second direction is the Y direction as shown in the above figures, and the first direction is the X direction as shown in the above figures.
As shown in the layout structure of fig. 6, the first memory cell sub-array 111 and the second memory cell sub-array 112 in the memory cell array 110 are arranged at the bottom of the layout at intervals. The read/write control circuit 140 and the buffer circuit 210 are located at one side of the memory cell array 110 in the Y direction and are sequentially connected correspondingly.
In some embodiments, the semiconductor structure further comprises:
and a control line connected between a plurality of the read/write control circuits 140.
Because some control signals need to be transmitted among the plurality of read/write control circuits 140, control lines are further provided among the read/write control circuits 140. For example, a read/write command signal, an enable signal for reading and writing data, and the like are transmitted between different read/write control circuits.
Because the control lines are connected between the odd read-write control circuit 141 and the even read-write control circuit 142, the odd read-write control circuit 141 and the even read-write control circuit 142 are alternately arranged by using the layout method provided by the embodiment of the disclosure, so that the number and the length of the control lines can be reduced, and the circuit layout is simplified.
As shown in fig. 7, some circuit traces (extending in the X direction) of the second metal layer M2 in the conventional design include an address bus Abus, some control signal lines DrC and data lines YIO in the read/write control circuit, and so on. It can be seen that in the conventional design, the circuit traces occupy a large number of traces of the second metal layer M2, which results in a large layout area and a complicated circuit.
After the improvement based on the above embodiment, the circuit trace (extending along the X direction) of the second metal layer M2 is as shown in fig. 8, and it can be seen that the routing of the second metal layer M2 is obviously reduced, the layout area can be effectively saved, and the complexity of the circuit is reduced.
In addition, an embodiment of the present disclosure further provides a memory, including: a plurality of semiconductor structures as described in any of the embodiments above.
It should be noted that the features disclosed in the various embodiments provided in this disclosure may be combined arbitrarily to obtain new method embodiments or apparatus embodiments without conflict.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not imply an order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or in other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit may be implemented in the form of hardware, or in the form of hardware plus a software functional unit.
The above-described embodiments are merely illustrative of the principles of the present disclosure and their efficacy, and are not intended to limit the disclosure. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present disclosure. Accordingly, it is intended that all equivalent modifications or changes be made by those skilled in the art without departing from the spirit and technical spirit of the present disclosure and be covered by the claims of the present disclosure.

Claims (10)

1. A semiconductor structure, comprising:
a memory cell array including a first memory cell sub-array and a second memory cell sub-array arranged in a first direction;
a first data line group including a plurality of first data lines connected to the first memory cell sub-arrays;
a second data line group including a plurality of second data lines, the second data lines being connected to the second memory cell sub-arrays, the first data lines and the second data lines being arranged at intervals;
the plurality of read-write control circuits comprise a plurality of odd read-write control circuits and a plurality of even read-write control circuits, and the odd read-write control circuits and the even read-write control circuits are sequentially and alternately arranged; wherein
The odd read-write control circuits are respectively connected with first odd data lines in the first data lines and second odd data lines in the second data lines in a one-to-one corresponding mode, and the even read-write control circuits are respectively connected with first even data lines in the first data lines and second even data lines in the second data lines in a one-to-one corresponding mode.
2. The semiconductor structure of claim 1, further comprising:
a buffer circuit, the buffer circuit comprising: and each buffer sub-circuit is connected with one read-write control circuit and is used for transmitting a control signal to the read-write control circuit.
3. The semiconductor structure of claim 2, wherein the plurality of buffer sub-circuits comprises: a plurality of odd buffer sub-circuits and a plurality of even buffer sub-circuits; wherein the content of the first and second substances,
the odd buffer sub-circuit is connected with the odd read-write control circuit; and the even buffer sub-circuit is connected with the even read-write control circuit.
4. The semiconductor structure of claim 3, wherein the number of odd buffered sub-circuits is equal to the number of even buffered sub-circuits;
the number of the odd read-write control circuits is equal to that of the even read-write control circuits.
5. The semiconductor structure of claim 3, further comprising:
the first control signal line is connected with the plurality of odd buffer sub-circuits and used for transmitting control signals of the odd read-write control circuit;
and the second control signal line is connected with the plurality of even buffer sub-circuits and is used for transmitting control signals to the even read-write control circuit.
6. The semiconductor structure according to any one of claims 2 to 4, wherein the read/write control circuit is located on one side of the memory cell array in the second direction; the second direction is perpendicular to the first direction.
7. The semiconductor structure according to claim 5, wherein the buffer circuit is located on a side of the read-write control circuit away from the memory cell array in the second direction; the second direction is perpendicular to the first direction.
8. The semiconductor structure of claim 7, wherein the plurality of buffer sub-circuits are spaced along the first direction.
9. The semiconductor structure of claim 1, further comprising:
and a control line connected between the plurality of read/write control circuits.
10. A memory, comprising:
a plurality of semiconductor structures as claimed in any one of claims 1 to 9.
CN202211244265.7A 2022-10-11 2022-10-11 Semiconductor structure and memory Pending CN115620773A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211244265.7A CN115620773A (en) 2022-10-11 2022-10-11 Semiconductor structure and memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211244265.7A CN115620773A (en) 2022-10-11 2022-10-11 Semiconductor structure and memory

Publications (1)

Publication Number Publication Date
CN115620773A true CN115620773A (en) 2023-01-17

Family

ID=84862137

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211244265.7A Pending CN115620773A (en) 2022-10-11 2022-10-11 Semiconductor structure and memory

Country Status (1)

Country Link
CN (1) CN115620773A (en)

Similar Documents

Publication Publication Date Title
KR910000589B1 (en) Memory system providing a continuous address space
KR100661419B1 (en) Non-volatile semiconductor memory device and semiconductor disk apparatus
US9606907B2 (en) Memory module with distributed data buffers and method of operation
US7027307B2 (en) Clock routing in multiple channel modules and bus systems
EP1194856B1 (en) A memory expansion module including multiple memory banks and a bank control circuit
CN102622192B (en) Weak correlation multiport parallel store controller
JP2007140948A (en) Laminated memory
US20070067579A1 (en) Shared memory device
CN102216992A (en) Mass data storage system with non-volatile memory modules
CN100419901C (en) Memory device having different burst order addressing for read and write operations
US7715269B2 (en) Semiconductor memory device and semiconductor device comprising the same
KR101183739B1 (en) Integrated circuit with multiported memory supercell and data path switching circuitry
CN1328676C (en) Multi-bank memory subsystem employing arrangement of multiple memory modules
US20060198114A1 (en) Interface connection device for connecting a mainboard to a memory card having two series of memory modules
WO2000026917A1 (en) Microelectronic chips
EP0213835A2 (en) Semiconductor memory device
CN114141279A (en) Memory topology
US20090296443A1 (en) Memory device having data paths
CN115620773A (en) Semiconductor structure and memory
US6097664A (en) Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan
CN210271794U (en) Test circuit and memory chip using the same
CA1262492A (en) Computer memory apparatus
CN102237867B (en) Semiconductor module including module control circuit and method for controlling the same
US6601197B1 (en) Semiconductor memory device
KR20040111368A (en) Nonvolatile semiconductor storage device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination