CN115617733A - RapidIO network message conversion method, system and equipment - Google Patents

RapidIO network message conversion method, system and equipment Download PDF

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Publication number
CN115617733A
CN115617733A CN202211629277.1A CN202211629277A CN115617733A CN 115617733 A CN115617733 A CN 115617733A CN 202211629277 A CN202211629277 A CN 202211629277A CN 115617733 A CN115617733 A CN 115617733A
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message
pcie
module
rapidio
idle
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CN115617733B (en
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朱珂
姜海斌
王盼
吴佳骏
朱婧瑀
杨晓龙
刘长江
陈德沅
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Jingxin Microelectronics Technology Tianjin Co Ltd
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Jingxin Microelectronics Technology Tianjin Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a method, a system and equipment for converting RapidIO network messages, wherein the system comprises the following steps: one or more message (i.e., rapidIO message) inbound management channels; the configuration management module is used for initializing a message inbound management channel; a PCIe scheduling module; a PCIe data MWr generation module; a message information storage module; a message content storage module; a message preprocessing module; a RapidIO controller module. The scheme has high intellectualization, can automatically classify the same type of message slices, collects the effective load to the CPU side, can simultaneously support the parallel receiving of a plurality of messages, improves the message processing efficiency in a pipeline mode, and has high user configurability.

Description

RapidIO network message conversion method, system and equipment
Technical Field
The invention relates to the field of electric data processing and integrated circuit design, can be applied to a complex RapidIO network, realizes the conversion of RapidIO message data to PCIe by means of a conversion chip, and particularly relates to a RapidIO network message conversion method, a system and equipment.
Background
The RapidIO protocol and the PCIe protocol are common high-speed serial bus protocols at present, only a few existing CPUs support RapidIO devices to be directly mounted, and the scheme that most CPUs mount RapidIO devices is still connected with the RapidIO devices through PCIe-RapidIO bridge chips arranged outside the PCIe bus.
The RapidIO message as a message class protocol of RapidIO has special structure and transmission mode compared with other protocols of RapidIO. The message can realize the data non-address transmission. For one device, a segment of address space can be mapped through the mailbox (or xmelbox) and the letter in the message, so that the address information isolation between the communication devices is realized. The single group of messages can be transmitted in a slicing mode, the number of the messages is 16 at most, each slice can transmit 256B data at most, and the single group of messages can transmit 4kB data at most.
The existing Message protocol interconversion methods for PCIe and RapidIO generally have two types, one is based on a PCIe-to-RapidIO conversion chip, and the other is realized through an FPGA. The PCIe-to-RapidIO conversion chip is not available in China, and is mostly realized by using foreign chips. In the prior art, a method for mutually converting Message protocols of PCIe and RapidIO realized by an FPGA is a method only used for testing functions of RapidIO interfaces, and has poor conversion performance, for example, a scheme in a patent document of "a system for realizing RapidIO and PCIe data conversion" with a patent authorization publication number of CN208207795U, and another method is a technical scheme provided in "a PCIe and RapidIO data conversion device" with a patent authorization publication number of CN214474972U, for example, the method can adopt the same DMA transmission mode for conversion with other RapidIO protocols, and cannot simultaneously support simultaneous transmission of a plurality of unfinished Message messages. And the specific implementation method of the circuit conversion mode from the Message without RapidIO to PCIe in the available patent or literature is available.
The prior art has simple structure and the following defects:
(1) The method cannot meet the requirement that a single CPU collects messages under a complex RapidIO network, and only supports receiving a group of unfinished message messages; (2) Only the implementation method of the direction from PCIe to RapidIO is described, and the implementation method of the direction from RapidIO to PCIe is not described; (3) The message load is collected at the device end, so that hardware resources are wasted; (4) the bus bandwidth utilization rate is low; (5) low throughput.
Disclosure of Invention
In order to solve at least part of technical problems in the prior art, the invention provides a method, a system and equipment for converting RapidIO network messages, and the messages in the scheme are all message messages under a RapidIO protocol, but not message messages under a PCIe protocol.
Specifically, the invention discloses the following technical scheme:
in one aspect, the present invention provides a RapidIO network message conversion system, which includes:
the system comprises one or more message inbound management channels, a message inbound management channel and a message service management channel, wherein the message inbound management channel is used for performing inbound processing on a message, the message is the message under the RapidIO protocol, and the message is transmitted in a slicing mode;
the configuration management module is used for initializing a message inbound management channel and configuring an FQ starting address of a PCIe side of the CPU, wherein the FQ is an idle pointer queue;
the PCIe scheduling module is used for scheduling the PCIe MWr data message and the descriptor PCIe MWr message and sending the PCIe data message and the descriptor PCIe MWr data message to a PCIe side of the CPU through the PCIe controller module; the MWr packet is a PCIe Memory Write packet, and belongs to one TLP in a PCIe protocol;
a PCIe data MWr generation module, configured to obtain message slice associated information, slice content, and an address of the message slice at the PCIe side of the CPU, generate a PCIe MWr data packet, and send the PCIe data packet to a PCIe scheduling module; the message slice associated information comprises: msgseg, context index address, message slice content address and message slice length in the message slice message; the msgseg is an msgseg domain segment in a message in a RapidIO protocol.
The message information storage module is used for storing message slice associated information;
the message content storage module is used for storing message slice contents;
the message preprocessing module is used for preprocessing the message slice transmitted by the RapidIO controller module, and is respectively connected with the message information storage module and the message content storage module for data interaction;
and the RapidIO controller module is connected with the RapidIO device side and receives the message slice sent by the RapidIO device side.
Preferably, the message inbound management channel further includes:
the PCIe idle pointer prefetching module prefetches an idle pointer at the PCIe side of the CPU based on the FQ starting address;
a PCIe descriptor generation module, configured to generate a descriptor PCIe MWr packet based on the DQ start address; the DQ is a queue for storing descriptors configured at the PCIe side of the CPU;
the idle pointer storage module is used for storing an idle pointer;
and the message context index module is used for establishing a context for the message and monitoring whether all message slices corresponding to a certain context are sent completely.
Preferably, the PCIe data MWr generation module and the message preprocessing module respectively perform data interaction with a message context index module in the message inbound management channel.
Preferably, when there are a plurality of message inbound management channels, a message content storage module is shared.
Preferably, the setting mode of the free pointer of the FQ is as follows:
and distributing a plurality of idle storage areas on the PCIe side of the CPU, wherein the size of each idle storage area is the same, and the head address of each idle storage area is used as an idle pointer of the idle pointer queue FQ.
Preferably, the message preprocessing module for preprocessing the message slice message includes: extracting destid and mbox bit fields in the message, sending the message slice to a corresponding message inbound management channel for processing based on the destid and mbox bit fields, and attaching message slice attribute information.
Preferably, the message slice attribute information includes any combination of destID, sourceID, mbox, lett, msgseg, sszie, msglen, tt, prio and crf domain segments of the message in the RapidIO protocol.
Preferably, after receiving the context establishment request, the message context indexing module firstly matches the existing context, and sets the msgseg flag bit if the matching is successful; if the matching is unsuccessful, checking whether an idle context exists or not and checking whether an idle pointer exists in the idle pointer storage module or not, if the idle context exists and the idle pointer exists, applying for the idle pointer from the idle pointer storage module and establishing a new context, and otherwise, sending a message retransmission signal to the message preprocessing module.
On the other hand, the invention also provides a RapidIO network message conversion method, which is applied to the RapidIO network message conversion system and comprises the following steps:
s1, a configuration management module initializes a message inbound management channel; configuring FQ and DQ starting addresses; the DQ is a queue for storing descriptors configured at the PCIe side of the CPU;
s2, the PCIe idle pointer prefetching module prefetches idle pointers from a PCIe side of the CPU based on the FQ starting address; if the idle pointer exists, the idle pointer is cached in the idle pointer storage module for standby;
s3, the message is transmitted in through the RapidIO controller module, is preprocessed by the message preprocessing module and is determined to be transmitted to the corresponding message inbound management channel;
s4, in the corresponding message inbound management channel, after receiving the context establishment request, the message context index module generates a message retransmission signal or a message normal signal based on the context matching condition and sends the message retransmission signal or the message normal signal to the message preprocessing module;
s5, if the message preprocessing module receives a message retransmission signal, generating a retransmission response, sending the retransmission response to a RapidIO device side through the RapidIO controller module, and finishing the message slice message processing;
if the message normal signal is received, generating a normal response, and sending the response to a RapidIO device side through a RapidIO controller module; meanwhile, the content of the message slice is stored in a message content storage module, and the channel information of the message slice is stored in a message information storage module;
s6, a PCIe data MWr generation module acquires message slice associated information from a message information storage module, acquires an address of the message slice on a CPU PCIe side, acquires data of the message slice from a message content storage module, combines a PCIe MWr data message based on data and PCIe packet rules, sends the data to the CPU PCIe side through a PCIe scheduling module and a PCIe controller module, and feeds back the sent slice msgseg to a message context index module;
and S7, after the message context indexing module monitors that all slices of a certain context are sent, sending the message attribute information and the idle pointer in the context to a PCIe descriptor generating module, wherein the PCIe descriptor generating module generates a descriptor PCIe MWr message based on the DQ initial address, and the descriptor PCIe MWr message is sent to a CPU PCIe side through a PCIe scheduling module and a PCIe controller module.
Preferably, in S4, the generating a message retransmission signal or a message normal signal based on the context matching condition further includes: firstly, matching the existing context, and setting the msgseg flag bit if the matching is successful; if the matching is unsuccessful, checking whether an idle context exists or not and checking whether an idle pointer exists in the idle pointer storage module or not, if any one of the contexts is not, sending a message retransmission signal to the message preprocessing module, and if the context is idle and the pointer is idle, applying for the idle pointer from the idle pointer storage module, establishing a new context, and sending a message normal signal to the message preprocessing module.
In another aspect, the present invention further provides a RapidIO network message conversion device, where the device includes a CPU processor, a conversion chip, and a RapidIO device; the conversion chip is matched with the CPU processor to execute the RapidIO network message conversion method so as to realize the transmission of the message from the RapidIO equipment end to the CPU processor end.
Compared with the prior art, the technical scheme can convert the RapidIO message into the PCIe message and send the PCIe message to the CPU for processing, and has at least the following advantages:
1. the intelligence is improved, the message slices of the same class can be automatically classified through channels and contexts in a mixed message network, and effective loads are accurately collected to the CPU side.
Rapidio to PCIe direction can simultaneously support 128 messages received in parallel.
3. By means of the FQ prefetching mechanism and the context management mechanism, pipeline operation is achieved, bandwidth of a high-speed channel is fully utilized, and message processing efficiency is improved.
4. The user configurability is high, parameters can be distributed according to the requirements of the user, and the storage utilization rate of the CPU is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of the structure and data interaction of an embodiment of the present invention;
FIG. 2 is a flow chart of a method according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be appreciated by those of skill in the art that the following specific examples or embodiments are a series of presently preferred arrangements of the invention to further explain the principles of the invention, and that such arrangements may be used in conjunction or association with one another, unless it is expressly stated that some or all of the specific examples or embodiments are not in association or association with other examples or embodiments. Meanwhile, the following specific examples or embodiments are merely provided as the best mode for setting, and are not to be construed as limiting the scope of the present invention.
The invention aims to provide a method for realizing the design of a circuit for converting RapidIO message into PCIe capable of processing complex RapidIO network message collection, so that the number of message items supported at the same time is more, the transmission efficiency of the message is higher, and the throughput is higher. In this specification, a message is a message, and both have the same meaning.
In this embodiment, we can implement the differentiation and classification of messages through the combination (hereinafter referred to as message info) of the sourceID, destID, mbox, xmbox, letter, etc. information in the message, and the classification mode is that the message slices of the same message info are classified into a class of messages.
In the prior art, for the conversion method from the RapidIO message to the PCIe, the conversion method from other message types of the RapidIO message to the PCIe is executed, and the particularity of the RapidIO message compared with other RapidIO messages is not considered, so that certain limitation is brought to the transmission of the message when the message is processed, and the unique characteristic of the message cannot be fully exerted. In the prior art, under a complex RapidIO network, for example, under the condition that a CPU is connected with multiple RapidIO devices through RapidIO switching equipment, multiple RapidIO device message requests cannot be processed in parallel better, rapidIO bandwidth resources are wasted, and only part of schemes in the prior art describe a realization method for the direction from PCIe to RapidIO, and the method cannot realize reverse conversion.
In a preferred embodiment, the scheme firstly allocates a plurality of free areas at the PCIe side of the CPU, and the size of each free area may be set to 4KB, for example; the first address of the free area is defined as a free pointer; a queue formed by a plurality of idle pointers is defined as an idle pointer queue, and is called FQ below; then, we allocate a continuous space capable of storing several descriptors at the PCIe side of the CPU, which is called DQ, and by querying the descriptors in the DQ, get the reconstructed message attribute information and the memory address of the PCIe side of the CPU where the message is located after reconstruction.
Preferably, the descriptor refers to a data string that is formed by the conversion circuit after all slices of a message are collected and sent to the PCIe side of the CPU and includes an address (i.e., a free pointer allocated to the message) stored by the message on the PCIe side of the CPU and the slice attribute information of the message.
Recombination is further described here: a Message is transmitted in batch by messages of not more than 16 Message slices, a Message slice belonging to a Message establishes a same context in a Message inbound management channel, each context occupies a free pointer, the slice of the same Message is stored in a space with the free pointer as a head address according to the msgseg sequence (the msgseg flag bit in the Message slice can indicate that the current slice is the second slice), when all the Message slices arrive and finish transmitting to the CPU PCIe side, a descriptor is generated and written in the DQ of the CPU PCIe side, and the descriptor includes the basic attribute information of the Message and the position of the Message content on the CPU PCIe side, that is, the free pointer allocated to the Message. The data recombination process occurs at the PCIe side of the CPU, and the conversion circuit calculates the address stored by each slice at the CPU side through the slice length based on the idle pointer of the message to realize the recombination at the CPU side; the specific recombination method of the section can be achieved by using a common method in the field, which is not limited herein as the invention point of the invention and is not described in detail.
Preferably, the invention realizes the management of messages according to channels by classes through a multi-channel structure, and also increases the capability of a conversion circuit to process a plurality of groups of message messages simultaneously; referring to fig. 1, in the multi-message inbound management channel structure in this embodiment, channels are in a parallel relationship, and there is no connection relationship between the channels.
The single channel can receive and process a plurality of groups of message messages simultaneously through the establishment of a context mechanism, and the method can cope with a more complex RapidIO network; the context establishing mechanism is described above, that is, the existing context is matched according to the message slice attribute information, and if the matching is successful, the msgseg of the current slice is recorded; if the matching is unsuccessful, checking whether an idle context exists or not and checking whether an idle pointer exists in the idle pointer storage module or not, if any one of the contexts is not, sending a message retransmission signal to the message preprocessing module, and if an idle context exists and an idle pointer exists, applying for the idle pointer from the idle pointer storage module and establishing a new context, and sending a message normal signal to the message preprocessing module.
All channels share one message content storage module, and message messages belonging to the same group are sliced and recombined on a PCIe storage side of a CPU in a circuit storage temporary storage and CPU storage main memory mode, so that the saving of circuit storage is realized, and the recombination mode is described above; in this embodiment, a mode of obtaining a CPU PCIe side address of a reassembled message slice in advance, collecting a group of message messages, and then sending a group of descriptors to a CPU PCIe side designated address is used, so that full pipeline operation from the message messages to PCIe is realized, and interface bandwidth utilization rate and data throughput are improved.
With reference to fig. 1, in a preferred embodiment, the technical solution provided by the present invention can be implemented by using a RapidIO network message transformation system. The system comprises:
in this embodiment, for example, 8 message inbound management channels may be provided, where the message inbound management channels are used to perform inbound processing on a message, the message is a message under a RapidIO protocol, and the message is transmitted in a slice manner;
a configuration management module, configured to initialize one or more message inbound management channels, and configure a start address of a free pointer queue (FQ for short) on the PCIe side of the CPU;
the PCIe scheduling module is used for scheduling the PCIe MWr data message and the descriptor PCIe MWr message and sending the PCIe data message and the descriptor PCIe MWr data message to a PCIe side of the CPU through the PCIe controller module;
a PCIe data MWr generation module, configured to obtain message slice associated information, slice content, and an address of the message slice at the PCIe side of the CPU, generate a PCIe MWr data packet, and send the PCIe data packet to a PCIe scheduling module;
the message information storage module is used for storing the channel associated information of the message slice;
the message content storage module is used for storing the content of the message slice;
the message preprocessing module is used for preprocessing the message slices transmitted by the RapidIO controller module and is respectively connected with the message information storage module and the message content storage module for data interaction;
and the RapidIO controller module is connected with the RapidIO device side and receives the message sent by the RapidIO device side.
Preferably, the PCIe data MWr generation module and the message preprocessing module respectively perform data interaction with one or more message inbound management channels, and more specifically, perform data interaction with a message context index module in the message inbound management channels.
Preferably, the message inbound management channel further includes:
the PCIe idle pointer prefetching module prefetches an idle pointer at the PCIe side of the CPU based on the FQ starting address;
a PCIe descriptor generation module, configured to generate a descriptor PCIe MWr packet based on the DQ start address; the DQ is a queue for storing descriptors configured at the PCIe side of the CPU;
the idle pointer storage module is used for storing an idle pointer;
and the message context index module is used for establishing a context for the message and monitoring whether all message slices corresponding to a certain context are sent completely.
Preferably, when there are a plurality of message inbound management channels, a message content storage module is shared.
Preferably, the starting address setting mode of the free pointer queue is as follows:
and allocating a plurality of idle storage areas on the PCIe side of the CPU, wherein the size of each idle storage area is the same, and the first address of each idle storage area is used as the content of an idle pointer queue.
Preferably, the message preprocessing module for preprocessing the message includes: extracting destid and mbox bit fields in the message slice, sending the message slice to a corresponding message inbound management channel for processing based on the destid and mbox bit fields, and attaching attribute information in the message slice.
Preferably, after receiving the context establishment request, the message context indexing module firstly matches the existing context, and sets the msgseg flag bit if the matching is successful; if the matching is unsuccessful, checking whether an idle context exists or not and checking whether an idle pointer exists in the idle pointer storage module or not, if any one of the contexts is not, sending a message retransmission signal to the message preprocessing module, and if an idle context exists and an idle pointer exists, applying for the idle pointer from the idle pointer storage module and establishing a new context.
In another specific embodiment, with reference to fig. 1 and 2 and the systems described in the above embodiments, a specific method for performing message conversion according to the solution of the present invention is preferably as follows:
the method comprises the following steps: CPU CPIE side software initializes an inbound management channel through a configuration management module, and configures a Free pointer Queue starting address of the CPU CPIE side, namely the starting address of FQ (Free pointer Queue), and a Descriptor Queue starting address, namely the starting address of DQ (Descriptor Queue); the initialization is to configure information such as an FQ start address, a DQ start address, a start channel, and the like, and the CPU writes corresponding data to a corresponding address in the circuit through the PCIe channel, and here, a specific initialization operation can be implemented using a conventional technique in the art, which is not described again.
Step two: the PCIe idle pointer prefetching module prefetches idle pointers from a PCIe side of a CPU through a PCIe channel based on an FQ starting address, the single maximum prefetching number and the number of idle pointers which can be contained by a circuit can be configured in advance, the configuration mode belongs to the prior art, and details are not repeated here. This prefetch, i.e., read ahead, may be achieved by, for example: the circuit is realized by reading an idle pointer from the FQ starting address and the like according to the FQ starting address and the PCIe MRd message configured by the CPU, and the like, wherein the circuit only needs to realize the function of prefetching.
Step three: and caching the returned prefetched idle pointer into the idle pointer storage module for standby.
Here, a description of a preferred embodiment is made of the free pointer. The free pointer is manufactured by a CPU, a plurality of free pointers form a free pointer queue (FQ), the queue is placed in a storage area, the CPU configures the first address of the area to a circuit through configuration, the first address is the free pointer of the FQ, the circuit reads the free pointer from the CPU side according to the configured address and automatically calculates the address of the next free pointer, namely the size of the queue (namely the size of the storage area) can be set to be the same, and therefore after the previous free pointer is read, the address of the next free pointer can be automatically calculated according to the size of the queue. The above communication between the circuit and the CPU is performed through the PCIe interface, that is, the circuit generates PCIe MRd message read, and the CPU returns PCIe CplD message return data, and this specific read and return may follow the existing PCIe message read and return protocol, and is not described here again.
Step four: the RapidIO message is transmitted from the RapidIO side through the RapidIO controller module, and is preprocessed through the message preprocessing module, preferably, the preprocessing includes: extracting destid and mbox bit fields in the message, determining which channel the message goes to establish a context according to the combination of destid and mbox, and attaching attribute information in the message to the context.
Here, the following method may be preferably adopted to determine the channel to which the message is specifically directed: a channel is demapped according to a self-defined rule, for example, a message with destID of 0 and mbox of 00 goes to a channel 0; and the message with the mbox of 01 is sent to the channel 1. The specific rule can be adjusted according to the actual setting requirement, and is not described in detail herein. The above channel refers to a specific message inbound management channel.
Step five: after receiving the context establishment request, the message context index module of the corresponding channel firstly matches the existing context, if the matching is successful, the specific bitmap bit field of the corresponding msgseg flag bit is set to be 1 to receive the message slice, and the message preprocessing module is informed that the message is normal, and the sequence of the specific bitmap bit field can represent the sequence of the message slice; in this embodiment, a message can be divided into 16 slices at most for transmission, and corresponds to 16 bitmap fields of msgseg, and we indicate that the current slice is the second slice through msgseg in the message; a bitmap is a 16-bit register, a bit of 1 indicates that the slice has arrived, for example, a bit1 bit field 1 indicates that the slice with msgseg of 1 has arrived, a bit2 bit field 1 indicates that the slice with msgseg of 2 has arrived, a bit3 bit field 1 indicates that the slice with msgseg of 3 has arrived, and so on, although this is a preferred way, this may also be represented by other corresponding ways between the bit field order and the slice order, for example, a bit5 bit field represents a slice 1, and such conventional changes are considered to fall within the scope of the present invention. The msgseg belongs to a field of a message in a RapidIO protocol.
If the matching fails, checking whether an idle context exists and whether an idle pointer exists in the idle pointer storage module, if any one condition is not met (namely no idle context and/or no idle pointer exists), informing the message preprocessing module of message retransmission, if the two conditions are met simultaneously, applying for the idle pointer from the idle pointer storage module, establishing a new context, and informing the message preprocessing module that the message is normal.
Here "establish new context" is illustrated by an example: assume that in the initial state, a channel has 16 idle contexts, 0 valid contexts (i.e., contexts that are not already occupied). When a type of message comes, a context is occupied, so that a new context is established, the number of idle contexts is changed to 15, and the number of active contexts is changed to 1. When all the slices of the type of message arrive and are sent to the CPU, the effective context is released, at this time, the effective contexts become 0, and the idle contexts become 16 again. Certainly, in the process of processing the context, message slice messages of other classes are allowed to be transmitted, and messages of other classes apply for a context. The above different classes of message slices refer to slices that do not belong to the same message. Whether the message belongs to a message can be judged by the message info in the message, and the context is inquired based on the judgment.
Step six: if the message preprocessing module receives the retransmission instruction, generating a retransmission response message, and sending the retransmission response message to a RapidIO device side through a RapidIO controller module, wherein the message processing is finished; if a normal instruction is received, generating a normal response message, sending the normal response message to a RapidIO device side through a RapidIO controller module, simultaneously storing the message slice content to a message content storage module, and storing the message slice associated information to the message information storage module.
Step seven: the PCIe data MWr generation module acquires the slice channel information of the message from the message information storage module, inquires and acquires the address of the slice distributed at the CPU side from the context of the corresponding channel according to the context information, acquires the data of the slice from the address of the corresponding message content storage module, combines a PCIe MWr data message according to the data length and the PCIe packet rule, schedules the PCIe MWr data message through the priority of the PCIe scheduling module, sends the PCIe MWr data message to the CPU PCIe side through the PCIe controller module, and stores the slice content in the CPU PCIe side for storage. And simultaneously feeding back the slice msgseg which is finished to be sent to the message context index module. The priority setting can be based on the PCIe protocol general rule, the MWr priority of the general data packet is lower than the descriptor MWr priority, or the priority setting can be adjusted based on the transmission processing requirement.
In a preferred embodiment, the PCIe packet rule may be set as: addresses do not cross 4K boundaries, and are no longer than MPS (max payload size, a parameter of PCIe, as is well known in the art). The 4K boundary is well known in the art and will not be described further herein.
Step eight: and the message context index module transmits the message attribute information and the idle pointer to a PCIe descriptor generation module after monitoring that all slices of a certain context are transmitted completely through the mode of the fifth step, the module generates a descriptor PCIe MWr message according to the DQ address configured by configuration management, the descriptor PCIe MWr message is dispatched through a PCIe dispatch module, the descriptor PCIe MWr message is transmitted to a CPU PCIe side through a PCIe controller module, and the CPU is informed of the position (namely a specific storage address) of the message attribute information and the message content on the CPU PCIe side.
In this embodiment, 8 channels are provided to implement that 8 channels can work in parallel, each channel can process 16 contexts at the same time, and 8 channels are the message inbound management channel 0 to the message inbound management channel 7 in fig. 1. Therefore, rapidIO to PCIe processing of the complicated RapidIO network message can be met.
In yet another specific embodiment, the scheme of the present invention can also be implemented in a device, where the device includes a CPU processor, a conversion chip, and a RapidIO device; the conversion chip cooperates with the CPU processor to execute the RapidIO network message conversion method described in the above embodiment, so as to implement sending of a message from a RapidIO device end to a CPU processor end.
The conversion chip can comprise a corresponding module for executing the RapidIO network message conversion method. Accordingly, each step or several steps of the above-described respective embodiments may be performed by a corresponding module. The modules may be one or more hardware modules specifically configured to perform the respective steps, or implemented by a processor configured to perform the respective steps, or stored within a computer-readable medium for implementation by a processor, or by some combination.
Any process or method descriptions otherwise herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present disclosure includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of implementation of the present disclosure. The processor performs the various methods and processes described above. For example, method embodiments in the present scheme may be implemented as a software program tangibly embodied in a machine-readable medium, such as a memory. In some embodiments, some or all of the software program may be loaded and/or installed via memory and/or a communication interface. When the software program is loaded into memory and executed by a processor, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform one of the methods described above in any other suitable manner (e.g., by means of firmware).
The logic and/or steps otherwise described herein may be embodied in any readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

  1. A RapidIO network message conversion system, characterized in that, the system includes:
    the system comprises one or more message inbound management channels, a message inbound management channel and a message service module, wherein the message inbound management channel is used for inbound processing of a message, the message is a message under a RapidIO protocol, and the message is transmitted in a slicing mode;
    the configuration management module is used for initializing a message inbound management channel and configuring an FQ starting address of a PCIe side of the CPU, wherein the FQ is an idle pointer queue;
    the PCIe scheduling module is used for scheduling the PCIe MWr data message and the descriptor PCIe MWr message and sending the data message and the descriptor PCIe MWr message to a PCIe side of a CPU through the PCIe controller module;
    a PCIe data MWr generation module, configured to obtain message slice associated information, slice content, and an address of the message slice at the PCIe side of the CPU, generate a PCIe MWr data packet, and send the PCIe data packet to a PCIe scheduling module;
    the message information storage module is used for storing message slice associated information; the message slice associated information comprises: msgseg, context index address, message slice content address and message slice length in the message slice message;
    the message content storage module is used for storing message slice contents;
    the message preprocessing module is used for preprocessing the message slices transmitted by the RapidIO controller module and is respectively connected with the message information storage module and the message content storage module for data interaction;
    and the RapidIO controller module is connected with the RapidIO device side and receives the message slice sent by the RapidIO device side.
  2. 2. The system of claim 1, wherein the message inbound management channel further comprises:
    the PCIe idle pointer prefetching module prefetches an idle pointer at the PCIe side of the CPU based on the starting address of the FQ;
    a PCIe descriptor generation module, configured to generate a descriptor PCIe MWr packet based on the starting address of the DQ; the DQ is a queue for storing descriptors configured at the PCIe side of the CPU;
    the idle pointer storage module is used for storing an idle pointer;
    and the message context index module is used for establishing a context for the message and monitoring whether all message slices corresponding to a certain context are sent completely.
  3. 3. The system of claim 2, wherein the PCIe data MWr generation module and the message preprocessing module respectively perform data interaction with a message context index module in the message inbound management channel.
  4. 4. The system of claim 1, wherein the message inbound management channel is plural and shares a message content storage module.
  5. 5. The system of claim 1, wherein the free pointer of the FQ is set in a manner that:
    and allocating a plurality of idle storage areas on the PCIe side of the CPU, wherein the size of each idle storage area is the same, and the head address of each idle storage area is used as an idle pointer of the FQ.
  6. 6. The system of claim 1, wherein the message preprocessing module preprocesses the message slice comprises: extracting destID and mbox bit fields in the message, sending the message slice to a corresponding message inbound management channel for processing based on the destID and mbox bit fields, and attaching message slice attribute information, wherein the message slice attribute information comprises any combination of destID, sourceID, mbox, lett, msgseg, sse, msglen, tt, prio and crf field segments of the message in the RapidIO protocol.
  7. 7. The system of claim 2, wherein the message context indexing module first matches the existing context after receiving the context establishment request, and sets the msgseg flag bit if the matching is successful; if the matching is unsuccessful, checking whether an idle context exists or not and checking whether an idle pointer exists in the idle pointer storage module or not, if the idle context exists and the idle pointer exists, applying for the idle pointer from the idle pointer storage module and establishing a new context, and otherwise, sending a message retransmission signal to the message preprocessing module.
  8. A RapidIO network message conversion method, characterized in that the method is applied to a RapidIO network message conversion system according to any one of claims 1 to 7, and the method comprises:
    s1, a configuration management module initializes a message inbound management channel and configures an FQ and a DQ initial address; the DQ is a queue for storing descriptors configured at the PCIe side of the CPU;
    s2, the PCIe idle pointer prefetching module prefetches idle pointers from a PCIe side of the CPU based on the FQ starting address; if the idle pointer exists, caching the idle pointer into an idle pointer storage module for standby;
    s3, message slice messages are transmitted in through a RapidIO controller module, are preprocessed by a message preprocessing module and are determined to be transmitted to a corresponding message inbound management channel;
    s4, in the corresponding message inbound management channel, after receiving a context establishing request, the message context index module generates a message retransmission signal or a message normal signal based on the context matching condition and sends the message retransmission signal or the message normal signal to the message preprocessing module;
    s5, if the message preprocessing module receives a message retransmission signal, generating a retransmission response, sending the retransmission response to a RapidIO device side through the RapidIO controller module, and finishing the message slice message processing;
    if the message normal signal is received, generating a normal response, and sending the response to a RapidIO device side through a RapidIO controller module; meanwhile, the message slice content is stored in a message content storage module, and the message slice associated information is stored in a message information storage module;
    s6, a PCIe data MWr generation module acquires message slice associated information from a message information storage module, acquires an address of the message slice on a CPU PCIe side, acquires the content of the message slice from a message content storage module, combines a PCIe MWr data message based on data and PCIe packet rules, sends the message MWr data message to the CPU PCIe side through a PCIe scheduling module and a PCIe controller module, and feeds back msgseg of the sent slice to a message context index module;
    and S7, after the message context indexing module monitors that all slices of a certain context are sent, sending the message attribute information and the idle pointer in the context to a PCIe descriptor generating module, wherein the PCIe descriptor generating module generates a descriptor PCIe MWr message based on the DQ initial address, and the descriptor PCIe MWr message is sent to a CPU PCIe side through a PCIe scheduling module and a PCIe controller module.
  9. 9. The method of claim 8, wherein in S4, generating a message retransmission signal or a message normal signal based on the context matching condition further comprises:
    firstly, matching the existing context, and setting the msgseg flag bit if the matching is successful; if the matching is unsuccessful, checking whether an idle context exists or not and checking whether an idle pointer exists in the idle pointer storage module or not, if any one of the contexts is not, sending a message retransmission signal to the message preprocessing module, and if an idle context exists and an idle pointer exists, applying for the idle pointer from the idle pointer storage module and establishing a new context, and sending a message normal signal to the message preprocessing module.
  10. The RapidIO network message conversion equipment is characterized by comprising a CPU (central processing unit), a conversion chip and RapidIO equipment; the conversion chip cooperates with the CPU processor to execute the RapidIO network message conversion method according to any one of claims 8 to 9, so as to send a message from the RapidIO device side to the CPU processor side.
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