CN115603864A - Rate matching method and device, and channel interleaving method and device - Google Patents
Rate matching method and device, and channel interleaving method and device Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0067—Rate matching
Abstract
The disclosure provides a rate matching method and device, and a channel interleaving method and device, and relates to the technical field of communication. Determining a target index table corresponding to the bit stream from a plurality of preset index tables according to the length of the bit stream output after encoding, wherein the target index table is used for showing the position offset of a plurality of bits in the bit stream after bit interleaving; and according to the target index table, carrying out bit interleaving on a plurality of bits in the bit stream to obtain rate matching data. Compared with the related technology, the method for obtaining the rate matching data does not contain the null bit, saves the occupation of the memory in the process of knocking out the null bit in the rate matching data, improves the rate matching efficiency, can directly generate channel interleaving data from the rate matching data according to the mapping relation between the rate matching data and the channel interleaving data, and further saves the occupation of the memory in the process of channel interleaving.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a rate matching method and apparatus, and a channel interleaving method and apparatus.
Background
At present, when a terminal and a base station transmit data, a transmitting side needs to perform processes such as coding, rate matching, channel multiplexing, channel interleaving, and the like. In the related art, generally, according to the requirement of a data transmission protocol, the functions of the above processes are divided and the memories are allocated according to the processing sequence, which results in an excessively large amount of used memories, and further causes a communication chip for data transmission to be expensive.
Disclosure of Invention
In view of this, the present disclosure provides a rate matching method and apparatus, and a channel interleaving method and apparatus.
In a first aspect, a method for rate matching is provided, including: determining a target index table corresponding to the bit stream from a plurality of preset index tables according to the length of the bit stream output after encoding, wherein the target index table is used for showing the position offset of a plurality of bits in the bit stream after bit interleaving; and according to the target index table, carrying out bit interleaving on a plurality of bits in the bit stream to obtain rate matching data.
In some embodiments, bit interleaving a plurality of bits in a bit stream according to a target index table to obtain rate-matched data comprises: determining position indexes of a plurality of bits in the bit stream after bit interleaving according to the target index table; and arranging a plurality of bits in the bit stream according to the position indexes to obtain the rate matching data.
In some embodiments, determining a position index of a plurality of bits in the bitstream after bit interleaving according to the target index table includes: determining, for each bit of a plurality of bits, a row index, a column index, and an inter-column permutation pattern of the bit in the bitstream; and according to the row index, the column index and the inter-column replacement mode, combining the row number of the bit stream and the target index table to obtain the position index of the bit in the bit stream after bit interleaving.
In some embodiments, determining, for each bit of the plurality of bits, a row index, a column index, and an inter-column permutation pattern of the bit in the bitstream comprises: for each bit in the plurality of bits, determining a row index and a column index of the bit according to position information of the bit in the bit stream; an inter-column permutation pattern of bits is determined according to a column index of the bits.
In some embodiments, before determining a target index table corresponding to a bitstream from a plurality of preset index tables according to a length of the bitstream output after encoding, the method further includes: and creating a plurality of preset index tables according to the sub-block interleaving modes of the bit streams with different lengths, wherein the preset index tables and the bit streams with different lengths have corresponding relations.
In some embodiments, the bitstream comprises a systematic bitstream, a first parity bitstream, and a second parity bitstream; the target index table includes a first position offset amount for indicating a position offset of a plurality of bits in the systematic bitstream and a second position offset amount for indicating a position offset of a plurality of bits in the first parity bitstream and the second parity bitstream.
In a second aspect, a channel interleaving method is provided, including: establishing a channel interleaving index according to the position of each bit data in the rate matching data, wherein the rate matching data is obtained based on the method of the first aspect, and the channel interleaving index is used for showing the mapping relation between the rate matching data and the channel interleaving data; and arranging each bit data in the rate matching data according to the channel interleaving index to obtain channel interleaving data.
In a third aspect, a rate matching apparatus is provided, including: the determining module is used for determining a target index table corresponding to the bit stream from a plurality of preset index tables according to the length of the bit stream output after encoding, wherein the target index table is used for showing the position offset of a plurality of bits in the bit stream after bit interleaving; and the output module is used for carrying out bit interleaving on a plurality of bits in the bit stream according to the target index table to obtain the rate matching data.
In a fourth aspect, a channel interleaving apparatus is provided, which includes: the establishing module is used for establishing a channel interleaving index according to the position of each bit data in the rate matching data, the rate matching data is obtained based on the method of the first aspect, and the channel interleaving index is used for showing the mapping relation between the rate matching data and the channel interleaving data; and the output module is used for arranging each bit data in the rate matching data according to the channel interleaving index to obtain channel interleaving data.
In a fifth aspect, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions for the processor; wherein the processor is configured to perform the method of the first or second aspect described above via execution of the executable instructions.
A sixth aspect provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of the first or second aspect described above.
According to the rate matching method provided by the embodiment of the disclosure, a target index table corresponding to a bit stream can be determined from a plurality of preset index tables according to the length of the bit stream output after encoding, and the target index table is used for showing the position offset of a plurality of bits in the bit stream after bit interleaving. And then, according to the target index table, bit interleaving is carried out on a plurality of bits in the bit stream to obtain rate matching data. Because the bits in the bit stream are directly arranged according to the index in the embodiment of the disclosure, no empty bit is contained in the obtained rate matching data, and compared with the related art, the occupation of a memory in the processes of subblock interleaving and empty bit knockout in the rate matching process is saved, and the rate matching efficiency is improved. In addition, because the rate matching data output by the method does not have empty bits, the channel interleaving data can be directly generated by the rate matching data according to the mapping relation between the rate matching data and the channel interleaving data, and the occupation of a memory in channel interleaving in the related technology is further saved.
Drawings
Fig. 1 is a schematic diagram of a system architecture of a rate matching method in an embodiment of the present disclosure.
Fig. 2 is a flow chart illustrating a rate matching method in an embodiment of the present disclosure.
Fig. 3 is a schematic diagram illustrating a preset index table according to an embodiment of the disclosure.
Fig. 4 shows a schematic diagram of a process of bit interleaving in the embodiment of the present disclosure.
Fig. 5 is a flowchart illustrating a channel interleaving method in an embodiment of the disclosure.
Fig. 6 is a schematic structural diagram of a rate matching apparatus in an embodiment of the present disclosure.
Fig. 7 shows a schematic structural diagram of a channel interleaving apparatus in an embodiment of the present disclosure.
Fig. 8 shows a schematic structural diagram of an electronic device in an embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
In the aspect of radio access, after data of a transmission channel is encoded, for example, channel encoding in 5G/4G technology, if data traffic of the transmission channel may be different from data amount that can be carried by an air interface resource, rate matching is performed. The basic principle of rate matching is based on a 32-column matrix, firstly inputting according to rows, performing sub-block interleaving after initially introducing empty bits (filling the empty positions of the row-column matrix), then outputting according to the columns to form an annular data stream, finally performing puncturing or repeated bit selection output according to the bit number (data quantity) which can be carried by air interface resources, and simultaneously removing the selected empty bits through puncturing. However, these empty bits have no practical meaning and occupy a large amount of memory, thereby reducing the rate matching efficiency.
In view of this, the present disclosure provides a scheme that can determine a target index table corresponding to a bitstream from a plurality of preset index tables according to a length of the bitstream output after encoding. And then, according to the target index table, bit interleaving is carried out on a plurality of bits in the bit stream, and the rate matching data without null bits can be obtained. Therefore, the occupation of the memory in the process of subblock interleaving and empty bit knockout in the rate matching process is saved, and the rate matching efficiency is improved.
A system architecture of the rate matching method in the embodiment of the present disclosure will be described below with reference to fig. 1.
Fig. 1 shows an exemplary system architecture diagram of a rate matching method or rate matching apparatus applied to an embodiment of the present disclosure. As shown in FIG. 1, the system architecture 100 includes a processor 101 and a memory 102.
The processor 101 is configured to execute program instructions, for example, to perform the rate matching method provided in the present disclosure. The memory 102 may exist in the system architecture 100 as various forms of program storage units or data storage units, such as a hard disk, read Only Memory (ROM), random Access Memory (RAM), which can be used to store various data files used during processing and/or execution of the rate matching method by the processor, as well as possible program instructions executed by the processor. Although not shown in the figures, the system architecture 100 may also include an input/output component to support input/output data flow between the rate matching device to which the system architecture 100 is applied and devices downstream thereof. In addition, the rate matching device to which the system architecture 100 is applied can also send and receive information and data from the network through the communication port.
Although in fig. 1, the processor 101 and the memory 102 are presented as separate modules, those skilled in the art will appreciate that the apparatus modules described above may be implemented as separate hardware devices, or may be integrated into one or more hardware devices, such as integrated into a smart watch or other smart device. The specific implementation of various hardware devices should not be considered as a limitation on the scope of the present disclosure, as long as the principles described in the present disclosure can be implemented.
The present exemplary embodiment will be described in detail below with reference to the drawings and examples.
First, the embodiments of the present disclosure provide a rate matching method, which may be executed by any electronic device with computing processing capability.
Fig. 2 is a schematic flow chart of a rate matching method in an embodiment of the present disclosure, and as shown in fig. 2, the rate matching method provided in the embodiment of the present disclosure includes the following steps.
S201, according to the length of the coded output bit stream, determining a target index table corresponding to the bit stream from a plurality of preset index tables.
It should be noted that the coding in the embodiment of the present disclosure may be channel coding in a 5G technology, and may also be channel coding in a 4G technology, which is not limited in the embodiment of the present disclosure.
It should be noted that the bit stream may be a bit stream obtained by encoding an original bit stream at the sending end, and is used for rate matching processing and air interface downlink transmission.
Illustratively, after the original bit stream of the downlink transmission data is subjected to the encoding process of the transmission channel, a corresponding three-way bit stream, i.e., a system bit stream, a first parity bit stream, and a second parity bit stream, may be formed. The three bit streams have the same length, and each bit stream comprises a plurality of bits corresponding to downlink transmission data with practical significance.
In the related art, since sub-block interleaving needs to be performed on the three bit streams in the process of rate matching, not only the memory is occupied, but also meaningless null bits are filled in bit data. Specifically, since the total number of columns of the sub-block interleaver is determined, that is, 32 columns. Therefore, in the related art, when the total length of the bit sequence formed by the bits contained in each bit stream is smaller than the total length of the sub-block interleaver through which the bit stream will pass (i.e., the sub-block interleaver is not filled), a certain number of null bits are added to fill the null positions of the rows of the sub-block interleaver that are not filled with bits, so as to form a matrix based on the minimum rows of the bits, thereby being used for rate matching.
The embodiment of the disclosure does not need the sub-block interleaving process, so that not only the occupation of the sub-block interleaving process to the memory is saved, but also the occupation of meaningless empty bits to the memory is saved.
In some embodiments, as known from the related protocol standard, since the total column number of the sub-block interleaver is fixed to 32 columns, the number of the empty bits padded for each bit stream during the sub-block interleaving may be 4, 12, 20 or 28, which are four cases. Therefore, four kinds of preset index tables can be created for the bit streams of the above four cases.
For example, after the preset index table is created, a target index table corresponding to the bitstream may be determined according to the length of the bitstream.
Specifically, according to the length of the bit stream, the number of empty bits required to be filled in the sub-block interleaving process can be calculated. For example, the bit stream has a length of 76 bits, and the number of bits of the unfilled rows in the sub-block interleaver can be obtained by dividing 76 by the total column number of the block interleaver and taking the remainder. In this example, 76 divided by 32 to 12, i.e., the unfilled rows in the sub-block interleaver, have 12 bits. Then, in order to fill up the sub-block interleaver, 20 bits need to be padded again in the unfilled rows. It can be seen that, when the length of the bit stream is 76 bits, the predetermined index table corresponds to the empty bit number of 20.
It should be understood that the sub-block interleaver and the padding process thereof mentioned above are only used for illustrating the corresponding relationship between the preset index table and the bit stream, and are not used for limiting the embodiments of the present disclosure. When the method provided by the embodiment of the disclosure is implemented specifically, the filling process is not required to be performed, and a sub-block interleaver is not required to be constructed, so that a large amount of memory occupation can be saved, and the rate matching efficiency can be improved.
It should be noted that the target index table is a preset index table corresponding to the bit stream, and is used for showing a position offset of a plurality of bits in the bit stream after bit interleaving.
Specifically, since the same number of null bits are distributed in the same group of sub-blocks, a plurality of preset index tables may be created according to the arrangement of different numbers of null bits in the bitstream, and then the target index table corresponding to the bitstream is determined according to the number of null bits.
In some embodiments, the predetermined index table may be constructed by assuming the effect of the filled null bits on other non-null bit positions during the rate matching process.
Exemplarily, fig. 3 illustrates a schematic diagram of a preset index table provided by an embodiment of the present disclosure. As shown in fig. 3, the predetermined index table is applicable to the case where the number of null bits is 20.
In fig. 3, the first row is an inter-column permutation pattern of the column index, the second row is a first position offset amount corresponding to the inter-column permutation pattern, and the third row is a second position offset amount corresponding to the inter-column permutation pattern. Wherein the first position offset amount is used for showing the position offset of a plurality of bits in the system bit stream, and the second position offset amount is used for showing the position offset of a plurality of bits in the first check bit stream and the second check bit stream.
S202, according to the target index table, bit interleaving is carried out on a plurality of bits in the bit stream, and rate matching data are obtained.
Specifically, according to the target index table, the position index of a plurality of bits in the bit stream after bit interleaving can be determined. And arranging a plurality of bits in the bit stream according to the position indexes to obtain the rate matching data.
In some embodiments, for each bit of the plurality of bits, a row index, a column index, and an inter-column permutation pattern of the bit in the bitstream are determined. And combining the row number of the bit stream and the target index table according to the row index, the column index and the inter-column replacement mode to obtain the position index of the bit in the bit stream after bit interleaving. Wherein the row index and the column index of the bit can be determined according to the position information of the bit in the bit stream. The inter-column permutation pattern of bits may be determined according to the column index of the bits.
Illustratively, the position index of each bit in each bitstream can be obtained by traversing the following equations (1) to (7). Wherein, the first and the second end of the pipe are connected with each other,iis an integer for representing the position index of the bit in each bit stream, and since the position index number in the bit stream is 0 at the start position, the following traversal procedure is performediSequentially take 0 to (D-1)，DIndicating the length of each bit stream (i.e., the number of bits in each bit stream) that is output after encoding.
Wherein, the first and the second end of the pipe are connected with each other,rowis the row index of the bits in the systematic bit stream and the first check bit stream,row 1 is the row index of the bits in the second parity bit stream.colIs the column index of the bits in the systematic bit stream and the first check bit stream,col 1 is the column index of the bits in the second parity bit stream.floorFor indicating a rounding down of the result,modfor representing a modulo operation.P(col)For representingcolThe corresponding inter-column permutation pattern (obtained by the query protocol),P(col 1 )for representingcol 1 A corresponding inter-column permutation pattern (obtained by a query protocol), wherein,<P(0)~P(31)>respectively corresponding to a value of< 0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31>。idx 0 Indicating the position index of the bit in the systematic bit stream.idx 1 Indicating the position index of the bit in the first check bit stream.idx 2 Indicating the position index of the bit in the second parity bit stream.N D Indicating the number of null bits that need to be padded to place the bit stream into the sub-block interleaver.RTCRepresenting the total number of rows occupied when placing the bit stream into the sub-block interleaver.colOffset 0 AndcolOffset 1 respectively representing a first position offset amount and a second position offset amount determined by looking up the target index table.
It should be noted that the index number of the position in the rate matching data starts from 0, i.e. the index number 1 corresponds to the second position in the rate matching data. When bits of each bitstream are arranged according to the position index, bits in the systematic bitstream may be first arranged according to their position indexes. After the bits in the system bit stream are arranged, the bits in the first check bit stream and the bits in the second check bit stream are arranged according to the position indexes of the bits respectively, so that the rate matching data is obtained. That is, the position index of the bit in the first parity bit stream and the position index of the bit in the second parity bit stream show the index position after the bit of the aligned systematic bit stream and also start from 0. Illustratively, the bit position index 1 in the first parity bit stream corresponds to the second position after the bit of the arranged systematic bit stream.
According to the rate matching method provided by the embodiment of the disclosure, a target index table corresponding to a bit stream can be determined from a plurality of preset index tables according to the length of the bit stream output after encoding, and the target index table is used for showing the position offset of a plurality of bits in the bit stream after bit interleaving. And then, according to the target index table, bit interleaving is carried out on a plurality of bits in the bit stream to obtain rate matching data. Because the bits in the bit stream are directly arranged according to the index in the embodiment of the disclosure, no empty bit is contained in the obtained rate matching data, and compared with the related art, the occupation of a memory in the processes of subblock interleaving and empty bit knockout in the rate matching process is saved, and the rate matching efficiency is improved.
For ease of understanding, the process of bit interleaving bits according to the index table in the embodiment of the present disclosure will be described below with reference to fig. 4.
Fig. 4 shows a schematic diagram of a process of bit interleaving bits in the embodiment of the present disclosure. To facilitate an intuitive illustration of the bit interleaving process in the disclosed embodiments, the bits in the systematic bit stream are shown in bold and the bits in the first parity bit stream are shown in underlined form.
Specifically, the three-way bit streams in fig. 4 are each 76 in length, and the position indexes of the respective bits in the system bit stream, the first parity bit stream, and the second parity bit stream are first calculated according to equations (1) to (7) above, respectively.
Illustratively, taking the first bit in the systematic bitstream, the first parity bitstream, and the second parity bitstream, respectively, as an example (i.e., the position index in the bitstream is 0), the index position in the rate matching data can be calculated as follows.
Specifically, leti=0，N D =20，RTC=3(As mentioned above, the number of columns of the sub-block interleaver is fixed to 32 columns, and if 76 bits are put into the sub-block interleaver, 3 rows are occupied), as can be seen from the above equations (1) to (7),row=0，col=20，P (col)=5，row 1 =0，col 1 =19，P(col 1 )=25. As can be seen in connection with the index table shown in figure 3,colOffset 0 (5)=4，colOffset 1 (5)=8，colOffset 1 (33). Therefore, the number of the first and second electrodes is increased,idx 0 =5×3-colOffset 0 (5)=11，idx 1 =5×3×2- colOffset 1 (5)=22，idx 2 =25×3×2+1-colOffset 1 (25)=118。
note that, similarly to the position index number in the bit stream, the position index number in the rate matching data also starts from 0. For example, in the above examplei=0Is calculated to obtainidx 0 =11，That is, the first bit in the systematic bit stream has a position index of 11 in the rate matching data, which corresponds to the 12 th position of the rate matching data, i.e., the 12 th column in row 1 (the position index number in the rate matching data starts from 0, so the actual position corresponding to the position index 11 is 11+1= 12).
It is noted that, according to the protocol, in the rate matching data, since the bits corresponding to the first parity bit stream and the second parity bit stream are interleaved after the bits in the system bit stream, the obtained bits areidx 1 Andidx 2 the position index shown is the position index after the systematic bit. That is, the first parity bitstream and the second parity bitstream share the same position index for the parity bitstream in the rate matching data, and the position index for the parity bitstream starts after the systematic bitstream and starts again from 0. For example, in the above exampleidx 1 =22That is, the position index of the first bit in the first parity bit stream after the systematic bit stream is 22, which corresponds to the 99 th position of the entire rate matching data, that is, the 3 rd position in the 4 th row (starting from 0, so the position corresponding to the position index 22 is 22+1=23, and knowing that the position index of the first parity bit stream after the systematic bit stream, the systematic bit stream contains 76 bits, that is, the first parity bit streamThe actual position of the first bit in the rate matched data is 23+ 76=99).
The embodiment of the disclosure can directly calculate the output position index of each bit in the coded and output bit stream, and directly write each bit into the memory according to the position index, thereby directly obtaining the rate matching data in the memory, and saving the memory occupied by the related technology in the middle process.
It is noted that since the present disclosure can directly obtain the position of each bit in the rate matching data through the position index. Therefore, in the process of bit stream transmission, each bit in the bit stream can be filled to a corresponding position according to the position index of the bit stream without waiting for the completion of bit stream transmission. Therefore, the rate matching method provided by the embodiment of the disclosure has the advantage of high efficiency.
Based on the same inventive concept, in an application scenario of the present disclosure, a channel interleaving method is also provided.
Fig. 5 shows a flowchart of a channel interleaving method provided in the embodiment of the present disclosure, and as shown in fig. 5, the method includes the following steps.
S501, according to the position of each bit data in the rate matching data, a channel interleaving index is established.
It should be noted that the rate matching data in the embodiment of the present disclosure is obtained based on the rate matching method shown in fig. 2, and the details of the present disclosure are not repeated here.
Note that the channel interleaving index is used to show the mapping relationship between the rate matching data and the channel interleaving data.
Illustratively, when channel interleaving, the bit data in the rate matching data are sequentially arranged in the subcarriers according to a time domain first and a frequency domain second, and the number of bits in each frequency domain is the same. Because no empty bit exists in the rate matching data output by the rate matching method provided by the disclosure, bit data can be directly selected in the rate matching data according to an arithmetic progression mode. For example, in a modulation scheme for Quadrature Phase Shift Keying (QPSK), bit data can be obtained from rate-matched data in an arithmetic series with a tolerance of 24.
In some embodiments, a channel interleaving index of bit data in each arithmetic sequence may be established according to the permutation of each arithmetic sequence acquired in sequence.
Specifically, in the channel interleaving index, the bit data at the same position in each arithmetic progression is allocated to the same time domain, and the precedence order in the frequency domain is allocated according to the acquisition order of the arithmetic progression.
And S502, arranging each bit data in the rate matching data according to the channel interleaving index to obtain channel interleaving data.
It should be noted that the rate matching data can be directly output as channel interleaving data by arranging the bit data of the same time domain on the frequency domain according to the sequence obtained by the arithmetic progression.
It should be noted that, since the main inventive concept and the effect of the implementation of the embodiment of the present disclosure are similar to the rate matching method embodiment shown in fig. 2, specific implementation details may refer to the channel interleaving method embodiment shown in fig. 2. Because no empty bit exists in the rate matching data output by the method, the channel interleaving data can be directly generated by the rate matching data according to the mapping relation between the rate matching data and the channel interleaving data, and the occupation of the memory in channel interleaving in the related technology is further saved.
Fig. 6 is a schematic structural diagram of a rate matching apparatus in an embodiment of the present disclosure, and as shown in fig. 6, the rate matching apparatus 600 includes: a determination module 601 and an output module 602.
Specifically, the determining module 601 is configured to determine, according to the length of the encoded output bitstream, a target index table corresponding to the bitstream from a plurality of preset index tables, where the target index table is used to show position offsets of a plurality of bits in the bitstream after bit interleaving. The output module 602 is configured to perform bit interleaving on multiple bits in the bit stream according to the target index table to obtain rate matching data.
In some embodiments, the output module 602 is further configured to determine, according to the target index table, a position index of a plurality of bits in the bitstream after bit interleaving; and arranging a plurality of bits in the bit stream according to the position indexes to obtain the rate matching data.
In some embodiments, the output module 602 is further configured to, for each bit of the plurality of bits, determine a row index, a column index, and an inter-column permutation pattern of the bit in the bitstream; and according to the row index, the column index and the inter-column replacement mode, combining the row number of the bit stream and the target index table to obtain the position index of the bit in the bit stream after bit interleaving.
In some embodiments, the output module 602 is further configured to determine, for each bit of the plurality of bits, a row index and a column index of the bit according to position information of the bit in the bitstream; an inter-column permutation pattern of bits is determined according to a column index of the bits.
In some embodiments, the determining module 601 is further configured to create a plurality of preset index tables according to sub-block interleaving manners of bit streams with different lengths, where the preset index tables and the bit streams with different lengths have corresponding relationships.
In some embodiments, the bitstream comprises a systematic bitstream, a first parity bitstream, and a second parity bitstream; the target index table includes a first position offset amount for indicating a position offset of a plurality of bits in the systematic bitstream and a second position offset amount for indicating a position offset of a plurality of bits in the first parity bitstream and the second parity bitstream.
It should be noted that, when the rate matching apparatus provided in the foregoing embodiment is used for rate matching, only the division of the functional modules is illustrated, and in practical applications, the function distribution may be completed by different functional modules according to needs, that is, the internal structure of the apparatus is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the rate matching apparatus and the rate matching method provided in the above embodiments belong to the same concept, and specific implementation processes thereof are described in the method embodiments and are not described herein again.
Based on the same inventive concept, the embodiment of the present disclosure further provides a channel interleaving apparatus, such as the following embodiments. Since the principle of solving the problem in this embodiment is similar to that in the above-described embodiment of the rate matching method, the implementation of this embodiment may refer to the implementation of the above-described embodiment of the rate matching method, and repeated details are not described again.
Fig. 7 is a schematic structural diagram of a channel interleaving apparatus in an embodiment of the present disclosure, and as shown in fig. 7, the channel interleaving apparatus 700 includes: a setup module 701 and an output module 702.
Specifically, the establishing module 701 is configured to establish a channel interleaving index according to a position of each bit data in the rate matching data, where the rate matching data is obtained based on the rate matching method provided by the present disclosure, and the channel interleaving index is used to show a mapping relationship between the rate matching data and the channel interleaving data. The output module 702 is configured to arrange each bit data in the rate matching data according to the channel interleaving index to obtain channel interleaving data.
As will be appreciated by one skilled in the art, aspects of the present disclosure may be embodied as a system, method or program product. Accordingly, various aspects of the present disclosure may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.
An electronic device 800 according to this embodiment of the disclosure is described below with reference to fig. 8. The electronic device 800 shown in fig. 8 is only an example and should not bring any limitations to the functionality and scope of use of the embodiments of the present disclosure.
As shown in fig. 8, electronic device 800 is in the form of a general purpose computing device. The components of the electronic device 800 may include, but are not limited to: the at least one processing unit 810, the at least one memory unit 820, and a bus 830 that couples the various system components including the memory unit 820 and the processing unit 810.
Where the memory unit stores program code, the program code may be executed by the processing unit 810 to cause the processing unit 810 to perform steps according to various exemplary embodiments of the present disclosure as described in the "exemplary methods" section above in this specification.
In some embodiments, the processing unit 810 may perform the following steps of the above-described rate matching method embodiments: determining a target index table corresponding to the bit stream from a plurality of preset index tables according to the length of the bit stream output after encoding, wherein the target index table is used for showing the position offset of a plurality of bits in the bit stream after bit interleaving; and according to the target index table, carrying out bit interleaving on a plurality of bits in the bit stream to obtain rate matching data.
In other embodiments, the processing unit 810 may further perform the following steps of the above channel interleaving method embodiment: establishing a channel interleaving index according to the position of each bit data in the rate matching data, wherein the rate matching data is obtained based on the rate matching method provided by the disclosure, and the channel interleaving index is used for showing the mapping relation between the rate matching data and the channel interleaving data; and arranging each bit data in the rate matching data according to the channel interleaving index to obtain channel interleaving data.
The memory unit 820 may include readable media in the form of volatile memory units, such as a random access memory unit (RAM) 8201 and/or a cache memory unit 8202, and may further include a read only memory unit (ROM) 8203.
The storage unit 820 may also include a program/utility 8204 having a set (at least one) of program modules 8205, such program modules 8205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.
The electronic device 800 may also communicate with one or more external devices 840 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device 800, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 800 to communicate with one or more other computing devices. Such communication may occur via input/output (I/O) interfaces 850. Also, the electronic device 800 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) via the network adapter 860. As shown in FIG. 8, the network adapter 860 communicates with the other modules of the electronic device 800 via the bus 830. It should be appreciated that although not shown, other hardware and/or software modules may be used in conjunction with the electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.
Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.
In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium, which may be a readable signal medium or a readable storage medium. On which a program product capable of implementing the above-described method of the present disclosure is stored. In some possible embodiments, various aspects of the disclosure may also be implemented in the form of a program product comprising program code for causing a terminal device to perform the steps according to various exemplary embodiments of the disclosure described in the above-mentioned "exemplary methods" section of this specification, when the program product is run on the terminal device.
More specific examples of the computer-readable storage medium in the present disclosure may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
In the present disclosure, a computer readable storage medium may include a propagated data signal with readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Alternatively, program code embodied on a computer readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
In particular implementations, program code for carrying out operations of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Through the description of the above embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, and may also be implemented by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (11)
1. A method of rate matching, comprising:
determining a target index table corresponding to the bit stream from a plurality of preset index tables according to the length of the bit stream output after encoding, wherein the target index table is used for showing the position offset of a plurality of bits in the bit stream after bit interleaving;
and performing bit interleaving on the plurality of bits in the bit stream according to the target index table to obtain rate matching data.
2. The method of claim 1, wherein the bit interleaving the plurality of bits in the bitstream according to the target index table to obtain rate-matched data comprises:
determining position indexes of the plurality of bits in the bit stream after bit interleaving according to the target index table;
and arranging the plurality of bits in the bit stream according to the position indexes to obtain rate matching data.
3. The method of claim 2, wherein determining the position index of the plurality of bits in the bitstream after bit interleaving according to the target index table comprises:
determining, for each bit of the plurality of bits, a row index, a column index, and an inter-column permutation pattern of the bit in the bitstream;
and obtaining the position index of the bit in the bit stream after bit interleaving by combining the row number of the bit stream and the target index table according to the row index, the column index and the inter-column permutation mode.
4. The method of claim 3, wherein the determining, for each bit of the plurality of bits, a row index, a column index, and an inter-column permutation pattern of the bit in the bitstream comprises:
for each bit of the plurality of bits, determining a row index and a column index for the bit from position information of the bit in the bitstream;
and determining an inter-column permutation mode of the bit according to the column index of the bit.
5. The method according to claim 1, before determining a target index table corresponding to the bitstream from a plurality of preset index tables according to a length of the bitstream after encoding, further comprising:
and creating the preset index tables according to the sub-block interleaving modes of the bit streams with different lengths, wherein the preset index tables and the bit streams with different lengths have corresponding relations.
6. The method of claim 1 or 5, wherein the bitstream comprises a systematic bitstream, a first parity bitstream, and a second parity bitstream;
the target index table includes a first position offset amount and a second position offset amount, the first position offset amount is used for showing position offsets of a plurality of bits in the system bit stream, and the second position offset amount is used for showing position offsets of a plurality of bits in the first check bit stream and the second check bit stream.
7. A method of channel interleaving, comprising:
establishing a channel interleaving index according to the position of each bit data in rate matching data, wherein the rate matching data is obtained based on the method of any one of claims 1 to 6, and the channel interleaving index is used for showing the mapping relation between the rate matching data and the channel interleaving data;
and arranging each bit data in the rate matching data according to the channel interleaving index to obtain channel interleaving data.
8. A rate matching apparatus, comprising:
a determining module, configured to determine, according to a length of a bitstream that is output after encoding, a target index table corresponding to the bitstream from a plurality of preset index tables, where the target index table is used to show position offsets of a plurality of bits in the bitstream after bit interleaving;
and the output module is used for carrying out bit interleaving on the plurality of bits in the bit stream according to the target index table to obtain rate matching data.
9. A channel interleaving apparatus, comprising:
a building module, configured to build a channel interleaving index according to a position of each bit data in rate matching data, where the rate matching data is obtained based on the method in any one of claims 1 to 6, and the channel interleaving index is used to show a mapping relationship between the rate matching data and the channel interleaving data;
and the output module is used for arranging each bit data in the rate matching data according to the channel interleaving index to obtain channel interleaving data.
10. An electronic device, comprising:
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the method of any of claims 1-7 via execution of the executable instructions.
11. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method of any one of claims 1 to 7.
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