CN115603747A - Quantization method, analog-to-digital converter, electronic device, and computer-readable storage medium - Google Patents
Quantization method, analog-to-digital converter, electronic device, and computer-readable storage medium Download PDFInfo
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Abstract
The present disclosure provides a quantization method, an analog-to-digital converter, an electronic device, and a computer-readable storage medium, the method including obtaining a signal to be quantized and a reference signal, wherein the reference signal includes a threshold decision section reference signal and a quantization section reference signal; carrying out threshold judgment on the signal to be quantized by utilizing the reference signal of the threshold judgment section, and determining a plurality of sections of effective signals to be quantized; and quantizing any effective signal to be quantized in the multiple effective quantized signals by using the quantized segment reference signals to obtain a quantization result of the signal to be quantized. The quantization speed can be improved according to the embodiments of the present disclosure.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a quantization method, an analog-to-digital converter, an electronic device, and a computer-readable storage medium.
Background
A single slope ADC (Analog-to-Digital Converter) compares an input Analog voltage signal with a single slope signal, converts input voltage information into time information, and converts the time information into a Digital code, thereby converting the Analog signal into a Digital signal. The single slope ADC has the advantages of simple structure, high expandability, high precision and the like, and can be applied to the fields of sensors, instruments, image recognition and the like.
Disclosure of Invention
The disclosure provides a quantization method, an analog-to-digital converter, an electronic device, and a computer-readable storage medium.
In a first aspect, the present disclosure provides a quantization method, the method comprising: acquiring a signal to be quantized and a reference signal, wherein the reference signal comprises a threshold judgment section reference signal and a quantization section reference signal;
carrying out threshold judgment on the signal to be quantized by utilizing the reference signal of the threshold judgment section, and determining a plurality of sections of effective signals to be quantized;
and quantizing any effective signal to be quantized in the multiple effective quantized signals by utilizing the quantized segment reference signals to obtain a quantization result of the signal to be quantized.
In a second aspect, the present disclosure provides an analog-to-digital converter comprising:
an obtaining module, configured to obtain a signal to be quantized and a reference signal, where the reference signal includes a threshold decision segment reference signal and a quantization segment reference signal;
the judging module is used for utilizing the threshold judging section reference signal to carry out threshold judgment on the signal to be quantized and determining a plurality of sections of effective signals to be quantized;
and the quantization module is used for quantizing any effective signal to be quantized in the multiple sections of effective quantized signals by utilizing the quantized section reference signals to obtain a quantization result of the signal to be quantized.
In a third aspect, the present disclosure provides an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executable by the at least one processor to enable the at least one processor to perform the quantization method described above.
In a fourth aspect, the present disclosure provides a computer readable storage medium having stored thereon a computer program, wherein the computer program, when executed by a processor/processing core, implements the quantization method described above.
In the quantization method provided by the embodiment of the present disclosure, the reference signal includes a threshold judgment section reference signal and a quantization section reference signal, the threshold judgment is performed on the signal to be quantized by using the threshold judgment section reference signal, and the quantization signal that is easily affected by noise in the signal to be quantized is determined as an invalid section quantization signal.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is a schematic diagram of an analog-to-digital converter according to an embodiment of the disclosure;
FIG. 2 is a waveform diagram of a reference signal in an embodiment of the disclosure;
FIG. 3 is a flow chart of a quantization method provided by an embodiment of the present disclosure;
FIG. 4 is a waveform diagram of another reference signal provided by an embodiment of the present disclosure;
fig. 5 is a waveform diagram of another reference signal provided by an embodiment of the present disclosure;
fig. 6 is a timing diagram illustrating an operation of an analog-to-digital converter according to an embodiment of the disclosure;
fig. 7 is a waveform diagram of a reference signal and a signal to be quantized according to an embodiment of the present disclosure;
fig. 8 is a waveform diagram of another reference signal and a signal to be quantized provided by an embodiment of the disclosure;
FIG. 9 is a graph of code values for an output of an analog-to-digital converter provided by an embodiment of the present disclosure;
FIG. 10 is a graph of a code value output by a current ADC;
fig. 11 is a block diagram of an electronic device provided in an embodiment of the present disclosure.
Detailed Description
To facilitate a better understanding of the technical aspects of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, wherein various details of the embodiments of the present disclosure are included to facilitate an understanding, and they should be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," 8230; \8230 "; when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The single-slope ADC can quantize a signal to be quantized by using a reference signal with a linearly descending slope, compare the reference signal with the signal to be quantized in the quantization process, count a comparison result until a comparator is turned over, and store the count result into a latch, so that the quantization result of the signal to be quantized is obtained.
The related art needs to quantize all signals to be quantized, and if the adopted frequency of the reference signal is n bits, 2 is needed n The quantization can be completed only in one clock period, and the quantization efficiency is low.
Researches show that a low signal section which is easily influenced by noise exists in the signal to be quantized, the low signal section belongs to an invalid signal to be quantized, the invalid signal to be quantized is quantized, and the quantization efficiency is reduced.
Based on this, the embodiments of the present disclosure provide a quantization method, which can improve quantization efficiency.
Fig. 1 is a schematic diagram of an analog-to-digital converter according to an embodiment of the disclosure. As shown in fig. 1, the analog-to-digital converter includes an obtaining module 10 for obtaining input signals of the analog-to-digital converter, such as obtaining a signal to be quantized and a reference signal.
In some embodiments, the reference signal may be generated by the reference signal generation submodule 11, for example, the DAC signal may be used as the reference signal generated by the reference signal generation submodule; the signal to be quantized is a signal which is generated and acquired by the corresponding signal to be quantized generating submodule 12 and needs to be subjected to analog-to-digital conversion. The present embodiment does not limit the specific structures of the reference signal generation submodule 11 and the signal to be quantized generation submodule 12. The output ends of the reference signal generation submodule 11 and the signal to be quantized generation submodule 12 are electrically connected with the input end of the judgment module 20.
In some embodiments, as shown in fig. 2, the reference signal includes a threshold decision segment reference signal and a quantization segment reference signal, where the threshold decision segment reference signal is used for performing threshold decision on the signal to be quantized to determine an effective signal to be quantized and an ineffective signal to be quantized in the signal to be quantized. The quantization segment reference signal is used for performing quantization processing on the signal to be quantized.
In some embodiments, the reference signal further comprises a sample segment reference signal.
As shown in fig. 2, the reference signal includes a sampling segment reference signal, a threshold judging segment reference signal and a quantization segment reference signal, that is, the reference signal is divided into three segments, a voltage value of the sampling segment reference signal is a constant value, such as V0, a voltage value of the threshold judging segment reference signal may include a plurality of voltage values, such as V1 and V2, and a voltage value of the quantization segment reference signal is a continuously changing value.
And the judging module 20 is configured to perform threshold judgment on the signal to be quantized by using the reference signal of the threshold judgment section, and determine an effective signal to be quantized.
The threshold judgment can be realized by comparing the voltage value of the reference signal of the threshold judgment section with the voltage value of the signal to be quantized, and determining an effective signal to be quantized and an ineffective signal to be quantized based on the voltage comparison result.
In some embodiments, the decision module 20 includes a comparator sub-module 21 and a counter sub-module 22, wherein,
the comparator submodule 21 is configured to compare the voltage value of the threshold judgment section reference signal with the voltage value of the signal to be quantized, and obtain a first comparison result. A first input terminal INN of the comparator submodule 21 is electrically connected to the output terminal of the signal to be quantized obtaining submodule 12, and a second input terminal of the comparator submodule 21 is electrically connected to the second output terminal of the reference signal generating submodule 11.
A counter submodule 22 for determining a threshold determination result based on the first comparison result; the input of the counter submodule 22 is connected to the output of the comparator submodule 21.
The quantization module 30 includes a comparator submodule 21 and a counter submodule 22, wherein the comparator submodule 21 is further configured to compare the voltage value of the signal to be quantized with the voltage value of the quantization segment reference signal, and obtain a second comparison result. The counter submodule 22 is also arranged to record the toggling of the comparator submodule 21 based on the second comparison result.
In some embodiments, as shown in fig. 2, the threshold judging section reference signal includes a sampling section reference signal V0, a first threshold judging section reference signal V1 and a second threshold judging section reference signal V2.
In some embodiments, the first comparison result obtained by the comparator sub-module 21 includes that the voltage value Vx of the signal to be quantized is smaller than the voltage value V1 of the first threshold determination section reference signal, the voltage value Vx of the signal to be quantized is equal to the voltage value V1 of the first threshold determination section reference signal, the voltage value Vx of the signal to be quantized is greater than the voltage value V1 of the first threshold determination section reference signal, and the voltage value Vx of the signal to be quantized is smaller than the voltage value V2 of the second threshold determination section reference signal, the voltage value Vx of the signal to be quantized is equal to the voltage value V2 of the second threshold determination section reference signal, and the voltage value Vx of the signal to be quantized is greater than the voltage value V2 of the second threshold determination section reference signal.
If the voltage value V1 of the reference signal of the first threshold judgment section is greater than the voltage value V2 of the reference signal of the second threshold judgment section, the threshold judgment result determined by the counter submodule 22 includes: the voltage value Vx of the signal to be quantized is larger than the voltage value V1 of the reference signal of the first threshold judgment section; the voltage value Vx of the signal to be quantized is smaller than or equal to the voltage value V1 of the reference signal of the first threshold judgment section, and meanwhile, the voltage value Vx of the signal to be quantized is larger than or equal to the voltage value V2 of the reference signal of the second threshold judgment section; the voltage value Vx of the signal to be quantized is smaller than the voltage value V2 of the second threshold determination section reference signal, i.e., the signal to be quantized is divided into three sections by the first threshold determination section reference signal and the second threshold determination section reference signal.
In the embodiment of the disclosure, the signal to be quantized is a differential signal, such as a differential signal (VIN-VIP) of a first input signal VIN and a second input signal VIP, and the signal to be quantized close to 0 is determined as an invalid signal to be quantized, that is, the signal to be quantized with V1 ≦ Vx ≦ V2, where Vx is a voltage value of the signal to be quantized. And determining the signals to be quantized with Vx < V1 and Vx > V2 as effective signals to be quantized.
By adjusting the voltage value V1 of the first threshold determination section reference signal and the voltage value V2 of the second threshold determination section reference signal, the size of the interval between the effective signal to be quantized and the ineffective signal to be quantized can be controlled. In some embodiments, the interval of the invalid signal to be quantized can be controlled in the range of 10% by adjusting the voltage value V1 of the first threshold decision section reference signal and the voltage value V2 of the second threshold decision section reference signal, for example, when the voltage value of the signal to be quantized is [ -1v,1v ], the invalid signal to be quantized can be controlled in the interval of [ -0.1v,0.1v ], and [ -1V, -0.1V ] and [0.1v,1v ] are valid signals to be quantized.
And the quantization module 30 is configured to quantize any effective signal to be quantized in the multiple effective quantized signals by using the quantized segment reference signal, so as to obtain a quantization result of the signal to be quantized.
In some embodiments, the quantization module 30 includes a comparator sub-module 21 and a counter sub-module 22, i.e., the quantization module 30 and the decision module 20 share the comparator sub-module 21 and the counter sub-module 22. In some embodiments, the quantization module 30 and the determination module 20 employ different comparator sub-modules 21 and 22. However, the quantization module 30 and the determination module 20 share the comparator sub-module 21 and the counter sub-module 22, which can reduce the cost and volume of the analog-to-digital converter.
In the threshold judgment stage, the comparator submodule 21 is used to compare the reference signal of the threshold judgment stage with the signal to be quantized to obtain a first comparison result, and the counter submodule 22 is used to count the first comparison result obtained by the comparator submodule 21 to determine an effective signal to be quantized. In the quantization stage, the comparator submodule 21 is used to compare the quantization segment reference signal with the signal to be quantized to obtain a second comparison result, and the counter submodule 22 is used to count the second comparison result obtained by the comparator submodule 21 to obtain the quantization result of the signal to be quantized.
The comparator submodule 21 is configured to compare the voltage value of the quantization segment reference signal with the voltage value of any segment of the effective signal to be quantized, and obtain a second comparison result. The counter submodule 22 is configured to obtain a quantization result of the signal to be quantized based on the second comparison result.
In some embodiments, the comparator sub-module 21 compares the quantized segment reference signal with the valid signal to be quantized, and the counter sub-module 22 stops counting when the comparator sub-module 21 flips.
In some embodiments, as shown in fig. 2, the analog-to-digital converter further comprises a common mode voltage module 40 and a reference voltage module 50, wherein,
and the common-mode voltage module 40 is used for generating a common-mode voltage VCM of the comparator submodule 21, and an output end of the common-mode voltage module 40 is electrically connected with a second input end of the comparator submodule 21.
When the common-mode voltage module 40 is electrically connected to the second input terminal of the comparator submodule 21, the reference signal to be quantized is sampled when the common-mode voltage VCM is input to the comparator submodule 21.
And a reference voltage module 50 for generating a reference voltage VREF of the comparator sub-module 21, an output terminal of the reference voltage module being electrically connected to a second input terminal of the comparator sub-module 21.
After the threshold is judged, if the highest count value of the counter submodule 22 is "1", the reference voltage module 50 is electrically connected to the second input terminal of the comparator submodule 21, otherwise, the reference voltage module 50 is electrically disconnected from the second input terminal of the comparator submodule 21.
In the analog-to-digital converter provided by the embodiment of the disclosure, the reference signal acquired by the acquisition module includes a threshold judgment section reference signal and a quantization section reference signal, the judgment module performs threshold judgment on a signal to be quantized by using the threshold judgment section reference signal, removes an invalid band quantization signal which is easily affected by noise in the signal to be quantized, and determines a plurality of sections of effective signals to be quantized, and when the quantization module quantizes the signal to be quantized, the quantization module does not need to quantize all effective signals to be quantized, and only needs to quantize any section of effective signals to be quantized in the plurality of sections of effective signals to be quantized, so that a quantization result of the signal to be quantized can be obtained, and thus the quantization efficiency is improved.
The embodiment of the disclosure also provides a quantization method, which can improve quantization efficiency. Fig. 3 is a flowchart of a quantization method provided by an embodiment of the present disclosure. As shown in fig. 3, the quantization method includes:
step S301, a signal to be quantized and a reference signal are obtained, wherein the reference signal comprises a threshold judgment section reference signal and a quantization section reference signal, and the signal to be quantized and the reference signal are both analog signals.
Step S302, threshold judgment is carried out on the signal to be quantized by utilizing the reference signal of the threshold judgment section, and a plurality of sections of effective signals to be quantized are determined.
Step S303, quantize any one segment of effective signals to be quantized in the multiple segments of effective quantized signals by using the quantized segment reference signal, and obtain a quantized result of the signals to be quantized.
In the quantization method provided by the embodiment of the present disclosure, the reference signal includes a threshold judgment section reference signal and a quantization section reference signal, the threshold judgment is performed on the signal to be quantized by using the threshold judgment section reference signal, the invalid band quantization signal that is easily affected by noise in the signal to be quantized is removed, the multiple sections of effective signals to be quantized are determined, when the signal to be quantized is quantized, all the effective signals to be quantized do not need to be quantized, and only any one section of effective signals to be quantized in the multiple sections of effective signals to be quantized needs to be quantized, so that the quantization result of the signal to be quantized can be obtained, thereby improving the quantization efficiency.
In some embodiments, the reference signal comprises one or more threshold decision segment reference signals, and the voltage value of each threshold decision segment reference signal is different.
As shown in fig. 2, the reference signal includes two threshold determination segment reference signals, wherein a voltage value of the first threshold determination segment reference signal is V1, a voltage value of the second threshold determination segment reference signal is V2, and V1 ≠ V2.
In some embodiments, the reference signal comprises a threshold decision segment reference signal, and the decision segment reference signal may be a positive decision segment of the signal to be quantized or a negative decision segment of the signal to be quantized. For example, a threshold decision section reference signal is used to decide the forward direction of the signal to be quantized, if the voltage value of the signal to be quantized is less than or equal to the voltage value of the threshold decision section reference signal, the signal to be quantized is an invalid signal to be quantized, otherwise, the signal to be quantized is a valid signal to be quantized. If the voltage value of the signal to be quantized is greater than or equal to the voltage value of the threshold judgment section reference signal, the signal to be quantized is an invalid signal to be quantized, otherwise, the signal to be quantized is an effective signal to be quantized.
In some embodiments, the reference signal comprises a multi-segment threshold decision segment reference signal. As shown in fig. 4, the reference signal includes four threshold determination segment reference signals, wherein a voltage value of the first threshold determination segment reference signal is V1, a voltage value of the second threshold determination segment reference signal is V2, a voltage value of the third threshold determination segment reference signal is V3, a voltage value of the fourth threshold determination segment reference signal is V4, and V1 ≠ V2 ≠ V3 ≠ V4.
And respectively carrying out threshold judgment on the positive direction and the negative direction of the signal to be quantized by utilizing the voltage value V2 of the reference signal of the second threshold judgment section and the voltage value V4 of the reference signal of the fourth threshold judgment section. And when the voltage value of the signal to be quantized is greater than the voltage value V2 of the reference signal of the second threshold judgment section, the signal to be quantized is an effective signal to be quantized. And when the voltage value of the signal to be quantized is less than or equal to the voltage value V2 of the reference signal of the second threshold judgment section and is greater than or equal to the voltage value V4 of the reference signal of the fourth threshold judgment section, the signal to be quantized is an invalid signal to be quantized. And when the voltage value of the signal to be quantized is smaller than the voltage value V4 of the reference signal of the fourth threshold judgment section, the signal to be quantized is an effective signal to be quantized.
When it is determined that the voltage value of the signal to be quantized is greater than the voltage value V2 of the second threshold decision section reference signal, the voltage value of the quantization section reference signal may be increased with reference to the voltage value V1 of the first threshold decision section reference signal, so that the quantization section reference signal can intersect with the signal to be quantized. In this embodiment, the voltage value of the quantized segment reference signal is determined more accurately by using a plurality of threshold judgment modes, and the voltage value of the quantized segment reference signal does not need to be adjusted for many times to determine the voltage value of the quantized segment reference signal in a proper range, so that the quantization efficiency of the effective signal to be quantized can be realized more efficiently.
It should be noted that, in the embodiments of the present disclosure, only two reference signals are listed, but the present disclosure is not limited thereto, and the reference signal may include only one segment of the threshold decision section reference signal, or may be more segments of the threshold decision section reference signals. When the reference signal includes a plurality of threshold judging section reference signals, the voltage value of each threshold judging section reference signal is different.
In some embodiments, as shown in fig. 2, the reference signal further includes a sampling segment reference signal, and in the sampling segment reference signal, the analog-to-digital converter is configured to collect the signal to be quantized, and the threshold determination and quantization steps are not performed.
The threshold judgment section reference signal comprises a first threshold judgment section reference signal and a second threshold judgment section reference signal, and a first voltage difference value between a voltage value V1 of the first threshold judgment section reference signal and a voltage value V0 of the sampling section reference signal is equal to a second voltage difference value between a voltage value V2 of the second threshold judgment section reference signal and a voltage value V0 of the sampling section reference signal. In other words, in the embodiment of the present disclosure, the voltage value V1 of the first threshold determination section reference signal and the voltage value V2 of the second threshold determination section reference signal are symmetrical with respect to the voltage value V0 of the sampling section reference signal. In the embodiment of the present disclosure, the voltage value V1 of the first threshold judgment section reference signal and the voltage value V2 of the second threshold judgment section reference signal may also be asymmetric, but the voltage value V1 of the first threshold judgment section reference signal and the voltage value V2 of the second threshold judgment section reference signal are respectively located at two sides of the voltage value V0 of the sampling section reference signal. If the voltage value V1 of the reference signal of the first threshold value judging section is consistent with the voltage value V0 of the reference signal of the sampling section; or the voltage value V2 of the reference signal of the second threshold judgment section is consistent with the voltage value V0 of the reference signal of the sampling section; alternatively, the voltage value V1 of the first threshold determination section reference signal and the voltage value V2 of the second threshold determination section reference signal may be different values.
In some embodiments, the step S302 of performing threshold decision on the signal to be quantized by using the threshold decision section reference signal, and determining a plurality of sections of valid signals to be quantized includes:
when the reference signal jumps from the sampling section reference signal to a first threshold judgment section reference signal, performing threshold judgment on a signal to be quantized by using the first threshold judgment section reference signal to obtain a first threshold judgment result; when the reference voltage jumps from the first threshold judgment section reference signal to a second threshold judgment section reference signal, performing threshold judgment on a signal to be quantized by using the second threshold judgment section reference signal to obtain a second threshold judgment result; and segmenting the signal to be quantized based on the first threshold judgment result and the second threshold judgment result, and determining multiple sections of effective signals to be quantized.
In this embodiment, the threshold determination result includes a first threshold determination result and a second threshold determination result, the first threshold determination result is a comparison result between a voltage value of a first threshold determination segment reference signal and a voltage value of a signal to be quantized, and the second threshold determination result is a comparison result between a voltage value of a second threshold determination segment reference signal and a voltage value of a signal to be quantized. The signal to be quantized may be divided into a plurality of pieces of effective signals to be quantized based on the first threshold determination result and the second threshold determination result.
In some embodiments, if the voltage value of the first threshold decision segment reference signal is greater than or equal to the voltage value of the second threshold decision segment reference signal; segmenting the signal to be quantized based on the first threshold judgment result and the second threshold judgment result, and determining a plurality of effective signals to be quantized, including:
if the voltage value of the signal to be quantized is larger than the voltage value of the reference signal of the first threshold judgment section, the signal to be quantized is an effective signal to be quantized; if the voltage value of the signal to be quantized is less than or equal to the voltage value of the reference signal of the first threshold judgment section and the voltage value of the signal to be quantized is greater than or equal to the voltage value of the reference signal of the second threshold judgment section, the signal to be quantized is an invalid signal to be quantized; and if the voltage value of the signal to be quantized is smaller than the voltage value of the reference signal of the second threshold judgment section, the signal to be quantized is an effective signal to be quantized.
Exemplarily, the voltage value Vx of the signal to be quantized is greater than the voltage value V1 of the first threshold determination section reference signal; the voltage value Vx of the signal to be quantized is smaller than or equal to the voltage value V1 of the reference signal of the first threshold judgment section, and meanwhile, the voltage value Vx of the signal to be quantized is larger than or equal to the voltage value V2 of the reference signal of the second threshold judgment section; the voltage value Vx of the signal to be quantized is smaller than the voltage value V2 of the reference signal of the second threshold judgment section, namely, the signal to be quantized is divided into three sections through the reference signal of the first threshold judgment section and the reference signal of the second threshold judgment section.
When the signal to be quantized is a differential signal, the signal to be quantized close to 0 is determined as an invalid signal to be quantized, namely the signal to be quantized with V1 being more than or equal to Vx being more than or equal to V2 is determined as an invalid signal to be quantized. And determining the signals to be quantized with Vx < V1 and Vx > V2 as effective signals to be quantized.
In some embodiments, the step S203 quantizes any one of the multiple effective quantized signals by using the quantized segment reference signal to obtain a quantization result of the signal to be quantized, including:
comparing the quantization segment reference signal with any segment of effective signal to be quantized to obtain a plurality of second comparison results; a quantization result of the signal to be quantized is obtained based on the plurality of second comparison results.
In the embodiment of the present disclosure, when the quantized segment reference signal is compared with any segment of the effective signal to be quantized, a second comparison result is obtained, and since the comparison is performed once per clock cycle and multiple comparisons are performed for each quantization, multiple second comparison results can be obtained for each quantization. These second comparison results are counted and a quantization result can be obtained.
According to the embodiment of the invention, any section of effective signals to be quantized only needs to be quantized, and all signals to be quantized do not need to be quantized, so that the comparison times are reduced, and the quantization time only needs 2 n-1 A clock, relative to the current 2 n And the clock is used for improving the quantization speed.
In order to better understand the analog-to-digital converter and the quantization method provided by the embodiments of the present disclosure, the following description will take an example in which the reference signal includes two threshold decision section reference signals.
In the embodiment of the present disclosure, as shown in fig. 5, the voltage value of the reference signal in the sampling section is VA + VTH, the voltage value of the reference signal in the first threshold determination section is VA +2 × VTH, and the voltage value of the reference signal in the second threshold determination section is VA. Where VA =127 lsb, vth = k lsb, lsb represents the quantization accuracy, and the value of k may be set by a register.
The signal to be quantized is a differential signal (VIN-VIP) which is a first input signal VIN and a second input signal VIP, and the disclosed embodiment quantizes the difference value of the input differential signal with a quantization precision of 8 bits. The quantization accuracy may be arbitrarily set as necessary.
In the embodiment of the present disclosure, as shown in fig. 1, a first input terminal INN of the comparator submodule 21 is connected to a signal to be quantized, and a second input terminal INP of the comparator submodule 21 is connected to a reference signal, and may also be connected to a common mode voltage signal or a reference voltage signal. When the output of the comparator submodule 21 is high level, the counter submodule 22 counts; the comparator sub-module 21 output is low and the counter sub-module 22 does not count.
As shown in fig. 6, the operation of the analog-to-digital converter is shown in a timing diagram. In fig. 6, DAC _ CODE is the input CODE value of the control reference signal (all corresponding decimal values): sampling phase DAC _ CODE = (127 +) k; threshold judging stage DAC _ CODE is changed from (127 + 2k) to 127; the fine quantization phase DAC _ CODE drops linearly from 127 to 0.
CNT _ RSTN is a counter reset signal and is reset and cleared in the sampling stage of the sub-module of the comparator.
CNT _ CLK0 is the clock signal of the threshold decision stage, and within each quantization period, there are only 2 high pulses, and the rising edge is the trigger edge, where the first rising edge corresponds to the time when DAC _ CODE jumps from (127 + 2k) to 127, and decides in which time segment the signal to be quantized is.
CNT _ CLK1 is a clock signal after the start of fine quantization, and has 127 high pulses in each quantization period;
the LATCH signal is the signal that stores the code value Q <7> in the counter into the LATCH, resulting in a LATCH code value DOUT <7 >.
As shown in fig. 1, 5 and 6, the quantization process of the analog-to-digital converter includes:
in the sampling segment reference signal phase, the first input signal VIN and the sampling segment reference signal are respectively input to the first input terminal INN and the second input terminal INP of the comparator sub-module, step S61.
In step S62, the second input signal VIP is input to the first input terminal of the comparator sub-module, and at this time, the voltage variation of the first input terminal of the comparator sub-module is the absolute value of (VIN-VIP).
And S63, when the reference voltage jumps from the voltage value (VA + VTH) of the reference signal in the sampling period to the voltage value (VA +2 VTH) of the reference signal in the first threshold judgment period, performing first threshold judgment, namely comparing the difference value of the signals to be quantized (VIN-VIP) with the value of-VTH. If (VIN-VIP) < -VTH, the output of the comparator submodule is inverted from high level to low level, the first rising edge of the CNT _ CLK0 signal is not counted, the counter submodule outputs a first count code value Q <7> =0, and a second count code value Q _ TMP <7> =0; if (VIN-VIP) > -VTH, the comparator sub-module output is high, the first rising edge of the CNT _ CLK0 signal counts a number, the comparator sub-module outputs a first count code value Q <7> =0, and a second count code value Q _ TMP <7> =1. Wherein Q <7> is the maximum value of Q <7 >.
Step S64, when the output voltage of the reference signal jumps from the voltage value (VA +2 VTH) of the reference signal of the first threshold judgment section to the voltage value VA of the reference signal of the second threshold judgment section, performing second threshold judgment, namely comparing the difference value of (VIN-VIP) with the value of VTH; if (VIN-VIP) < VTH, the comparator sub-module output is inverted from high to low, the second rising edge of the CNT _ CLK0 signal is not counted, and the counter sub-module output is unchanged, i.e., the first count code value Q <7> =0 and the second count code value Q _ TMP <7> =1; if (VIN-VIP) > VTH, the comparator sub-module output is still high, the second rising edge of the CNT _ CLK0 signal continues to count by one number, and the counter sub-module outputs the first count code value Q <7> =1 and the second count code value Q _ TMP <7> =0.
Step S65, based on the threshold judgment result, segmenting the signal to be quantized:
when VIN-VIP < -VTH, the first count code value Q <7> =0, the second count code value Q _ TMP <7> =0, and the signal to be quantized is an effective signal to be quantized;
when-VTH = < VIN-VIP = < VTH, the first count code value Q <7> =0, the second count code value Q _ TMP <7> =1, and the signal to be quantized is an invalid signal to be quantized;
when VIN-VIP > = VTH, the first count code value Q <7> =1, the second count code value Q _ TMP <7> =0, and the signal to be quantized is an effective signal to be quantized.
When the first count code value Q <7> =0, the reference voltage module is electrically connected to the second input INP of the comparator sub-module, and at this time, the value of the second input INP is VREF, that is, VREF = VCM + VTH + VA. When the first count code value Q <7> =1, the reference voltage module is disconnected from the second input end INP of the comparator sub-module, and the value of the second input end INP is maintained as it is.
It is easy to understand that the signal to be quantized is divided into three segments according to the threshold judgment result, wherein the middle segment is an invalid signal to be quantized close to 0.
And S66, quantizing one section of effective signals to be quantized based on the threshold judgment result.
In step S66, the first count code value Q is obtained as a result of the threshold determination<7>=0, input differential signal (VIN-VIP)>0, the voltage of the reference signal of the quantization section is linearly decreased from VA to 0 and is quantized according to the waveform shown in FIG. 7, the waveform of the first input terminal INN and the first input terminal INP of the comparator sub-module is decreased from VCM + VTH + VA to VCM + VTH; if the threshold value judgment result is the first counting code value Q<7>＝1，(VIN-VIP)>0, the voltage of the quantization segment reference signal is linearly decreased from VA to 0 and is quantized according to the waveform shown in FIG. 8, and the first input terminal INP of the comparator sub-module is decreased from VCM-VTH to VCM-VTH-VA; only 2 need to be executed for each fine quantization 7 -1=127 clock cycles, and thus shorter than the quantization time of a conventional 8-bit single-ramp ADC (conventional quantization time is2 8 1 clock cycle). In the quantized segment reference signal of the reference signal shown in fig. 7, there is a signal value rising process in the quantization starting stage compared to the voltage value of the second threshold determination reference signal, i.e. the reference signal in fig. 7 rises from VCM-VTH to VCM + VTH + VA at the intersection of the 'threshold determination' and 'quantization' stages, so that the ramp signal of the quantized segment reference signal crosses the signal to be quantized. It will be appreciated that the rise value of the quantized segment reference signal may be determined empirically or in conjunction with the first threshold value.
In step S67, when the LATCH signal is in a high pulse state, all counter code values Q <7> in the counter submodule are stored in a LATCH (not shown in the figure), so as to obtain quantized code values DOUT <7 >.
FIG. 9 is a graph of code values output by an analog-to-digital converter provided by an embodiment of the present disclosure. Wherein the horizontal axis is the difference of the signals to be quantized, i.e. (VIN-VIP), and the vertical axis is the 8-bit code value of the quantized output. As can be seen from the figure, in the case of an invalid signal segment to be quantized (VIN-VIP) = [ -VTH, VTH ], the output code value is 8' h7f, i.e., no quantization is performed; the code value to be outputted is within (8 ' h7f,8' hff) in the case of (VIN-VIP) > VTH, and within [0,8' h7 f) in the case of (VIN-VIP) < -VTH.
FIG. 10 is a graph of the code value output by the current ADC. As can be seen from fig. 10, the invalid signal segment to be quantized [ -VTH, VTH ] is also quantized. And the invalid signal segment to be quantized is quantized, so that the quantization efficiency is reduced. The embodiment of the present disclosure quantizes only the effective signals to be quantized, so that the quantization efficiency can be improved, and only one section of the effective signals to be quantized in the effective signals to be quantized can be selected for quantization, thereby further improving the quantization efficiency.
The quantization method and the analog-to-digital converter provided by the embodiment of the disclosure can be applied to various fields, such as various sensors, instruments and meters, image and voice recognition and other occasions, can improve the quantization speed, and combine the advantages of high precision and small area of the ADC.
It is understood that the above embodiments of the method and the analog-to-digital converter mentioned in the present disclosure can be combined with each other to form a combined embodiment without departing from the logic principle, which is limited by the space, and the detailed description of the present disclosure is omitted. Those skilled in the art will appreciate that in the above methods of the specific embodiments, the specific order of execution of the steps should be determined by their function and possibly their inherent logic.
Fig. 11 is a block diagram of an electronic device provided in an embodiment of the present disclosure.
Referring to fig. 11, an embodiment of the present disclosure provides an electronic device including: at least one processor 1101; at least one memory 1102, and one or more I/O interfaces 1103 coupled between the processor 1101 and the memory 502; wherein the memory 1102 stores one or more computer programs executable by the at least one processor 1101 to enable the at least one processor 1101 to perform the quantization method described above.
Embodiments of the present disclosure also provide a computer-readable storage medium having stored thereon a computer program, wherein the computer program, when executed by a processor/processing core, implements the above-described quantization method. The computer readable storage medium may be a volatile or non-volatile computer readable storage medium.
The disclosed embodiments also provide a computer program product comprising computer readable code or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, the processor in the electronic device performs the above quantization method.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, or suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable storage media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static Random Access Memory (SRAM), flash memory or other memory technology, portable compact disc read-only memory (CD-ROM), digital Versatile Discs (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. In addition, communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.
The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).
The computer program product described herein may be embodied in hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK) or the like.
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (12)
1. A method of quantization, comprising:
acquiring a signal to be quantized and a reference signal, wherein the reference signal comprises a threshold judgment section reference signal and a quantization section reference signal;
carrying out threshold judgment on the signal to be quantized by utilizing the reference signal of the threshold judgment section, and determining a plurality of sections of effective signals to be quantized;
and quantizing any effective signal to be quantized in the multiple effective quantized signals by utilizing the quantized segment reference signals to obtain a quantization result of the signal to be quantized.
2. The method of claim 1, wherein the reference signal comprises one or more segments of the threshold decision segment reference signal, and a voltage value of each segment of the threshold decision segment reference signal is different.
3. The method of claim 2, wherein the reference signal further comprises a sampled segment reference signal;
the threshold judgment section reference signal comprises a first threshold judgment section reference signal and a second threshold judgment section reference signal, and a first voltage difference value between the voltage value of the first threshold judgment section reference signal and the voltage value of the sampling section reference signal is equal to a second voltage difference value between the voltage value of the second threshold judgment section reference signal and the voltage value of the sampling section reference signal.
4. The method of claim 3, wherein the thresholding the to-be-quantized signal using the thresholding segment reference signal to determine multiple segments of valid to-be-quantized signals comprises:
when the reference signal jumps from the sampling section reference signal to the first threshold judgment section reference signal, performing threshold judgment on the signal to be quantized by using the first threshold judgment section reference signal to obtain a first threshold judgment result;
when the reference voltage jumps from the first threshold judgment section reference signal to the second threshold judgment section reference signal, performing threshold judgment on the signal to be quantized by using the second threshold judgment section reference signal to obtain a second threshold judgment result;
and segmenting the signal to be quantized based on the first threshold judgment result and the second threshold judgment result, and determining the multiple sections of effective signals to be quantized.
5. The method of claim 4, wherein the voltage value of the first threshold decision segment reference signal is greater than or equal to the voltage value of the second threshold decision segment reference signal;
the segmenting the signal to be quantized based on the first threshold judgment result and the second threshold judgment result, and determining the multiple effective signals to be quantized includes:
if the voltage value of the signal to be quantized is larger than the voltage value of the reference signal of the first threshold judgment section, the signal to be quantized is the effective signal to be quantized;
if the voltage value of the signal to be quantized is less than or equal to the voltage value of the first threshold judgment section reference signal and the voltage value of the signal to be quantized is greater than or equal to the voltage value of the second threshold judgment section reference signal, the signal to be quantized is an invalid signal to be quantized;
and if the voltage value of the signal to be quantized is smaller than the voltage value of the reference signal of the second threshold judgment section, the signal to be quantized is the effective signal to be quantized.
6. The method according to claim 4, wherein the quantizing any segment of the effective signals to be quantized in the plurality of segments of effective quantized signals by using the quantized segment reference signals to obtain the quantization result of the signals to be quantized comprises:
comparing the quantization segment reference signal with any segment of the effective signal to be quantized to obtain a plurality of second comparison results;
obtaining a quantization result of the signal to be quantized based on the plurality of second comparison results.
7. An analog-to-digital converter, comprising:
an obtaining module, configured to obtain a signal to be quantized and a reference signal, where the reference signal includes a threshold decision segment reference signal and a quantization segment reference signal;
the judging module is used for utilizing the threshold judging section reference signal to carry out threshold judgment on the signal to be quantized and determining a plurality of sections of effective signals to be quantized;
and the quantization module is used for quantizing any effective signal to be quantized in the multiple effective quantized signals by utilizing the quantized segment reference signals to obtain a quantization result of the signal to be quantized.
8. The analog-to-digital converter according to claim 7, wherein the determining module comprises:
the comparator submodule is used for comparing the voltage value of the threshold judgment section reference signal with the voltage value of the signal to be quantized to obtain a first comparison result; a first input end of the comparator submodule is electrically connected with a first output end of the acquisition module, and a second input end of the comparator submodule is electrically connected with a second output end of the acquisition module;
a counter submodule for determining a threshold determination result based on the first comparison result; and the input end of the counter submodule is connected with the output end of the comparator submodule.
9. The analog-to-digital converter according to claim 8, wherein the comparator sub-module is further configured to compare the voltage value of the quantized segment reference signal with the voltage value of any segment of the valid signal to be quantized to obtain a second comparison result;
and the counter submodule is also used for obtaining a quantization result of the signal to be quantized based on the second comparison result.
10. The analog-to-digital converter of claim 8, further comprising:
the common-mode voltage module is used for generating an initial common-mode voltage of the comparator sub-module, and the output end of the common-mode voltage module is electrically connected with the second input end of the comparator sub-module;
and the reference voltage module is used for generating a reference voltage of the comparator submodule, and the output end of the reference voltage module is electrically connected with the second input end of the comparator submodule.
11. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores one or more computer programs executable by the at least one processor to enable the at least one processor to perform the quantization method of any one of claims 1-6.
12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the quantization method according to any one of claims 1-6.
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| PCT/CN2023/120101 WO2024067299A1 (en) | 2022-09-30 | 2023-09-20 | Network precision quantization method, system and apparatus, and electronic device and readable medium |
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