CN115602773A

CN115602773A - Light-emitting diode

Info

Publication number: CN115602773A
Application number: CN202211088027.1A
Authority: CN
Inventors: 王水杰; 徐瑾; 刘可; 石保军; 吴美健
Original assignee: Hubei San'an Photoelectric Co ltd
Current assignee: Hubei San'an Photoelectric Co ltd
Priority date: 2022-05-25
Filing date: 2022-09-07
Publication date: 2023-01-13

Abstract

The invention relates to a design of a light-emitting diode chip, which comprises an epitaxial structure positioned on a first area of a first surface of a substrate, an insulating layer covering a second area of the substrate around the epitaxial structure, a part of the insulating layer with relatively lower compactness is removed on the second area of the substrate, the part of the insulating layer with relatively higher compactness is remained on the second area of the whole substrate, so that the risk of breakage of the insulating layer at the edge of the chip is reduced while water vapor protection is ensured, and the manufacturing yield is improved.

Description

Light-emitting diode

Technical Field

The invention relates to the field of semiconductor devices, in particular to a light emitting diode.

Background

Semiconductor light emitting elements, i.e., light emitting diodes, are widely used in various products such as large-sized backlight units, general lighting, and electrical components. The application of small-sized light emitting diode chips (Mini-LEDs) in the field of display is particularly favored because of their advantages of small size, high light source utilization, long lifetime, etc.

As application products such as general illumination or electric appliances, a light emitting diode having a relatively large size is used in order to realize high output in a single chip. Such light emitting diode chips generally have a size of, for example, 700 × 700 μm2 or more.

In contrast, in the small-sized backlight display unit, in order to secure the fineness of display, small-sized light emitting diodes, for example, light emitting diode chips having a size of 300 × 300 μm2 or less are suitably used, and are arranged on the backlight panel with mounting at a smaller pitch.

The backlight source required in the field of display panels needs thousands or tens of thousands of leds mounted on a circuit board, so the yield and reliability of led chip fabrication become very important to reduce the cost and ensure the performance. Such as moisture protection, chip fabrication yield. And the requirements of the LED on the performance such as the water vapor protection performance, the chip manufacturing yield and the like are higher and more rigorous along with the continuous reduction of the miniLED size.

Disclosure of Invention

One objective of the present invention is to provide a light emitting diode chip with high moisture protection performance and high manufacturing yield.

It is also an object of the present invention to provide a compact light emitting diode chip having a simple structure.

The present invention provides a light emitting diode, comprising:

the device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a first surface which is divided into a first area and a second area;

the epitaxial structure is positioned on a first area of the first surface of the substrate and comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially laminated from bottom to top;

the insulating layer comprises a DBR layer and a bottom protective layer below the DBR layer, and the upper surface and the side wall of the epitaxial structure are covered by the DBR layer and the bottom protective layer below the DBR layer;

a first pad electrode and a second pad electrode on the insulating layer;

wherein the DBR layer and the underlying protective layer below the DBR layer further overlie a portion of the second region of the substrate surrounding the epitaxial structure, and said underlying protective layer further overlies the remaining second region of the substrate.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1~2 is a cross-sectional view of a conventional LED;

fig. 3 is a schematic top view of an led structure according to an embodiment of the present invention;

fig. 4 is a schematic cross-sectional view of an led structure according to an embodiment of the invention;

fig. 5 (a) and 5 (b) are partial schematic views of the insulating layer 60 a.

Reference numerals are as follows: 10, a substrate; 20, a first semiconductor layer; 30, a light emitting layer; 40, a second semiconductor layer; 50, a current spreading layer; 60, an insulating layer; 70, a first electrode; 71, a first contact electrode; 72, a first pad electrode; 80, a second electrode; 81, a second contact electrode; 82, a second pad electrode; 100, a current blocking layer; 60a, a first portion of the insulating layer; 60b, a second portion of the insulating layer.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

It should be noted that the thickness of each layer in the present specification and claims refers to a geometric thickness and also refers to the thickest thickness of each layer in the whole light emitting diode, that is, each layer has different thickness settings due to etching in different regions, but the thickness of each layer is defined as the thickest thickness position of each layer in all regions of the chip.

A conventional small-sized light emitting diode is shown in fig. 1, and includes a substrate, where the substrate includes a first surface, and the first surface is divided into a first area and a second area; the epitaxial structure is positioned on a first area of the first surface of the substrate and comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially laminated from bottom to top; the insulating layer is defined as an m layer and covers the upper surface and the side wall of the epitaxial structure; a first pad electrode and a second pad electrode on the insulating layer; wherein the m insulating layers also cover all the second areas of the substrate.

The m insulating layers comprise DBR layers formed by repeatedly stacking two material layers with different refractive indexes, the two material layers with different refractive indexes are usually silicon oxide and titanium oxide, the DBR layers are manufactured by adopting an optical film coating machine, such as an ion-assisted vapor deposition machine, the geometric thickness of each layer is usually 20-200nm, a film obtained by a film coating process adopted by the conventional DBR layer is high in brittleness and stress, the total thickness of the insulating layers is usually 3~6 micrometers, the thickness is thick, before a cutting and separating step in a chip manufacturing process, the thick insulating layers continuously cover a wafer which is not cut and separated, the whole wafer is easy to warp, the brittleness is high, the insulating layers at the edges of chips are easy to crack after the cutting and separating step, and the chip manufacturing yield is low.

In another conventional light emitting diode, as shown in fig. 2, unlike the structure shown in fig. 1, the m insulating layers only cover part of the upper surface of the substrate around the epitaxial structure, and part of the upper surface of the substrate is exposed, that is, the insulating layer of each chip is disconnected before the dicing and separating step in the chip manufacturing process, so that the risks that the stress of the entire insulating layer causes wafer warpage and the insulating layer is easily broken at the edge are reduced, and the manufacturing yield of the chips is improved.

However, if the insulating layer is exposed out of part of the upper surface of the substrate, if the width of the upper surface of the substrate which is not occupied by the epitaxial structure is not widened, the edge of the insulating layer is closer to the epitaxial structure, water vapor easily enters the epitaxial structure, leakage failure occurs, and the protection performance is insufficient; if the width of the upper surface of the substrate around the epitaxial structure is widened, the particle number of the chip manufactured by a single wafer is reduced, and the manufacturing cost of the chip is improved.

Therefore, the invention provides a light emitting diode which is improved based on the existing structure, and comprises an epitaxial structure positioned in a first area of a first surface of a substrate, an insulating layer covering a second area of the substrate around the epitaxial structure, a part of the insulating layer with relatively low compactness is removed from the second area of the substrate, and a part of the insulating layer with relatively high compactness is remained on the second area of the whole substrate, so that the risk of chip warpage and insulating layer fracture is reduced while water vapor protection is ensured, and the manufacturing yield is improved.

The present invention provides a light emitting diode, comprising:

a first pad electrode and a second pad electrode on the insulating layer;

Specifically, the light emitting diode according to the present embodiment will be described in detail below with reference to fig. 3~5, which includes:

a substrate 10;

alternatively, the substrate 10 includes at least one of sapphire (alumina layer), siC, gaAs, gaN, znO, gaP, inP, and Ge, which may be selected, and is not limited to the examples listed herein.

The light emitting diode in this embodiment is a flip-chip light emitting diode, preferably a sapphire substrate, the light emitting layer 30 is a multi-quantum well layer, and the sapphire substrate has two opposite sides, wherein the lower side serves as a light emitting surface, and the upper side is stacked with an epitaxial structure.

The epitaxial structure on the substrate comprises a first semiconductor layer 20, a light-emitting layer 30 and a second semiconductor layer 40 which are sequentially laminated from bottom to top on the substrate, and preferably, the epitaxial structure further comprises an electrode table top, wherein the electrode table top is provided with an inclined plane penetrating through the second semiconductor layer 40 and the light-emitting layer 30, and a plane area exposing part of the first semiconductor layer 20. Preferably, the surface of the planar region is annular around the light-emitting layer, and the planar region has a local widening on the side of the light-emitting layer for mounting a first contact electrode mentioned later, when the first semiconductor layer 20 is viewed from the side of the second semiconductor layer 40.

As an example, the first semiconductor layer 20 may be an N-type GaN layer, and the second semiconductor layer 40 may be a P-type GaN layer. Wherein the N type is a silicon-based doping type, and the P type is a magnesium-based doping type.

The epitaxial structure is a gallium nitride-based epitaxial layer or a gallium arsenide-based epitaxial layer, and light-emitting radiation between 380 and 700nm, such as light with single peak wavelength of blue light, green light or red light, can be provided through the selection of materials of the light-emitting layer.

Preferably, there is a transparent current spreading layer 50 on the second semiconductor layer 40. The current spreading layer forms an ohmic contact with the second semiconductor layer and is formed on the second semiconductor layer 40 nearly over the entire surface (at least 90% of the coverage area). The current spreading layer simultaneously enables lateral transport of current in the horizontal direction.

The material of the current spreading layer 50 may be a metal oxide, and the current spreading layer is a relatively transparent material that allows at least part of the radiation of the light emitting layer to transmit, such as one or a combination of ITO, GTO, GZO, and ZnO, and is not limited to the examples listed here, and preferably, the thickness of the current spreading layer is 30 to 200nm.

The first electrode 70, electrically connected to the first semiconductor layer 20, includes a first contact electrode 71 and a first pad electrode 72, wherein the first contact electrode 71 is located on a planar area of the first semiconductor layer 20 of the electrode mesa, forming an ohmic contact with the first semiconductor layer 20.

A second electrode 80, located over the second semiconductor layer 40, electrically connected to the second semiconductor layer 40, including a second contact electrode 81 and a second pad electrode 82.

In this embodiment, the first electrode 70 and the second electrode 80 are metal electrodes, such as nickel, gold, chromium, titanium, platinum, palladium, rhodium, iridium, aluminum, tin, indium, tantalum, copper, cobalt, iron, ruthenium, zirconium, tungsten, molybdenum, and one or a combination thereof.

As an example, the first electrode 70 may be an N electrode, and the second electrode 80 may be a P electrode.

As an example, the first pad electrode 72 may be an N pad electrode, and the second pad electrode 82 may be a P pad electrode.

As an embodiment, the second contact electrode 81 is located on the second semiconductor layer, and is located on the transparent current spreading layer 50, and is in contact with the transparent current spreading layer 50.

And an insulating layer 60 on the epitaxial structure, specifically on the second semiconductor layer 40, the planar area of the first semiconductor layer 20, and the inclined plane of the electrode mesa, and covering the first contact electrode 71 and the second contact electrode 81, wherein the first pad electrode 72 and the second pad electrode 82 are formed on the insulating layer 60. The insulating layer may be one that allows most of the light to be transmitted or allows most of the light to be reflected.

The insulating layer 60 covers the upper surface and the sidewall of the epitaxial structure, and covers the transparent current spreading layer 50 and the first and

second contact electrodes

71 and 81.

The insulating layer 60 is provided with a through hole penetrating through the insulating layer 60, and as shown in fig. 4, the through hole is located above the first contact electrode 71 and the second contact electrode 81. The insulating layer 60 has a first via hole 73 on a contact portion of the first contact electrode 71.

The first pad electrode 72 and the second pad electrode 82 are in contact connection with the contact portions of the first contact electrode 71 and the second contact electrode 81, respectively, through via holes provided in the insulating layer 60. The shortest distance between the first pad electrode and the second pad electrode is 60 to 300 mu m.

A current blocking layer 100 is further disposed between the transparent current spreading layer 50 and the second semiconductor layer 40. The current blocking layer 100 is disposed below the second contact electrode, and is used for blocking current from vertically and longitudinally transmitting current between the second contact electrode and the second semiconductor layer, and promoting the transverse transmission function of the current spreading layer 50. The current blocking layer 100 corresponds to the shape and position of the second contact electrode, and the width of the current blocking layer 100 may be widened by at least 5 micrometers with respect to the width of the second contact electrode.

A current blocking layer 100 is also disposed between the first contact electrode 71 and the first semiconductor layer 20, and the current blocking layer 100 is only located under the contact portion of the first contact electrode 71.

The insulating layer 60 is a multilayer and is defined as an m + n layer, as shown in 3~5, the insulating layer 60 includes two portions in position, a first portion 60a includes an m + n insulating layer which covers part of the second area of the substrate adjacent to the periphery of the epitaxial structure in addition to the epitaxial structure and the side wall, and the insulating layer also includes a second portion 60b which is an n layer which also covers the rest of the second area of the substrate, and m is greater than 0,n and is greater than 0.

The m layer of the m + n insulating layer may be on the n layer, as shown in fig. 5 (a); or the m layer described in the m + n insulating layer may be in the lower part of the n layer, as shown in fig. 5 (b).

The m layers in the insulating layer 60 include two material layers with different refractive indexes, which are repeatedly stacked, for example, the refractive indexes of the two material layers are different, so as to form a Distributed Bragg Reflector (DBR) layer, and the reflectivity of the light emitted by the epitaxial structure can reach over 90% under an angle of 0 to 10 degrees, so that the problem of absorption of a metal reflecting layer is solved, and the position of an energy gap can be adjusted by changing the refractive index or the thickness of the material.

The DBR layer may include titanium oxide, silicon oxide layer, hfO ₂ 、ZrO ₂ 、Nb ₂ O ₅ 、MgF ₂ And the like. Preferably, the DBR layer may be an alternating titanium oxide/silicon oxide layer structure. In this embodiment, the DBR may include 10 to 25 pairs (pairs).

The DBR layer is manufactured by adopting an optical film coating machine, such as an ion-assisted vapor deposition machine. The geometric thickness of each layer is usually 20 to 200nm.

The insulating layer 60 may also include n layers along with the DBR, which are additional insulating layers, and may include, for example, a bottom protective layer located at a lower portion of the DBR and/or a top protective layer covering an upper portion of the DBR layer. The bottom protective layer and the top protective layer may have a higher density than the DBR layer.

The bottom and top protective layers may be obtained using a fabrication process that is more dense than the DBR layer fabrication process, thereby ensuring the compactness of the protective layers, such as an ALD process or a PECVD process. Meanwhile, the bottom protective layer and the top protective layer are different from the DBR layer, the manufacturing process is different from that of the DBR layer, the material composition and/or the thickness are different from that of the DBR layer, so that the bottom protective layer and the top protective layer are different from that of the DBR layer, the compactness of the bottom protective layer and the top protective layer can be higher than that of the DBR layer, the brittleness is low, the stress is small, and therefore the cutting is not prone to cracking.

The bottom protective layer may be formed of an aluminum oxide layer or a silicon oxide layer, and preferably has at least a silicon oxide layer, which has a lower refractive index, usually 1.47, than the epitaxial structure layer, and can effectively reflect light. The silicon oxide layer can be formed by adopting PECVD.

The ALD process may have a higher dense film layer than the PECVD process, but the speed of fabricating the film layer is slower, so the bottom protective layer or the top protective layer may be multi-layered, for example, two layers, for example, a combination of the PECVD process and the ALD process shortens the fabrication process time, for example, a layer of bottom protective layer is fabricated by ALD, for example, a layer of aluminum oxide is fabricated by ALD, the thickness may be 10 to 200nm, and then a layer of bottom protective layer is fabricated by PECVD, for example, silicon oxide, the thickness may be 200 to 600nm. The ALD film may form the most dense bottom layer protection, and the thickness of the ALD film may be lower than that of the PECVD film.

Thus, the bottom protective layer may be a multilayer, for example, the bottom layer may be a double protective layer of aluminum oxide and silicon oxide.

Similarly, the top protective layer may be a single layer, such as a silicon nitride or aluminum oxide layer. The thickness of the top layer protective layer can be 10 to 200nm, for example, silicon nitride can be formed by PECVD, and an aluminum oxide layer can be formed by ALD. The top protective layer can also be a layer of silicon oxide, and the thickness can be 200 to 600nm. Alternatively, the top protective layer may be a multilayer, e.g., two layers, such as a combination of ALD-formed alumina and PECVD-formed silica.

The m insulating layers further cover part of the second area of the substrate, n layers of the m insulating layers further cover the rest of the second area of the substrate, and 0 is smaller than n and smaller than m.

The n-layer also covers the rest of the second area of the substrate and extends to the edge of the second area of the first surface of the substrate, so that the upper surface of the substrate is not exposed, the water vapor protection performance is improved, and the risk of cracking of the insulating layer is reduced when the chip is separated from the upper surface of the n-layer insulating layer.

The n layers comprise bottom layer protection layers, and the upper surfaces of the n layers are located on the bottom layer protection layers.

Or the n layer comprises a top protective layer, and the n layer comprises a top protective layer which is directly contacted with the first surface of the substrate.

The n layer does not comprise the DBR layer, so that the phenomenon that the wafer is warped and the chip is cracked due to the fact that the DBR layer is thick and large stress is caused by the manufacturing process of the DBR layer can be avoided.

In one embodiment, the m + n insulating layers include a bottom protective layer and a DBR layer, where the n insulating layers are the bottom protective layer, an aluminum oxide layer manufactured by ALD and a silicon oxide layer manufactured by PECVD on the aluminum oxide layer. The thickness of the ALD film may be less than the thickness of the PECVD film. The DBR layer comprises a silicon oxide layer, the thickness of the silicon oxide layer of the bottom protective layer is larger than that of each silicon oxide layer in the DBR layer, and the thickness matching of the aluminum oxide layer and the silicon oxide layer can be more than 1:2. For example, where the ALD layer is the densest of the m + n layers, the thickness is at least 50nm, such as 80nm; the silicon oxide layer has higher compactness than the DBR layer, and has a thickness of 200 to 400nm, such as 400nm. The m insulating layers comprise 20 pairs of DBR layers which are positioned on the bottom protective layer, and the total thickness of the DBR layers is about 4 microns. Wherein the m + n insulating layer covers the epitaxial structure and the sidewalls, and covers a portion of the second region of the substrate around the epitaxial structure. The n-layer insulating layer is a bottom protective layer, has a coverage area larger than that of the DBR, and also covers the rest of the second region of the substrate.

In one embodiment, the m + n insulating layers include a top protective layer and a DBR layer, wherein the n layers are an aluminum oxide layer formed by ALD on the top protective layer and a silicon oxide layer formed by PECVD on the aluminum oxide layer. Wherein the ALD layer is the densest layer in the m + n layers and has the thickness of 80nm; the silicon oxide layer has a higher density than the DBR layer and a thickness of 400nm. The m layers comprise 20 pairs of DBR layers which are positioned below the top protective layer, and the total thickness of the DBR layers is about 4 microns. Wherein the m + n insulating layer covers the epitaxial structure and the sidewalls, and covers a portion of the second region of the substrate, and the top protective layer has a coverage area greater than that of the DBR and covers the remaining second region of the substrate.

In one embodiment, the m + n insulating layers include a bottom passivation layer and a DBR layer, wherein the n insulating layer is a top passivation layer and is an aluminum oxide layer manufactured by ALD or a silicon oxide layer manufactured by PECVD. Wherein the ALD layer is the most dense layer of the m + n layers and has a thickness of 80nm; the silicon oxide is the most dense layer of the m + n layers and has a thickness of 400nm. The M layer comprises 20 pairs of DBR layers which are arranged on the bottom protective layer, and the total thickness of the DBR layers is about 4 microns. Wherein an m + n insulating layer covers the epitaxial structure and the sidewalls, and covers a portion of the second region of the substrate, the n layer having a coverage area greater than that of the DBR and covering the remaining second region of the substrate. For example, the aluminum oxide layer and the silicon oxide layer are located below the DBR, and the aluminum oxide layer extends beyond the lower regions of the silicon oxide layer and the DBR and covers the rest of the second region of the substrate. Or the aluminum oxide layer and the aluminum oxide layer are positioned below the DBR, the silicon oxide layer and the aluminum oxide layer exceed the lower area of the DBR and cover the rest second area of the substrate, and the thickness of the aluminum oxide layer is more than 100 nm.

In one embodiment, the m + n insulating layers include a top protective layer and a DBR layer, wherein the n insulating layer is a top protective layer and is an aluminum oxide layer manufactured by ALD, a silicon oxide layer manufactured by PECVD, or a silicon nitride layer manufactured by PECVD. Wherein the alumina layer is the most compact layer in the m + n layers and has the thickness of 80nm, or the silicon oxide is the most compact layer in the m + n layers and has the thickness of 20 to 200nm, or the silicon nitride is the most compact layer in the m layers and has the thickness of 20 to 200nm. The DBR layer is located below the top protective layer and is 20 pairs, and the total thickness of the DBR layer is about 4 microns. And the m + n insulating layers cover the epitaxial structure, the side wall and part of the second region of the substrate, the coverage area of the n layer in the m layers is larger than that of the DBR, and the n layer covers the rest of the second region of the substrate, wherein the n layer is a bottom protective layer, namely an aluminum oxide layer made by ALD (atomic layer deposition) or a silicon oxide layer made by PECVD (plasma enhanced chemical vapor deposition) or a silicon nitride layer made by PECD (plasma enhanced chemical vapor deposition).

Preferably, the width of the rest second area of the substrate is at least 2 micrometers and at most 10 micrometers, and the width of the whole second area of the substrate is 5-20 micrometers. The remaining second region of the substrate is at least 4 microns from the epitaxial structure.

The light emitting diode of the present invention is a rectangular light emitting diode, and the light emitting diode chip may be rectangular, further square or rectangular, and may be a small light emitting diode chip having a relatively small horizontal cross-sectional area. For example, the size of a square-shaped substrate is 300X 300. Mu.m ² The following may further have a particle size of 200X 200. Mu.m ² The following dimensions.

The overall thickness of the light emitting diode chip may be in the range of about 100 μm to 200 μm. The light emitting diode chip is of a flip chip type.

The embodiment of the invention also provides a specific manufacturing process of the light-emitting diode as a reference, which comprises the following steps:

a, growing a GaN buffer layer, an N-type GaN layer (a first semiconductor layer), a light-emitting layer and a P-type GaN layer (a second semiconductor layer) on a sapphire substrate in sequence;

step b, defining the size of the chip by an ICP dry etching method, and etching the table top to expose the N-type GaN layer;

c, manufacturing an ISO edge structure according to the edge of the chip through a yellow light and dry etching process;

step d, evaporating and plating a transparent current expansion layer on the P-type GaN layer, wherein the material of the expansion layer can be ITO, GTO, GZO, znO or the combination of several materials;

e, forming a first/second contact electrode by yellow light and evaporation process;

step f, manufacturing an insulating layer on the structure, firstly manufacturing a bottom protective layer, wherein the bottom protective layer comprises an aluminum oxide layer manufactured by ALD, then manufacturing a silicon oxide layer by PECVD,

and then manufacturing a Bragg reflection layer (DBR) which is an insulating layer with an alternating structure of silicon oxide layers and titanium oxide, wherein the insulating layer covers the whole chip area.

And step g, dry etching the DBR layer above the first contact electrode and the second contact electrode and on a partial region of the first surface of the substrate close to the edge, removing the DBR layer on the partial region of the first surface of the substrate close to the edge and leaving the bottom protection layer, and further etching the bottom protection layer above the epitaxial structure to expose a part of the first/second contact electrode.

Step h, manufacturing a first pad electrode and a second pad electrode again through photoetching and evaporation processes;

step i, thinning the sapphire layer of the chip formed by the process by using grinding equipment, and polishing;

and j, using invisible cutting to ablate the substrate, and cutting the chip from the surface of the bottom layer protective layer by a scribing process.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A light emitting diode, comprising:

a first pad electrode and a second pad electrode on the insulating layer;

2. A light emitting diode according to claim 1 comprising: the DBR layer includes layers in which two material layers having different refractive indexes are repeatedly stacked.

3. A light emitting diode according to claim 1 comprising: the compactness of the bottom protective layer is higher than that of the DBR layer.

4. The led of claim 1, wherein: the bottom protective layer comprises a silicon oxide layer, the DBR layer comprises a silicon oxide layer, and the thickness of the silicon oxide layer of the bottom protective layer is larger than that of the silicon oxide layer in the DBR layer.

5. The led of claim 1, wherein: the bottom protective layer comprises a silicon oxide layer and an aluminum oxide layer below the silicon oxide layer.

6. The led of claim 3, wherein: the thickness of the aluminum oxide layer is lower than that of the silicon oxide layer.

7. The led of claim 1, wherein: the bottom protective layer is an aluminum oxide layer.

8. The led of claim 6, wherein: the thickness of the silicon oxide layer is 200 to 600nm.

9. The light-emitting diode according to claim 6 or 7, wherein: the alumina layer is 10 to 200nm.

10. The light-emitting diode according to claim 5, wherein: the aluminum oxide layer and the silicon oxide layer are positioned below the DBR, and the aluminum oxide layer also exceeds the lower area of the silicon oxide layer and the DBR and covers the rest second area of the substrate.

11. The light-emitting diode according to claim 5, wherein: the aluminum oxide layer and the silicon oxide layer are positioned below the DBR, and the silicon oxide layer and the aluminum oxide layer also exceed the lower area of the DBR and cover the rest second area of the substrate.