CN115602773A - Light-emitting diode - Google Patents

Abstract

The invention relates to a design of a light-emitting diode chip, which comprises an epitaxial structure positioned on a first area of a first surface of a substrate, an insulating layer covering a second area of the substrate around the epitaxial structure, a part of the insulating layer with relatively lower compactness is removed on the second area of the substrate, the part of the insulating layer with relatively higher compactness is remained on the second area of the whole substrate, so that the risk of breakage of the insulating layer at the edge of the chip is reduced while water vapor protection is ensured, and the manufacturing yield is improved.

Description

a light emitting diode

technical field

The present invention relates to the field of semiconductor devices, in particular to a light emitting diode.

Background technique

Semiconductor light-emitting elements, or light-emitting diodes, are widely used in various products such as large backlight units, general lighting, and electrical components. Mini-LED chips (Mini-LED) are especially favored in the field of display due to their advantages of small size, high light source utilization rate, and long life.

For applications such as general lighting and electrical equipment, relatively large-sized light-emitting diodes are used in order to achieve high output in a single chip. Such light-emitting diode chips generally have dimensions of, for example, more than 700×700 μm 2 .

On the contrary, in a small backlight display unit, in order to ensure the fineness of the display, small light emitting diodes, such as light emitting diode chips with a size of 300×300 μm2 or less, are appropriately used and arranged on the backlight panel with a smaller pitch. .

The backlight source required in the display panel field requires thousands or tens of thousands of LEDs to be installed on the circuit board. Therefore, the yield and reliability of LED chips are very important to reduce costs and ensure performance. Such as water vapor protection performance, chip production yield. Moreover, as the size of mini LED continues to shrink, LED chips have higher and more stringent requirements for performance such as moisture protection performance and chip production yield.

Contents of the invention

An object of the present invention is to provide a light-emitting diode chip with high water vapor protection performance and high manufacturing yield.

Another object of the present invention is to provide a small LED chip with simple structure.

The present invention provides a kind of light-emitting diode as follows, it comprises:

a substrate, the substrate includes a first surface, the first surface is divided into a first region and a second region;

An epitaxial structure, located on the first region of the first surface of the substrate, including a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in sequence from bottom to top;

The insulating layer includes a DBR layer and an underlying protective layer below the DBR layer, and both the DBR layer and the underlying protective layer below the DBR layer cover the upper surface and side walls of the epitaxial structure;

the first pad electrode and the second pad electrode are on the insulating layer;

Wherein, the DBR layer and the underlying protection layer below the DBR layer also cover part of the second area of the substrate around the epitaxial structure, and the underlying protection layer also covers the rest of the second area of the substrate.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

1-2 are schematic cross-sectional views of existing light-emitting diodes;

FIG. 3 is a schematic top view of a light emitting diode structure provided by an embodiment of the present invention;

4 is a schematic cross-sectional view of a light emitting diode structure provided by an embodiment of the present invention;

5(a) and 5(b) are partial schematic views of the insulating layer 60a.

Reference numerals: 10, substrate; 20, first semiconductor layer; 30, light emitting layer; 40, second semiconductor layer; 50, current spreading layer; 60, insulating layer; 70, first electrode; 71, first contact 72, the first pad electrode; 80, the second electrode; 81, the second contact electrode; 82, the second pad electrode; 100, the current blocking layer; 60a, the first part of the insulating layer; 60b, the insulating layer the second part.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", The orientation or positional relationship indicated by "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying the referred device Or elements must have a certain orientation, be constructed and operate in a certain orientation, and thus should not be construed as limiting the invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and should not be understood as indicating or implying relative importance.

It should be noted that the thickness of each layer in the description and claims of the present invention refers to the geometric thickness, and also refers to the thickest thickness of each layer in the entire light-emitting diode, that is, each layer of film is in different regions because of Etching results in different thickness settings, but the thickness of each layer is defined at the position of the thickest thickness of each layer in all areas of the chip.

An existing small-sized light-emitting diode is shown in Figure 1, which includes a substrate, the substrate includes a first surface, and the first surface is divided into a first area and a second area; an epitaxial structure is located on the first surface of the substrate On the first region, it includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked in sequence from bottom to top; an insulating layer, defined as an m layer, covers the upper surface and side walls of the epitaxial structure; the first pad electrode and The second pad electrode is on the insulating layer; wherein, and the m-layer insulating layer also covers all the second regions of the substrate.

The m-layer insulating layer includes a DBR layer formed by repeated stacking of two material layers with different refractive indices. The two material layers with different refractive indices are usually silicon oxide and titanium oxide. The DBR layer uses an optical coating machine, such as ion-assisted The evaporation film machine is made, and the geometric thickness of each layer is usually between 20 and 200nm. The film layer obtained by the coating process used in the existing DBR layer is relatively brittle and has a large stress, and the total thickness of the insulating layer is usually 3~6 microns, the thickness is thicker. Before the cutting and separation step in the chip manufacturing process, such a thick insulating layer is continuously covered on the wafer that has not been cut and separated. The stress is greater, and the entire wafer is prone to warping and high brittleness. After the cutting and separation steps, the insulating layer at the edge of the chip is prone to cracks, resulting in low chip production yield.

Another existing light-emitting diode, as shown in Figure 2, differs from the structure shown in Figure 1 in that the m-layer insulating layer only covers part of the upper surface of the substrate around the epitaxial structure, exposing part of the substrate. The upper surface, that is, the insulating layer of each chip is disconnected before the cutting and separation step in the chip manufacturing process, thereby reducing the risk of wafer warpage caused by the stress of the entire insulating layer and the risk of the insulating layer being easily broken at the edge, and improving the reliability of the chip. Production yield.

However, if the insulating layer exposes part of the upper surface of the substrate, if the width of the upper surface of the substrate that is not occupied by the epitaxial structure is not widened, the edge of the insulating layer is closer to the epitaxial structure, and water vapor is easy to enter the epitaxial structure. Not enough; if the width of the upper surface of the substrate around the epitaxial structure is widened, the number of chip particles produced by a single wafer is reduced, which increases the production cost of the chip.

Therefore, the present invention provides the following light-emitting diode, which is improved based on the existing structure, including the epitaxial structure located in the first region of the first surface of the substrate, and the insulating layer covering the second region of the substrate around the epitaxial structure, dense Part of the insulating layer with relatively lower density is removed on the second region of the substrate, and a part of the insulating layer with relatively higher density remains on the second region of the entire substrate, thereby ensuring water vapor protection and reducing the chip temperature. The risk of warpage and cracking of the insulation layer improves the manufacturing yield.

The invention provides a kind of light-emitting diode, it comprises:

a substrate, the substrate includes a first surface, the first surface is divided into a first region and a second region;

An epitaxial structure, located on the first region of the first surface of the substrate, including a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in sequence from bottom to top;

The insulating layer includes a DBR layer and an underlying protective layer below the DBR layer, and both the DBR layer and the underlying protective layer below the DBR layer cover the upper surface and side walls of the epitaxial structure;

the first pad electrode and the second pad electrode are on the insulating layer;

Wherein, the DBR layer and the underlying protection layer below the DBR layer also cover part of the second area of the substrate around the epitaxial structure, and the underlying protection layer also covers the rest of the second area of the substrate.

Specifically, in this embodiment, the light-emitting diodes described in the following detailed description will be described in conjunction with accompanying drawings 3 to 5, including:

Substrate 10;

Optionally, the substrate 10 includes at least one of sapphire (aluminum oxide layer), SiC, GaAs, GaN, ZnO, GaP, InP and Ge, and is not limited to the examples listed here.

The type of light-emitting diode in this embodiment is a flip-chip light-emitting diode, preferably a sapphire substrate. The light-emitting layer 30 is a multi-quantum well layer. The sapphire substrate has two opposite sides, wherein the lower side is used as a light-emitting surface, and the upper side is a light-emitting surface. The side stacks have epitaxial structures.

The epitaxial structure on the substrate includes the first semiconductor layer 20, the light-emitting layer 30 and the second semiconductor layer 40 stacked sequentially on the substrate from bottom to top. Preferably, the epitaxial structure also includes an electrode mesa, and the electrode mesa has a penetrating The slope of the second semiconductor layer 40 , the light emitting layer 30 , and a part of the planar area of the first semiconductor layer 20 are exposed. Preferably, looking down on the first semiconductor layer 20 from the side of the second semiconductor layer 40, the surface of the planar area is in the form of a ring around the light-emitting layer, and the planar area has a local widening on one side of the light-emitting layer for installation Subsequent to the first contact electrode.

As an example, the first semiconductor layer 20 may be an N-type GaN layer, and the second semiconductor layer 40 may be a P-type GaN layer. Wherein the N-type is a silicon-based doping type, and the P-type is a magnesium-based doping type.

The epitaxial structure is a gallium nitride-based epitaxial layer or a gallium arsenide-based epitaxial layer. Through the material selection of the light-emitting layer, it can provide luminous radiation between 380 and 700nm, such as blue light, green light or red light with a single peak wavelength.

Preferably, there is a transparent current spreading layer 50 on the second semiconductor layer 40 . The current spreading layer forms an ohmic contact with the second semiconductor layer, and is formed on the second semiconductor layer 40 nearly the entire surface (at least 90% of the coverage area). The current spreading layer realizes the lateral transmission in the horizontal direction of the current at the same time.

The material of the current spreading layer 50 can be a metal oxide, and the current spreading layer is a relatively transparent material that can allow at least part of the radiation of the light-emitting layer to pass through, such as one or more combinations of ITO, GTO, GZO, and ZnO, and Not limited to the examples listed here, preferably, the thickness of the current spreading layer is 30-200 nm.

The first electrode 70 is electrically connected to the first semiconductor layer 20, including a first contact electrode 71 and a first pad electrode 72, wherein the first contact electrode 71 is located in the planar region of the first semiconductor layer 20 of the electrode mesa above, forming an ohmic contact with the first semiconductor layer 20 .

The second electrode 80 is located on the second semiconductor layer 40 , electrically connected to the second semiconductor layer 40 , and includes a second contact electrode 81 and a second pad electrode 82 .

In this embodiment, the first electrode 70 and the second electrode 80 are metal electrodes such as nickel, gold, chromium, titanium, platinum, palladium, rhodium, iridium, aluminum, tin, indium, tantalum, copper, cobalt, iron , ruthenium, zirconium, tungsten, molybdenum and one or a combination thereof.

As an example, the first electrode 70 may be an N electrode, and the second electrode 80 may be a P electrode.

As an example, the first pad electrode 72 may be an N pad electrode, and the second pad electrode 82 may be a P pad electrode.

As an embodiment, the second contact electrode 81 is located on the second semiconductor layer, is located on the transparent current spreading layer 50 , and is in contact with the transparent current spreading layer 50 .

The insulating layer 60 is located on the epitaxial structure, specifically on the second semiconductor layer 40, on the planar region of the first semiconductor layer 20 and on the slope of the electrode mesa, and covers the first contact The electrode 71 , the second contact electrode 81 , the first pad electrode 72 and the second pad electrode 82 are formed on the insulating layer 60 . The insulating layer may allow most of the light to pass through or allow most of the light to be reflected.

Wherein, the insulating layer 60 covers the upper surface and the sidewall of the epitaxial structure, and covers the transparent current spreading layer 50 and the first contact electrode 71 and the second contact electrode 81 .

The insulating layer 60 is provided with a through hole penetrating through the insulating layer 60 , as shown in FIG. 4 , the through hole is located on the first contact electrode 71 and the second contact electrode 81 . The insulating layer 60 has a first through hole 73 on the contact portion of the first contact electrode 71 .

The first pad electrode 72 and the second pad electrode 82 are respectively in contact with the contact portions of the first contact electrode 71 and the second contact electrode 81 through the through holes provided on the insulating layer 60 . The shortest distance between the first pad electrode and the second pad electrode is 60-300 μm.

A current blocking layer 100 is further disposed between the transparent current spreading layer 50 and the second semiconductor layer 40 . The current blocking layer 100 is disposed under the second contact electrode at the same time, and is used to block current from being transmitted vertically and longitudinally between the second contact electrode and the second semiconductor layer, so as to promote the lateral transmission function of the current spreading layer 50 . The shape and position of the current blocking layer 100 correspond to the second contact electrode, and the width of the current blocking layer 100 can be wider by at least 5 microns relative to the width of the second contact electrode.

There is also a current blocking layer 100 between the first contact electrode 71 and the first semiconductor layer 20 , and the current blocking layer 100 is only located under the contact portion of the first contact electrode 71 .

The insulating layer 60 is a multi-layer, defined as an m+n layer, as shown in Figures 3 to 5, the insulating layer 60 includes two parts in position, the first part 60a includes an m+n layer of insulating layer except covering the epitaxial Structurally and on the sidewalls, it also covers part of the second region of the substrate adjacent to the epitaxial structure, and the insulating layer further includes a second part 60b, the second part is an n layer and covers the remaining second region of the substrate , m is greater than 0, and n is greater than 0.

The m layer mentioned in the m+n insulating layer can be in the upper part of the n layer, as shown in Figure 5(a); or the m layer mentioned in the m+n insulating layer can be in the lower part of the n layer, as shown in Figure 5(a) 5(b).

The m layer in the insulating layer 60 includes two layers of material layers with different refractive indices that are repeatedly stacked. ° angle, the epitaxial structure has a reflectivity of more than 90%, it does not have the absorption problem of the metal reflective layer, and the position of the energy gap can be adjusted by changing the refractive index or thickness of the material.

The DBR layer may include titanium oxide, silicon oxide layer, HfO ₂ , ZrO ₂ , Nb ₂ O ₅ , MgF ₂ and the like. Preferably, the DBR layer may have a structure of alternately stacked titanium oxide layers/silicon oxide layers. In this embodiment, the DBR may include 10 to 25 pairs.

The DBR layer is made by an optical film coating machine, such as an ion-assisted evaporation film machine. The geometric thickness of each layer is usually between 20~200nm.

The insulating layer 60 together with the distributed Bragg reflector may further include an n-layer, which is an additional insulating layer, for example, may include a bottom protective layer under the DBR and/or a top protective layer covering the top of the DBR layer. The density of the bottom protective layer and the top protective layer may be higher than that of the DBR layer.

The bottom layer and the top protective layer can be obtained by using a manufacturing process with better density than the DBR layer manufacturing process, so as to ensure the denseness of the protective layer, such as ALD process or PECVD process. At the same time, these bottom protection layers and top protection layers are different from the DBR layer, their manufacturing process is different from the DBR layer, and the material composition and or thickness are different from the DBR layer, so that they are different from the DBR layer, and the bottom protection layer and the top layer The denseness of the protective layer may be higher than that of the DBR layer, and the brittleness is lower, and the stress is smaller, so it is not easy to break after cutting.

The underlying protective layer can be formed of an aluminum oxide layer or a silicon oxide layer, preferably at least with a silicon oxide layer. The silicon oxide layer has a lower refractive index than the epitaxial structure layer, usually 1.47, and can resist light. Make effective reflections. The silicon oxide layer can be formed by PECVD.

Among them, the ALD process can have a higher density film layer than PECVD, but its production rate is slower, so the bottom protective layer or the top protective layer can be multi-layered, such as two layers, such as a combination of PECVD and ALD processes In order to shorten the production process time, for example, first use ALD to make a layer of bottom protection layer, such as ALD to make a layer of aluminum oxide, the thickness can be 10~200nm, and then use PECVD to make a layer of bottom protection layer, such as silicon oxide, the thickness of the layer It can be 200~600nm. The film layer formed by ALD can form the densest underlying protection, and the thickness of the film layer of ALD can be lower than that of the film layer produced by PECVD.

Therefore, the bottom protection layer may be multi-layered, for example, the bottom layer may be a double protection layer of aluminum oxide and silicon oxide.

Similarly, the top protection layer may be a single layer, such as a silicon nitride or aluminum oxide layer. The thickness of the top protection layer may be 10-200 nm, for example, PECVD may be used to form silicon nitride, and ALD may be used to form an aluminum oxide layer. The top protective layer can also be a layer of silicon oxide, and the thickness can be 200-600nm. Alternatively, the top protection layer may be multilayer, for example two layers, such as a combination of aluminum oxide formed by ALD and silicon oxide formed by PECVD.

The m insulating layers also cover part of the second region of the substrate, and n layers of the m insulating layers also cover the rest of the second region of the substrate, where 0 is smaller than n and smaller than m.

The n-layer also covers the remaining second region of the substrate and extends to the edge of the second region of the first surface of the substrate, thereby ensuring that the upper surface of the substrate is not exposed, thereby improving the water vapor protection performance. Lifting, and starting to separate the chip from the upper surface of the n-layer insulating layer, the risk of insulating layer cracking is reduced.

The n layer includes a bottom protection layer, and the upper surface of the n layer is located on the bottom protection layer.

Or the n layer includes a top protective layer, and the n layer includes the top protective layer directly contacting the first surface of the substrate.

The n layer does not include the DBR layer, thereby avoiding the thicker DBR film layer and the greater stress caused by its manufacturing process, which will cause wafer warping and chip cracking.

As an embodiment, the m+n insulating layer includes a bottom protection layer and a DBR layer, wherein the n layer is the bottom protection layer, an aluminum oxide layer made by ALD, and a silicon oxide layer made by PECVD on the aluminum oxide layer. The thickness of the film layer of ALD can be lower than the thickness of the film layer produced by PECVD. The DBR layer includes a silicon oxide layer, the thickness of the silicon oxide layer of the underlying protective layer is greater than the thickness of each silicon oxide layer in the DBR layer, and the thickness of the aluminum oxide layer and the silicon oxide layer The match can be more than 1:2. For example, the ALD layer is the densest layer among the m+n layers, with a thickness of at least 50nm, such as 80nm; the silicon oxide layer is denser than the DBR layer, with a thickness of 200-400nm, such as 400nm. The m-layer insulation layer includes 20 pairs of the DBR layer located on the bottom protective layer, and the total thickness of the DBR layer is about 4 microns. Wherein the m+n insulating layer covers the epitaxial structure and the sidewall, and covers part of the second region of the substrate around the epitaxial structure. The n-layer insulating layer is a bottom protection layer, the covering area is larger than the covering area of the DBR, and also covers the rest of the second area of the substrate.

As an embodiment, the m+n insulating layer includes a top protective layer and a DBR layer, wherein the n layer is an aluminum oxide layer made of ALD for the top protective layer and a silicon oxide layer made of PECVD on the aluminum oxide layer. The ALD layer is the densest layer among the m+n layers, with a thickness of 80nm; the density of the silicon oxide layer is higher than that of the DBR layer, and the thickness is 400nm. The m layer includes 20 pairs of DBR layers located under the top protective layer, and the total thickness of the DBR layers is about 4 microns. Wherein the m+n insulating layer covers the epitaxial structure and the sidewall, and covers part of the second region of the substrate, and the covering area of the top protective layer is larger than that of the DBR, and covers the rest of the second region of the substrate. on the second area.

As an embodiment, the m+n insulating layer includes a bottom protective layer and a DBR layer, wherein the n insulating layer is a top protective layer, an aluminum oxide layer made by ALD or a silicon oxide layer made by PECVD. The ALD layer is the densest layer in the m+n layer with a thickness of 80nm; the silicon oxide is the densest layer in the m+n layer with a thickness of 400nm. The M layer includes the above-mentioned DBR layer, which is located on the bottom protective layer, and there are 20 pairs, and the total thickness of the DBR layer is about 4 microns. Wherein the m+n insulating layer covers the epitaxial structure and the sidewall, and covers a part of the second region of the substrate, the covering area of the n layer is larger than the covering area of the DBR, and covers the rest of the second region of the substrate area. For example, the aluminum oxide layer and the silicon oxide layer are located under the DBR, and the aluminum oxide layer also exceeds the area below the silicon oxide layer and the DBR, covering the remaining second area of the substrate. Alternatively, the aluminum oxide layer and the silicon oxide layer are located below the DBR, and the silicon oxide layer and the aluminum oxide layer also exceed the lower area of the DBR and cover the remaining second area of the substrate. The thickness of the aluminum layer is 100 nm or more.

As an embodiment, the m+n insulating layer includes a top protective layer and a DBR layer, wherein the n insulating layer is a top protective layer, an aluminum oxide layer made by ALD or a silicon oxide layer made by PECVD or PECVD fabricated silicon nitride layer. Among them, the aluminum oxide layer is the densest layer in the m+n layer with a thickness of 80nm, or silicon oxide is the densest layer in the m+n layer with a thickness of 20~200nm, or silicon nitride is the densest layer in the m layer layer with a thickness of 20-200nm. There are 20 pairs of DBR layers located under the top protective layer, and the total thickness of the DBR layers is about 4 microns. Wherein the m+n insulating layer covers the epitaxial structure and the sidewall, and covers part of the second region of the substrate, the n layer in the m layer covers an area larger than the DBR, and covers the substrate On the rest of the second area, the n layer is the bottom protection layer, that is, an aluminum oxide layer made by ALD or a silicon oxide layer made by PECVD or a silicon nitride layer made by PECD.

Preferably, the width of the remaining second region of the substrate is at least 2 microns and at most 10 microns, and the width of the entire second region of the substrate is 5-20 microns. The remaining second region of the substrate is at least 4 microns away from the epitaxial structure.

The light-emitting diode of the present invention is a rectangular light-emitting diode, and the light-emitting diode chip can be in a rectangular shape, and further can be in a square shape or a rectangular shape, and can be a small light-emitting diode chip with a relatively small horizontal cross-sectional area. For example, the size of a square-shaped substrate is 300×300 μm ² or less, and may further have a size of 200×200 μm ² or less.

The overall thickness of the LED chip may be in the range of about 100 μm to 200 μm. The light emitting diode chip is a flip-chip type.

The embodiment of the present invention also provides a specific manufacturing process of light-emitting diodes as a reference, including the following steps:

Step a, sequentially growing a GaN buffer layer, an N-type GaN layer (first semiconductor layer), a light-emitting layer, and a P-type GaN layer (second semiconductor layer) on a sapphire substrate;

Step b. Define the chip size by ICP dry etching, and carve out the mesa to expose the N-type GaN layer;

Step c, making the ISO edge structure according to the edge of the chip through yellow light and dry etching process;

Step d, evaporating a transparent current spreading layer on the P-type GaN layer, the material of the spreading layer can be ITO, GTO, GZO, ZnO or a combination of several kinds;

Step e, forming the first/second contact electrode by yellow light and evaporation process;

Step f, making an insulating layer on the above structure, first making a bottom protective layer, the bottom protective layer includes ALD to make a layer of aluminum oxide layer, and then PECVD to make a layer of silicon oxide layer,

Next, a layer of Bragg reflective layer (DBR) is fabricated, which is an insulating layer with an alternating structure of silicon oxide and titanium oxide, and the insulating layer covers the entire chip area.

Step g, dry etching the DBR layer above the first contact electrode and the second contact electrode and on the partial area of the first surface of the substrate close to the edge, and removing the DBR layer on the partial area of the first surface of the substrate close to the edge And the underlying protective layer is left, and the underlying protective layer is further etched on the epitaxial structure to expose part of the first/second contact electrodes.

Step h, making the first pad electrode and the second pad electrode again by photolithography and evaporation process;

Step i, using grinding equipment to thin the sapphire layer of the chip formed by the above process, and polish;

Step j, using stealth dicing to ablate the substrate and scribing the chip from the surface of the underlying protective layer.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (11)

1. A light emitting diode, comprising:

the device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a first surface which is divided into a first area and a second area;

the epitaxial structure is positioned on a first area of the first surface of the substrate and comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially laminated from bottom to top;

the insulating layer comprises a DBR layer and a bottom protective layer below the DBR layer, and the upper surface and the side wall of the epitaxial structure are covered by the DBR layer and the bottom protective layer below the DBR layer;

a first pad electrode and a second pad electrode on the insulating layer;

wherein the DBR layer and the underlying protective layer below the DBR layer further overlie a portion of the second region of the substrate surrounding the epitaxial structure, and said underlying protective layer further overlies the remaining second region of the substrate.

2. A light emitting diode according to claim 1 comprising: the DBR layer includes layers in which two material layers having different refractive indexes are repeatedly stacked.

3. A light emitting diode according to claim 1 comprising: the compactness of the bottom protective layer is higher than that of the DBR layer.

4. The led of claim 1, wherein: the bottom protective layer comprises a silicon oxide layer, the DBR layer comprises a silicon oxide layer, and the thickness of the silicon oxide layer of the bottom protective layer is larger than that of the silicon oxide layer in the DBR layer.

5. The led of claim 1, wherein: the bottom protective layer comprises a silicon oxide layer and an aluminum oxide layer below the silicon oxide layer.

6. The led of claim 3, wherein: the thickness of the aluminum oxide layer is lower than that of the silicon oxide layer.

7. The led of claim 1, wherein: the bottom protective layer is an aluminum oxide layer.

8. The led of claim 6, wherein: the thickness of the silicon oxide layer is 200 to 600nm.

9. The light-emitting diode according to claim 6 or 7, wherein: the alumina layer is 10 to 200nm.

10. The light-emitting diode according to claim 5, wherein: the aluminum oxide layer and the silicon oxide layer are positioned below the DBR, and the aluminum oxide layer also exceeds the lower area of the silicon oxide layer and the DBR and covers the rest second area of the substrate.

11. The light-emitting diode according to claim 5, wherein: the aluminum oxide layer and the silicon oxide layer are positioned below the DBR, and the silicon oxide layer and the aluminum oxide layer also exceed the lower area of the DBR and cover the rest second area of the substrate.

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