CN115602736A - Solar cell and photovoltaic cell module - Google Patents

Abstract

The embodiment of the invention provides a solar cell and a photovoltaic cell module, wherein the solar cell comprises: a semiconductor substrate; the first grid lines are arranged on the surface of the semiconductor substrate along a first direction; the second grid lines are arranged on the surface of the semiconductor substrate along a second direction, and the second grid lines are perpendicular to and intersect with the first grid lines; the second gate line includes: a neighboring portion connected to the first gate line; the extending part is connected with the adjacent part, the adjacent part is positioned between the first grid line and the extending part, and the length of the extending part is at least 0.8 of the length of the second grid line in the direction parallel to the first direction; the solder mask layer is positioned on the surface of the second grid line and at least covers the surface of the extension part; and the third grid line is arranged on the surface of the semiconductor substrate along the second direction and is vertical to the first grid line. The embodiment of the invention is beneficial to improving the condition that the junction area of the third grid line and the first grid line is broken in the process of manufacturing the photovoltaic cell.

Description

Solar cell and photovoltaic cell module

Technical Field

The embodiment of the invention relates to the field of photovoltaics, in particular to a solar cell and a photovoltaic cell assembly.

Background

The solar cell is a photoelectric semiconductor structure which generates electricity by using sunlight, and can output voltage and generate current under the condition of a loop as long as the solar cell is illuminated under a certain illumination condition.

Generally, a solar cell is manufactured on the basis of a silicon wafer through production processes of texturing, diffusion, cleaning, film coating, screen printing and the like, wherein in the screen printing process, conductive slurry is printed on the front surface and/or the back surface of the solar cell according to a certain screen printing pattern, the printed structure comprises a main grid and an auxiliary grid, and the auxiliary grid collects photogenerated current of the solar cell onto the main grid. Different solar cells are welded together to form the photovoltaic cell module, and the welding process mainly comprises the step of welding the main grid with a welding strip.

However, the photoelectric conversion efficiency and the service life of the current photovoltaic cell module need to be improved.

Disclosure of Invention

The technical problem solved by the embodiment of the invention is to provide a solar cell and a photovoltaic cell assembly, which can improve the grid breaking phenomenon of the junction area of a first grid line and a third grid line in the solar cell.

In order to solve the above problems, an embodiment of the present invention provides a solar cell, including a semiconductor substrate; the first grid lines are arranged on the surface of the semiconductor substrate along a first direction; the second grid lines are arranged on the surface of the semiconductor substrate along a second direction, are perpendicular to and intersect with the first grid lines, and have a thickness smaller than that of the first grid lines in the direction perpendicular to the surface of the semiconductor substrate; the second gate line includes: an adjacent portion connected to the first gate line; an extending portion connected to the adjacent portion, the adjacent portion being located between the first gate line and the extending portion, a length of the extending portion being greater than or equal to a length of the adjacent portion in a direction parallel to the first direction; the solder mask layer is positioned on the surface of the second grid line and at least covers the top surface of the extension part; and the third grid line is arranged on the surface of the semiconductor substrate along the second direction and is vertical to the first grid line, wherein the third grid line also covers the first grid line, the solder mask layer and the second grid line, and the third grid line is electrically connected with at least 2 first grid lines.

In addition, the solder resist layer covers the entire top surface of the second gate line.

In addition, the thickness of the solder mask layer is 5nm to 10nm in the direction vertical to the surface of the semiconductor substrate.

In addition, the material of the solder resist layer includes epoxy resin or polyester resin.

In addition, in a direction parallel to the second direction, the width of the second gate line is greater than or equal to the width of the third gate line.

In addition, in the direction perpendicular to the surface of the semiconductor substrate, the thickness of the second grid line is 0.4-1 of the thickness of the third grid line.

In addition, the thickness of the second grid line is 0.004 mm-0.016 mm in the direction vertical to the surface of the semiconductor substrate.

In addition, the width of the second grid line is 0.02 mm-0.05 mm in the direction parallel to the second direction.

In addition, the length of the second grid line is 0.3 mm-0.6 mm in the direction parallel to the first direction. In addition, the first grid line and the second grid line are of an integrated structure.

In addition, the first gate line includes: the surface of the transition part is connected with the second grid line; wherein the transition portion has a thickness on a surface perpendicular to the semiconductor substrate that gradually decreases in a direction directed toward the second gate line along the flat portion.

In addition, an embodiment of the present invention further provides a photovoltaic cell module, including: the solar cell string is formed by electrically connecting the solar cells.

Compared with the related art, the technical scheme provided by the embodiment of the invention has the following advantages:

in the above technical scheme, a plurality of second gate lines which are perpendicular to and intersect with the first gate lines are arranged on the first gate lines, a solder mask is arranged on the surface of each second gate line, the solder mask at least covers the top surfaces of the extending portions of the second gate lines, and the extending portions are portions, far away from the first gate lines, of the second gate lines and are in junction with the third gate lines. The second grid line and the first grid line junction area are of a laminated structure of the second grid line and the third grid line, so that the thickness of the laminated structure of the first grid line and the third grid line junction area is increased, and the probability that the solder strip penetrates into the first grid line and the third grid line junction area to separate the first grid line and the third grid line is reduced; in addition, by arranging the second grid lines, compared with the scheme that the thickness of the third grid lines is increased integrally, the scheme that the second grid lines are arranged can save the slurry consumption for manufacturing the second grid lines and the third grid lines, and the cost of the solar cell is reduced. Meanwhile, due to the arrangement of the solder mask layer, solder strips can be prevented from melting tin and flowing into a junction area of the second grid line and the third grid line, so that grid breakage between the second grid line and the third grid line is prevented, and even if the length of the second grid line is short, the risk of grid breakage between the second grid line and the third grid line is reduced due to the arrangement of the solder mask layer. Therefore, the solar cell provided by the embodiment of the invention can effectively ensure the quality of the solar cell while saving the cost, so that a photovoltaic cell module manufactured by using the solar cell has low cost, high photoelectric conversion efficiency and long service life.

In addition, the orthographic projection of the second grid line on the surface of the semiconductor substrate is a first projection, the orthographic projection of the part, located right above the second grid line, of the third grid line on the surface of the semiconductor substrate is a second projection, and the first projection is overlapped with the second projection, or the second projection is located in the first projection. The first projection and the second projection are overlapped, so that the thickness of a junction area of the first grid line and the third grid line is increased, and the light receiving area of the solar cell piece can be unchanged, thereby ensuring that the solar cell piece has high photoelectric conversion efficiency.

In addition, the solder mask covers the whole top surface of the second grid line, so that the capability of the solder mask for blocking the solder strip from flowing to the junction area of the second grid line and the third grid line is further improved, and the risk of grid breakage of the junction area of the second grid line and the third grid line is further reduced.

Drawings

One or more embodiments are illustrated by corresponding figures in the drawings, which are not to scale unless otherwise specified.

FIG. 1 is a schematic diagram of a cross-sectional structure corresponding to a photovoltaic cell structure;

fig. 2 is a schematic top view of a solar cell according to an embodiment of the present invention;

fig. 3 is a schematic top view of a connection between a first gate line and a second gate line according to an embodiment of the present invention;

fig. 4 is a schematic cross-sectional view of a solar cell according to an embodiment of the invention;

fig. 5 is a schematic cross-sectional view of a solar cell according to an embodiment of the invention;

fig. 6 is a schematic cross-sectional view of a solar cell according to an embodiment of the invention;

fig. 7 is a schematic cross-sectional view of a solar cell according to an embodiment of the invention;

fig. 8 is a schematic cross-sectional view of a photovoltaic cell assembly according to an embodiment of the present invention;

fig. 9 is a schematic cross-sectional view of a photovoltaic cell module according to an embodiment of the invention.

Detailed Description

As can be seen from the background art, the photoelectric conversion efficiency and the service life of the current photovoltaic cell module are both to be improved.

Through analysis, after Electroluminescence (EL) detection is performed on the photovoltaic cell assembly, it is found that an EL image is dark, which indicates that a junction area between the main grid and the auxiliary grid of the photovoltaic cell assembly has a grid breaking problem, that is, a local or whole junction area between the main grid and the auxiliary grid is broken. Such a problem directly affects the collection of photo-generated current, thereby affecting the photoelectric conversion efficiency of the photovoltaic cell module; in addition, during the use of the photovoltaic cell assembly with the grid breaking problem, the grid breaking position can generate a hot spot phenomenon of local heating, and the service life of the photovoltaic cell assembly is influenced.

The problem of grid breakage is not found when the solar cell before welding is subjected to EL detection. Therefore, during the process of welding the solar cell pieces to form the photovoltaic cell module, the problem of fracture or loss of the conductive material at the boundary area of the main grid and the auxiliary grid is caused.

Referring to fig. 1, fig. 1 is a schematic partial cross-sectional view of a photovoltaic cell module in the related art, the photovoltaic cell module including: the semiconductor device comprises a semiconductor substrate 0, wherein a plurality of main grids 1 are arranged on the surface of the semiconductor substrate 0, and auxiliary grids 2 are vertically intersected with the main grids 1; the main grid 1 is provided with a solder strip molten tin 3, and the solder strip molten tin 3 connects the main grid 1 with a solder strip body 4.

During the formation of the photovoltaic cell assembly by soldering, the solder strip molten tin 3 penetrates into the boundary area of the main grid 1 and the auxiliary grid 2, namely, the solder strip molten tin 3 separates the main grid 1 and the auxiliary grid 2, and the grid breaking phenomenon between the main grid 1 and the auxiliary grid 2 occurs. In addition, for the scheme that a lower slurry dosage is required in the manufacturing process of the photovoltaic cell module, due to the low slurry dosage, the thickness of the corresponding main grid 1 and/or the corresponding auxiliary grid 2 is correspondingly lower, and then the length of the interface corresponding to the boundary region is relatively shorter, that is, the penetration path required by the solder strip molten tin 3 to break the main grid 1 and the auxiliary grid 2 is shortened, which results in higher probability of grid breakage. It is understood that the paste is a raw material for printing the main gate 1 and the sub-gate 2, and the length of the interface refers to a length on a surface perpendicular to the semiconductor substrate 0.

In order to solve the above problem, an embodiment of the present invention provides a solar cell, wherein second gate lines are disposed on two sides of a first gate line, the second gate lines are perpendicular to the first gate line, and a solder resist layer is disposed on a surface of the second gate line away from the first gate line. Therefore, the thickness of the junction area of the first grid line and the third grid line can be increased, and the solder strip can be prevented from being melted to flow to the junction area of the second grid line and the third grid line, so that the risk of grid breakage of the junction area of the second grid line and the third grid line is reduced.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

Fig. 2 to 7 are corresponding structural schematic diagrams of a solar cell according to an embodiment of the invention, and fig. 2 is a schematic top-view structural schematic diagram according to an embodiment of the invention; FIG. 3 is a schematic top view of a primary gate and a secondary gate connection according to an embodiment of the present invention; FIG. 4 is a schematic view of a first cross-sectional structure of FIG. 2 taken along direction AA 1; FIG. 5 is a schematic view of a second cross-sectional configuration of FIG. 2 taken along direction AA 1; FIG. 6 is a schematic view of a third cross-sectional structure of FIG. 2 taken along direction AA 1; FIG. 7 is a schematic view of a fourth cross-sectional structure of FIG. 2 taken along direction AA 1.

Referring to fig. 2 to 4, in the present embodiment, the solar cell includes: a semiconductor substrate 100; the semiconductor device includes a first gate line 101, wherein the first gate line 101 is arranged on the surface of a semiconductor substrate 100 along a first direction; a second gate line 102, wherein the second gate line 102 is arranged on the surface of the semiconductor substrate 100 along a second direction, the second gate line 102 is perpendicular to and intersects the first gate line 101, and the thickness of the second gate line 102 is smaller than that of the first gate line 101 in the direction perpendicular to the surface of the semiconductor substrate 100; the second gate line 102 includes: a neighboring portion 10, the neighboring portion 10 being connected to the first gate line 101; an extending portion 11, wherein the extending portion 11 is connected to the adjacent portion 10, the adjacent portion 10 is located between the first gate line 101 and the extending portion 11, and a length of the extending portion 11 is at least 0.8 of a length of the second gate line 102 in a direction parallel to the first direction; the solder mask layer 103, the solder mask layer 103 is located on the surface of the second gate line 102 and covers at least the top surface of the extension portion 11; and a third gate line 104, wherein the third gate line 104 is arranged on the surface of the semiconductor substrate 100 along the second direction and is perpendicular to the first gate line 101, the third gate line 104 further covers the first gate line 101, the solder resist layer 103 and the second gate line 102, and the third gate line 104 is electrically connected to at least 2 first gate lines 101.

The second grid lines 102 are arranged on two sides of the first grid line 101, and the second grid lines 102 and the third grid lines 104 jointly form the auxiliary grid, so that the thickness of a boundary area between the first grid line 101 and the auxiliary grid is increased, and the problem of grid breakage between the first grid line 101 and the auxiliary grid in the process of forming the photovoltaic cell assembly is avoided. The solder mask layer 103 covers the extending portion of the second gate line 102, and the solder mask layer 103 is favorable for blocking solder melting of the solder strip from flowing to the junction area of the second gate line 102 and the third gate line 104, so that the risk of grid breakage of the junction area of the second gate line 102 and the third gate line 104 is reduced.

The solar cell module provided in the present embodiment will be described in more detail below with reference to the accompanying drawings.

The material of the semiconductor substrate 100 is mainly single crystal silicon or polycrystalline silicon, and the semiconductor substrate 100 includes a light receiving surface facing the sun and a backlight surface opposite to the light receiving surface. Further, in some embodiments, the solar cell is a bifacial cell, and the light receiving surface and/or the backlight surface of the semiconductor substrate 100 can generate photogenerated carriers; in other embodiments, the solar cell is a single-sided cell, and only the light-receiving surface of the semiconductor substrate 100 can generate photogenerated carriers.

In this embodiment, taking a solar cell as an example of a double-sided cell, both the light receiving surface and the backlight surface of the semiconductor substrate 100 can generate light-generated carrier ions. A plurality of solar cells are welded by welding to form a photovoltaic cell module, and the welding operation increases new materials on the surfaces of the solar cells to shield a part of the surface of the semiconductor substrate 100, so that the photoelectric conversion efficiency of the solar cells is reduced.

The first gate line 101 may be a main gate for collecting the photo-generated current collected by the sub-gate.

In this embodiment, the first gate lines 101 are distributed at intervals along the first direction on the backlight surface of the semiconductor substrate 100. In other embodiments, the first gate lines may also be distributed on the light receiving surface of the semiconductor substrate. In addition, the first gate lines 101 may be solid strips or hollow strips, and the number of the first gate lines 101 may be 5 to 15, for example, 5, 6, or 9, and the number of the first gate lines 101 may be set reasonably according to the size of the solar cell. In some embodiments, the number of the first gate lines 101 is set to be more than 9, so that the width of the first gate lines 101 can be made narrower to save the paste. For example, the width of the first gate line may be 0.025mm to 0.04mm.

In the present embodiment, the width of the first gate line 101 in the second direction may be 0.04mm, and the thickness of the first gate line 101 in the direction perpendicular to the surface of the semiconductor substrate 100 may be 7 μm to 9 μm, for example, 7.5 μm, 8 μm, or 8.5 μm.

A silver-containing paste may be used as the material of the first gate line 101. In some embodiments, the first gate line 101 may include: a flat portion 13 and a transition portion 12 located at opposite sides of the flat portion 13, and a surface of the transition portion 12 is connected to the adjacent portion 10. Wherein the transition portion 12 has a thickness on a surface perpendicular to the semiconductor substrate 100 that gradually decreases in a direction pointing toward the second gate line 102 along the flat portion 13. That is, in a cross section perpendicular to the surface of the semiconductor substrate 100 and perpendicular to the extending direction of the first gate line 101, the cross section of the first gate line 101 may be trapezoidal.

It is understood that, in other embodiments, the cross-sectional shape of the first gate line in a cross-section perpendicular to the surface of the semiconductor substrate and perpendicular to the extending direction of the first gate line may also be rectangular.

The second gate line 102 may be a first sub-gate as a portion of the sub-gate, and forms a sub-gate together with the third gate line 104 for collecting a photo-generated current generated by a photo-generated voltage. The arrangement of the second gate line 102 is beneficial to increasing the thickness of the paste in the boundary area between the first gate line 101 and the auxiliary gate, that is, the thickness of the laminated structure formed by the first gate line 101 and the auxiliary gate in the boundary area is increased, so that the problem that the solder strip melts the boundary area between the first gate line 101 and the auxiliary gate during welding is effectively avoided, and the gate is broken between the first gate line 101 and the auxiliary gate is further avoided. In addition, compared with the scheme of increasing the overall thickness of the sub-grid, in the embodiment, the thickness of only a local area of the sub-grid can be increased by arranging the second grid line 102, so that the consumption of the paste can be saved, and the cost of the solar cell can be reduced.

In this embodiment, the material of the second gate line 102 may be the same as the material of the first gate line 101. In addition, referring to fig. 4 and fig. 5, the second gate line 102 and the first gate line 101 may be an integrally formed structure, and the integrally formed structure not only allows the first gate line 101 and the second gate line 102 to be printed simultaneously in the printing process, but also allows the intersection region of the first gate line 101 and the second gate line 102 not to have an obvious interface, thereby being beneficial to further preventing solder in the solder strip from infiltrating into the intersection region of the first gate line 101 and the second gate line 102 in the process of manufacturing the photovoltaic cell module, and further improving the performance of the photovoltaic cell module.

It should be noted that, in other embodiments, referring to fig. 6 and fig. 7, the first gate line 101 and the second gate line 102 may not be an integrated structure, that is, the first gate line 101 and the second gate line 102 are formed by step-by-step printing, and the requirement for the printing screen can be reduced by step-by-step printing, and the printing position and the printing thickness can be controlled more accurately compared to the integrated structure.

The second gate lines 102 are arranged at intervals along the second direction on opposite sides of the first gate line 101. In this embodiment, the relative arrangement density of the second gate lines 102 is greater than the relative arrangement density of the first gate lines 101, and specifically, the number of the second gate lines 102 may be 106 to 122.

In some embodiments, the length of the second gate line 102 in the parallel first direction may be 0.3mm to 0.6mm, such as 0.35mm, 0.45mm, or 0.55mm. The length of the second grid line 102 is within this range, so that the amount of paste required for the second grid line 102 is reduced, that is, the cost is reduced, and the path of the solder strip penetrating into the boundary region between the second grid line 102 and the third grid line 104 in the soldering process is relatively long, so that the risk of the solder strip melting the boundary region between the second grid line 102 and the third grid line 104 can be reduced.

If the length of the second gate line 102 is too short, the solder strip is prone to flowing to the boundary region of the second gate line 102 and the third gate line 104 in the welding process, so that the boundary region of the second gate line 102 and the third gate line 104 is prone to being fused; if the length of the second gate line 102 is too long, the amount of the paste required for the second gate line 102 increases, which correspondingly increases the cost of the solar cell. Further, the length of the second gate line 102 may be 0.4mm to 0.5mm.

In some embodiments, in the parallel and second directions, the width of the second gate line 102 may be greater than the width of the third gate line 104, so that even if a printing alignment error occurs between the second gate line 102 and the third gate line 104, it can still be ensured that the third gate line 104 is located on the top surface of the second gate line 102, and the boundary region between the sub-gate and the first gate line 101 is a stack of the second gate line 102 and the third gate line 104, and the boundary region between the sub-gate and the first gate line 101 is not a single-layer structure of the third gate line 104, thereby further improving the problem of preventing the boundary region between the sub-gate and the first gate line 101 from being fused.

In other embodiments, the width of the second gate line 102 in parallel with the second direction may be equal to the width of the third gate line 104, i.e., the third gate line 104 completely covers the second gate line 102 in parallel with the second direction when viewed from the top. In this way, the light receiving area outside the third gate line 104 can be prevented from being blocked by the second gate line 102, so that the solar cell still has a larger light receiving area, which is beneficial to further improving the photoelectric conversion efficiency of the solar cell. In one embodiment, the width of the second gate line 102 in the direction parallel to the second direction may be 0.02mm to 0.2mm, such as 0.027mm, 0.035mm, or 0.045mm.

In some embodiments, the thickness of the second gate line 102 is 0.4 to 1 of the thickness of the third gate line 104 in a direction perpendicular to the surface of the semiconductor substrate 100, for example, the thickness of the second gate line 102 is 0.5, 0.7, or 0.8 of the thickness of the third gate line 104. The thickness of the second grid line 102 is within this range, and the thickness of the second grid line 102 is moderate, so that the amount of the paste required by the second grid line 102 is relatively small, which is beneficial to saving the cost; in addition, the thickness of the boundary region between the first gate line 101 and the sub-gate is relatively thick, which is beneficial to ensuring the excellent capability of preventing the boundary region between the first gate line 101 and the sub-gate from being fused.

Specifically, the thickness of the second gate line 102 may be 0.5 of the thickness of the third gate line 104 in a direction perpendicular to the surface of the semiconductor substrate 100.

In some embodiments, the thickness of the second gate line 102 is 0.004mm to 0.016mm, such as 0.008mm, 0.01mm, or 0.015mm, in a direction perpendicular to the surface of the semiconductor substrate 100.

In addition, in some embodiments, the orthographic projection of the second gate line 102 on the surface of the semiconductor substrate 100 may be rectangular, that is, in parallel with the second direction, the width of the second gate line 102 towards one end of the first gate line 101 is the same as the width of the second gate line 102 away from one end of the first gate line 101. The benefits of such an arrangement include: the film layer of the boundary region of the second grid line 102 and the third grid line 104 is of a laminated structure (composed of the second grid line 102 and the third grid line 104) while the area of the light receiving region is not reduced, the film layer of the boundary region of the second grid line 102 and the third grid line 104 is prevented from having a single-layer film layer composed of the third grid line 104, the boundary region of the second grid line 102 and the third grid line 104 is guaranteed to have a thicker thickness, the probability that solder in a welding process penetrates into the second grid line 102 and the third grid line 104 is reduced, and the probability that the solder in the welding process fuses the boundary region of the second grid line 102 and the third grid line 104 is further reduced.

The third gate line 104 is a part of a sub-gate, and forms a sub-gate together with the second gate line 102, for collecting photo-generated current generated on the whole solar cell and transmitting the photo-generated current to the first gate line 101.

Each third gate line 104 crosses multiple first gate lines 101, and covers the side surfaces of the first gate lines 101 and the second gate lines 102 away from the first gate lines 101, and each third gate line 104 is electrically connected to at least 2 first gate lines 101. In this embodiment, the material of the third gate line 104 can be the same as the material of the second gate line 102. In other embodiments, the material of the third gate line 104 can also be different from the material of the second gate line 102.

In a specific embodiment, the width of the third gate line 104 in the direction parallel to the second direction may be 0.02mm to 0.2mm, such as 0.027mm, 0.035mm, or 0.045mm.

Further, in some embodiments, an orthographic projection of the second gate line 102 on the surface of the semiconductor substrate 100 is a first projection, an orthographic projection of a portion, located directly above the second gate line 102, of the third gate line 104 on the surface of the semiconductor substrate 100 is a second projection, and the first projection may coincide with the second projection, so that the thickness of the boundary area between the first gate line 101 and the sub-gate is increased, and the light receiving area of the solar cell may not be changed; in other embodiments, the second projection is located within the first projection, and even if the third gate line 104 is slightly shifted during the printing process (i.e., the third gate line 104 is still completely located within the second gate line 102 at the intersection of the second gate line 102 and the third gate line 104), the second gate line 102 can still increase the thickness of the intersection of the main gate and the sub-gate.

It can be understood that the amount of the paste affects the manufacturing cost and the photoelectric conversion efficiency of the solar cell, and in order to improve the problem of grid breaking and reduce the amount of the paste, before the third grid line 104 is printed, the second grid line 102 is arranged in the area where the third grid line 104 is located, which is close to the first grid line 101, and then the third grid line 103 is printed on the surface of the second grid line 102 and the rest areas, so that the second grid line 102 and the third grid line 104 jointly form a new secondary grid, the length of the interface of the junction area of the main grid and the new secondary grid is increased, accordingly, the penetration path of the solder strip molten tin is increased, which will reduce the probability of grid breaking in the junction area; thus, compared to the manner in which the thickness of the entire third gate line 104 is increased, the scheme of only increasing the thickness of the second gate line 102 while the thickness of the sub-gate in other areas is not changed can reduce the amount of the required paste.

In order to further save the amount of the paste, the length of the second grid line 102 is generally set to be shorter, and the length refers to the length of the extending direction of the third grid line 104; after the second gate line 102 is disposed, a new boundary region is also formed between the second gate line 102 and the third gate line 104, and the new boundary region is located at a position where the second gate line 102 is far away from the first gate line 101; in the new interface region, the solder ribbon molten tin still flows to the new interface region during the soldering process, so that the solder ribbon molten tin permeates from the new interface region, and therefore, the risk of grid breaking also exists between the second grid line 102 and the third grid line 104; in addition, the shorter the length of the second gate line 102, the higher the probability of the gate break occurring in the new interface region. Therefore, in order to improve the problem of grid breakage of the photovoltaic module while saving cost, in this embodiment, the solder resist layer 103 is further disposed on the surface of the second grid line 102, and the solder resist layer 103 covers at least the extension portion 11 of the second grid line 102. The solder resist layer 103 prevents solder ribbon molten tin from penetrating downwards from the boundary area of the second grid line 102 and the third grid line 104, so that the probability of grid breakage of the boundary area of the second grid line 102 and the third grid line 104 is reduced.

Furthermore, when the solar cells are connected in series to form the photovoltaic cell module, in the process of welding the solder strip and the solar cells, the solder strip is pressed, so that the solder strip is squeezed to melt tin and collect the tin in the direction far away from the first grid line 101, and in the production process, the collected area is found to be the direction far away from the first grid line 101 and close to the first grid line 101 on the surface of the second grid line 102, and the length of the collected area is 0.8 of the length of the second grid line.

In addition, since the solder resist layer 103 is disposed on the surface of the second gate line 102, correspondingly, the length of the second gate line 102 can be set shorter along the extending direction of the third gate line 104, which is beneficial to further saving the paste required by the second gate line 102 and further reducing the cost. This is because, even if the length of the second gate line 102 is short and the path of the solder ribbon molten tin penetrating into the boundary region between the second gate line 102 and the third gate line 104 is short, the solder resist layer 103 prevents the solder ribbon molten tin from penetrating, and the solder ribbon molten tin can be prevented from melting the boundary region between the second gate line 102 and the third gate line 104.

The second gate line 102 is divided into an adjacent portion 10 and an extending portion 11, the extending portion 11 is located on a side of the adjacent portion 10 away from the first gate line 101, and the solder resist layer 103 needs to be located on at least a top surface of the extending portion 11. It should be noted that, although the second gate line 102 is divided into the adjacent portion 10 and the extending portion 11, in fact, the adjacent portion 10 and the extending portion 11 are formed integrally.

Specifically, in the direction parallel to the first direction, the length of the extending portion 11 is at least 0.8 of the length of the second gate line 102, which shows the relationship between the probability of the gate breaking occurring in the interface region between the second gate line 102 and the third gate line 104 and the length of the extending portion 11.

Length of solder mask	Rate of gate break
		The length of the solder mask layer is 100 percent of the length of the first auxiliary grid	0％
The length of the solder mask layer is 90 percent of the length of the first auxiliary grid	0％
		The length of the solder mask layer is 82 percent of the length of the first auxiliary grid	0％
The length of the solder mask layer is 80 percent of the length of the first auxiliary grid	0％
		The length of the solder mask layer is 78 percent of the length of the first auxiliary grid	0.01％
The length of the solder mask layer is 76 percent of the length of the first auxiliary grid	0.04％
		The length of the solder mask layer is 74 percent of the length of the first auxiliary grid	0.09％
The length of the solder mask layer is 72 percent of the length of the first auxiliary grid	0.15％
		The length of the solder mask layer is 70 percent of the length of the first auxiliary grid	0.2％
The length of the solder mask layer is 60 percent of the length of the first auxiliary grid	0.5％
		Without solder resist	1.5％

As can be seen from the table one, when the length of the extension portion 11 is greater than or equal to 0.8 of the length of the second gate line 102, the probability of gate break in the boundary region between the second gate line 102 and the third gate line 104 is significantly reduced.

In some embodiments, the solder resist layer 103 covers the entire top surface of the extension portion 11 of the second gate line 102, which can improve the gate-breaking condition in the interface region between the second gate line 102 and the third gate line 104. In other embodiments, the solder resist layer 103 covers the entire top surface of the extension 11 and a portion of the surface of the portion of the adjacent portion 10. In addition, the solder mask layer 103 may also be located on the entire top surface of the second gate line 101, that is, on the entire surface of the adjacent portion 10, which is beneficial to further improve the ability of the solder mask layer 103 to block solder melting flowing to the junction area of the second gate line 102 and the third gate line 104, so as to further reduce the risk of gate break in the junction area of the second gate line 102 and the third gate line 104.

In some embodiments, the solder resist layer 103 has a thickness of 5nm to 10nm, for example, 7nm, 7.5nm, or 8nm, in a direction perpendicular to the surface of the semiconductor substrate 100, and the solder resist layer 130 has a single-layer structure. The thickness of the solder resist layer 103 is within this range, so that the material consumption of the solder resist layer 103 is reduced, and the penetration of solder melting tin of a solder strip to the boundary area of the second gate line 102 and the third gate line 104 is prevented, thereby preventing the gate break between the second gate line 102 and the third gate line 104.

If the thickness of the solder mask layer 103 is too thin, when solder ribbon molten tin flows to the boundary area of the second gate line 102 and the third gate line 104, the solder mask layer 103 cannot completely prevent the gate breaking in the boundary area of the second gate line 102 and the third gate line 104; if the thickness of the solder resist layer 103 is too thick, the material used for the solder resist layer 103 increases, which increases the cost of the solar cell.

The solder mask layer 103 comprises epoxy resin or polyester resin and the like, and the epoxy resin and polyester resin have the characteristics of high temperature resistance, good insulation, printing and the like, so that the junction area of the second grid line 102 and the third grid line 104 can be protected, and meanwhile, the production process is facilitated.

In the embodiment, by adding the second grid line 102, the second grid line 102 and the third grid line 104 together form the secondary grid, so that the thickness of the junction area of the first grid line 101 and the secondary grid is increased, and the probability that the molten tin of the solder strip permeates into the junction area of the first grid line 101 and the third grid line 104 to separate the first grid line 101 and the third grid line 104 is reduced; in addition, the slurry added by arranging the second grid lines 102 is less than the thickness added by arranging the third grid lines 104, so that the cost of the solar cell is reduced. Meanwhile, the solder mask layer 103 is arranged, and the solder mask layer 103 can prevent solder melting of the solder strip from penetrating into the boundary area of the second grid line 102 and the third grid line 104, so that the probability of grid breakage of the second grid line 102 and the third grid line 104 is reduced.

Correspondingly, the embodiment of the invention also provides a photovoltaic cell module, which comprises at least 2 solar cells provided by the embodiment. The photovoltaic cell module provided by the embodiment of the invention is explained in the following with reference to the accompanying drawings.

Fig. 8 and 9 are schematic cross-sectional structural views of a photovoltaic cell assembly according to an embodiment of the invention, and fig. 8 illustrates that a first grid line and a second grid line of a solar cell are formed independently; fig. 9 illustrates that the first grid line and the second grid line of the solar cell are formed at one time.

Referring to fig. 8 and 9, in the present embodiment, the photovoltaic cell module includes: the solar cell string is formed by electrically connecting at least 2 solar cells in the embodiment.

Specifically, the solar cell string further includes solder strips 20, and adjacent solar cells are electrically connected through the solder strips 20.

In some embodiments, the width of the solder ribbon 20 in the direction parallel to the second direction is greater than the width of the first grid line 201, so that the current collection efficiency of the photovoltaic cell module can be improved, and when the solder ribbon 20 is slightly shifted during the soldering process, the surface of the first grid line 201 is still not exposed; in other embodiments, in the direction parallel to the second direction, the width of the solder strip is equal to the width of the first grid line, so that the area of the power generation region of the solar cell is not reduced, the photoelectric conversion efficiency of the solar cell is ensured, and the impedance of the solder strip can be reduced, so that the transmission effect of the photo-generated carriers is better.

The solder ribbon 20 may include a solder ribbon body 206 and a solder ribbon wicking 205 surrounding the solder ribbon body 206. The photovoltaic cell assembly provided by the embodiment can improve the grid breaking phenomenon in the welding process of forming the photovoltaic cell, and the second grid line 202 and the solder resist layer 203 are additionally arranged, so that the second grid line 202 and the third grid line 204 jointly form the auxiliary grid, the thickness of the junction area of the main grid and the auxiliary grid is increased, and the grid breaking rate of the photovoltaic cell assembly can be reduced from 20% to 0% while the cost is saved; the solder mask layer 203 is arranged to prevent solder fillet tin 205 from penetrating into the boundary region between the second gate line 202 and the third gate line 204, so as to reduce the probability of gate breaking of the second gate line 202 and the third gate line 204. Therefore, the photovoltaic cell module provided by the embodiment of the invention has the advantages of low cost, high photoelectric conversion efficiency and long service life.

Further, an embodiment of the present invention further provides a method for forming a photovoltaic cell module, with reference to fig. 8 and 9, including: providing a plurality of solar cells of the foregoing embodiments; and electrically connecting the plurality of solar cells through the solder strips to form a solar cell string, namely a photovoltaic cell module.

Specifically, the solder strip 20 is used to electrically connect the adjacent solar cells, and the solder strip 20 may include a solder strip body and a solder strip molten tin 205 surrounding the solder strip body 206. In the welding process, the solder strip tin melting 205 permeates into the first grid line 201 from the surface of the third grid line 204 along the boundary area, the length of the solder strip tin melting 205 needing to permeate is increased due to the addition of the second grid line 202, and the grid breaking condition between the main grid and the auxiliary grid is improved by increasing the permeation length of the solder strip tin melting 205. However, a new boundary region is formed by adding the second gate line 202 and the third gate line 204, and the gate breaking phenomenon is also easily generated in the boundary region, so that the solder resist layer 203 is additionally printed on the top surface of the second gate line 202, and the solder resist layer 203 can prevent solder ribbon melting tin 205 from flowing into the boundary region between the second gate line 202 and the third gate line 204.

Because the solder mask layer 203 is made of epoxy resin or polyester resin, the material has good adhesiveness, and the quality of contact and adhesion between the solder strip 20 and the solar cell can be improved.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of practicing the invention, and that various changes in form and detail may be made therein without departing from the spirit and scope of the invention in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (12)

1. A solar cell, comprising:

a semiconductor substrate;

the first grid lines are arranged on the surface of the semiconductor substrate along a first direction;

the second grid lines are arranged on the surface of the semiconductor substrate along a second direction, are perpendicular to and intersect with the first grid lines, and have a thickness smaller than that of the first grid lines in the direction perpendicular to the surface of the semiconductor substrate; the second gate line includes: a neighboring portion connected with the first gate line; the extending part is connected with the adjacent part, the adjacent part is positioned between the first grid line and the extending part, and the length of the extending part is at least 0.8 of the length of the second grid line in the direction parallel to the first direction;

the solder mask layer is positioned on the surface of the second grid line and at least covers the top surface of the extension part;

and the third grid lines are arranged on the surface of the semiconductor substrate along the second direction and are vertical to the first grid lines, wherein the third grid lines cover the first grid lines, the solder mask layer and the second grid lines, and the third grid lines are electrically connected with at least 2 first grid lines.

2. The solar cell sheet of claim 1, wherein the solder resist layer covers an entire top surface of the second gate line.

3. The solar cell sheet according to claim 1, wherein the solder resist layer has a thickness of 5nm to 10nm in a direction perpendicular to the surface of the semiconductor substrate.

4. The solar cell sheet according to claim 1, wherein a material of the solder resist layer comprises an epoxy resin or a polyester resin.

5. The solar cell sheet according to any one of claims 1 to 4, wherein the width of the second grid line is greater than or equal to the width of the third grid line in a direction parallel to the second direction.

6. The solar cell sheet according to any one of claims 1 to 4, wherein the thickness of the second grid lines is 0.4 to 1 of the thickness of the third grid lines in a direction perpendicular to the surface of the semiconductor substrate.

7. The solar cell sheet according to any one of claims 1 to 4, wherein the thickness of the second grid line in a direction perpendicular to the surface of the semiconductor substrate is 0.004mm to 0.016mm.

8. The solar cell sheet according to any one of claims 1 to 4, wherein the width of the second grid line in a direction parallel to the second direction is 0.02mm to 0.2mm.

9. The solar cell sheet according to any one of claims 1 to 4, wherein the length of the second grid line in parallel to the first direction is 0.3mm to 0.6mm.

10. The solar cell sheet according to any one of claims 1 to 4, wherein the first grid lines and the second grid lines are of an integrally molded structure.

11. The solar cell of any one of claims 1-4, wherein the first grid line comprises: the surface of the transition part is connected with the second grid line; wherein the thickness of the transition part on the surface perpendicular to the semiconductor substrate is gradually reduced in a direction pointing to the second gate line along the flat part.

12. A photovoltaic cell assembly, comprising: solar cell string, wherein the solar cell string is formed by electrically connecting solar cell sheets according to any one of claims 1 to 11.

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