CN115602718A - Multi-channel HEMT device, preparation method thereof and electronic equipment - Google Patents

Multi-channel HEMT device, preparation method thereof and electronic equipment Download PDF

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CN115602718A
CN115602718A CN202211496052.3A CN202211496052A CN115602718A CN 115602718 A CN115602718 A CN 115602718A CN 202211496052 A CN202211496052 A CN 202211496052A CN 115602718 A CN115602718 A CN 115602718A
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layer
gate electrode
channel
channel layer
electron gas
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CN115602718B (en
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刘杉
陈雪磊
刘庆波
黎子兰
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Xuzhou Zhineng Semiconductor Co ltd
Guangdong Zhineng Technology Co Ltd
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Xuzhou Zhineng Semiconductor Co ltd
Guangdong Zhineng Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

The application relates to the technical field of semiconductors, and provides a multi-channel HEMT device, a preparation method thereof and electronic equipment, wherein the multi-channel HEMT device comprises: the semiconductor device comprises a substrate, and a nucleating layer, a buffer layer, a base material layer, a composite channel layer and at least two gate electrode layers which are arranged on the substrate in a laminated manner; the buffer layer, the substrate layer and the composite channel layer are sequentially arranged on the substrate in a laminated manner; the composite channel layer comprises at least two-dimensional electron gas channel layers; each two-dimensional electron gas channel layer is electrically connected with at least one gate electrode layer. This application is through setting up two-layer gate electrode layer from top to bottom for gate potential control is more balanced, and gate control response is fast, and the break-make of the interior 2DEG of the compound channel layer of the quick control of being convenient for is favorable to forming the multichannel through setting up multilayer two-dimentional electron gas channel layer simultaneously and is electrically conductive, makes whole device can realize more heavy current and higher breakdown voltage, and then promotes the working property of whole device.

Description

Multi-channel HEMT device, preparation method thereof and electronic equipment
Technical Field
The application relates to the technical field of semiconductors, in particular to a multi-channel HEMT device, a manufacturing method thereof and electronic equipment.
Background
The high mobility transistor (HEMT) has the advantages of strong breakdown field, high electron mobility, high thermal conductivity and the like, so that the HEMT is expected to replace the traditional silicon-based device in the field of power electronics. Due to the non-centrosymmetric characteristic of the III-group nitride material, the near interface of the AlGaN and GaN heterojunction has very strong piezoelectric polarization and spontaneous polarization effects, so that interface charges and electric fields are induced, and an electron potential well is formed at the interface. These accumulated high concentration electrons move at high speed in a direction parallel to the heterojunction interface to form a two-dimensional electron gas (2 DEG).
The current HEMT device has only one functional layer with a heterojunction interface, so that two-dimensional electron gas (2 DEG) generated by a single channel layer and a single barrier layer interface mostly performs electron transmission, so that the HEMT device suffers from many limitations, such as low 2DEG concentration and small on-current. Therefore, in order to realize a HEMT with a high on-current, the ohmic contact resistance needs to be optimized so as to reduce or enlarge the area of the active region as much as possible. However, the chip cost is high and its area needs to be fully utilized as much as possible.
Disclosure of Invention
The application aims to provide a multi-channel HEMT device, a preparation method thereof and electronic equipment, and the current and breakdown voltage of the device are further improved on the premise of saving the chip area.
In a first aspect, an embodiment of the application provides a multi-channel HEMT device, including: the device comprises a substrate, a buffer layer, a base material layer, a composite channel layer and at least two gate electrode layers; the buffer layer, the substrate layer and the composite channel layer are sequentially arranged on the substrate in a laminated manner;
the composite channel layer comprises at least two-dimensional electron gas channel layers;
each two-dimensional electron gas channel layer is electrically connected with at least one gate electrode layer.
In some embodiments, the number of gate electrode layers and the number of two-dimensional electron gas channel layers satisfy the following relationship:
N-1≤M≤N；
wherein N is the number of the two-dimensional electron gas channel layers, and N is an integer and is more than or equal to 2. M is the number of gate electrode layers.
In some embodiments, each of the two-dimensional electron gas channel layers comprises a non-doped channel layer, a barrier layer, disposed in a stack; the non-doped channel layer is arranged close to one side of the substrate layer; the barrier layer is arranged on one side far away from the base material layer.
In some embodiments, each of the two-dimensional electron gas channel layers further comprises an insertion layer, the insertion layer is located between the undoped channel layer and the barrier layer.
In some embodiments, the undoped channel layer is an undoped GaN channel layer; and/or
The barrier layer is Al x Ga 1x An N barrier layer; wherein x = 0.1-0.5; and/or
The insertion layer is an AlN layer.
In some embodiments, the undoped channel layer has a thickness of 10nm to 3000nm; and/or
The thickness of the barrier layer is 10 nm-5000 nm; and/or
The thickness of the insertion layer is 0.5 nm-5 nm.
In some embodiments, the substrate layer comprises a P-type GaN layer and a GaN planarization layer surrounding the P-type GaN layer; and/or
The buffer layer is an AlGaN buffer layer; and/or
The substrate is Si, siC, sapphire, gallium nitride or other substrates capable of realizing GaN epitaxial layer growth.
In some embodiments, the thickness of the P-type GaN layer is 5 to 500nm; the thickness of the GaN flattening layer is 10 nm-800 nm; and/or
The thickness of the buffer layer is 500nm to 8000nm.
In some embodiments, the P-type GaN layer is selected from an element-doped P-type gallium nitride layer or a P-type aluminum gallium nitride layer; the doping concentration of the element is 10 17 ~10 18 cm -3 The injection depth is 50 to 200nm.
In some embodiments, the multi-channel HEMT device further comprises: a passivation layer; the passivation layer is located on one side of the barrier layer away from the substrate.
In some embodiments, the at least two gate electrode layers include a first gate electrode layer and a second gate electrode layer;
the first gate electrode layer comprises a plurality of first gate electrode structures arrayed on the substrate layer;
the second gate electrode layer comprises a plurality of second gate electrode structures arrayed on the composite channel layer;
the passivation layer surrounds the periphery of the second gate electrode structure; the undoped channel layer close to one side of the substrate layer surrounds the periphery of the first gate electrode structure.
In some embodiments, a side of the passivation layer away from the substrate is further provided with a source electrode and a drain electrode;
the plurality of second gate electrode structures are arranged in parallel and in an interconnected mode, and the source electrode and the drain electrode are respectively positioned on two sides of one of the second gate electrode structures;
the source electrode and the drain electrode are respectively in electrical contact with the two-dimensional electron gas channel layer.
In some embodiments, orthographic projections of a plurality of the first gate electrode structures and a plurality of the second gate electrode structures on the substrate are arranged in an overlapping manner or in a staggered manner.
In a second aspect, the application also provides an electronic device comprising a multi-channel HEMT device according to the first aspect.
In a third aspect, the present application further provides a method for manufacturing a multi-channel HEMT device, for manufacturing the multi-channel HEMT device according to the first aspect, including:
providing a semi-finished product device, wherein the semi-finished product device comprises a buffer layer, a base material layer and a first gate electrode layer, which are sequentially formed on a substrate;
forming a composite channel layer and a second gate electrode layer on the semi-finished device in sequence;
wherein the composite channel layer comprises at least two-dimensional electron gas channel layers.
In some embodiments, the first gate electrode layer includes a number of first gate electrode structures arrayed on the substrate layer;
the forming of the first gate electrode layer includes:
forming a first gate electrode film layer on the substrate layer;
and carrying out a patterning process on the first gate electrode film layer according to the reserved position of the first gate electrode to obtain the patterned first gate electrode structure.
In some embodiments, each of the two-dimensional electron gas channel layers comprises a non-doped channel layer, a barrier layer, disposed in a stack;
the forming of the composite channel layer includes:
epitaxially growing a channel layer on the first gate electrode structure for the second time, wherein the channel layer covers the first gate electrode structure;
grinding the non-doped channel layer until the structure of the non-doped channel layer is consistent with that of the first gate electrode, and obtaining a first non-doped channel layer;
forming a barrier layer on the first undoped channel layer to obtain a first two-dimensional electron gas channel layer;
epitaxially growing a layer of the non-doped channel layer on the first two-dimensional electron gas channel layer, and forming a layer of the barrier layer on the non-doped channel layer to obtain a second two-dimensional electron gas channel layer;
and repeating or not repeating the preparation steps of the two-dimensional electron gas channel layer according to the number of the two-dimensional electron gas channel layers included in the composite channel layer to obtain the composite channel layer.
In some embodiments, the process of preparing the second gate electrode layer includes:
preparing a second gate electrode film layer on the composite channel layer;
and carrying out a patterning process on the second gate electrode film layer according to the reserved position of the second gate electrode to obtain the patterned second gate electrode structure.
In some embodiments, after the second gate electrode layer is prepared, the method further includes: forming a passivation layer;
the forming of the passivation layer includes:
forming a first connecting groove, a second connecting groove and a third connecting groove on the composite channel layer by using dry etching and/or wet etching; wherein the first connection trench extends until the first gate electrode structure appears; the second connecting groove and the third connecting groove extend to the two-dimensional electron gas channel layer close to the substrate layer to be displayed;
forming an ohmic contact metal layer in the second connecting groove and the third connecting groove by using a Lift off film tearing process to form a source electrode and a drain electrode;
depositing to form the passivation film layer;
removing the top surface of the second gate electrode structure and part of the passivation film layer on the bottom surface of the first connecting groove; enabling the second gate electrode structure and the first gate electrode structure to emerge;
depositing gate metal on the second gate electrode structure and the first gate electrode structure to form a second gate and a first gate;
and carrying out metal interconnection technology on the second grid, the first grid, the source electrode and the drain electrode to obtain the device.
In some embodiments, after the second gate electrode layer is prepared, the method further includes: forming a passivation layer;
the forming of the passivation layer includes:
forming a second connecting groove and a third connecting groove on the composite channel layer by using dry etching and/or wet etching; the second connecting groove and the third connecting groove extend to the two-dimensional electron gas channel layer close to the substrate layer to be displayed;
forming an ohmic contact metal layer in the second connecting groove and the third connecting groove by using a Lift off film tearing process to form a source electrode and a drain electrode;
forming a first connecting groove on the composite channel layer by using dry etching and/or wet etching; the first connecting groove extends to the appearance of the first gate electrode structure;
depositing to form the passivation film layer;
removing the top surface of the second gate electrode structure and part of the passivation film layer on the bottom surface of the first connecting groove; visualizing the second gate electrode structure and the first gate electrode structure;
depositing gate metal on the second gate electrode structure and the first gate electrode structure to form a second gate and a first gate;
and carrying out metal interconnection technology on the second grid electrode, the first grid electrode, the source electrode and the drain electrode to obtain the device.
In some embodiments, the passivation layer is made of SiN or SiO 2 、Al 2 O 3 Any one or more of.
The embodiment of the application has at least the following technical effects:
according to the multi-channel HEMT device provided by the embodiment of the application, the multi-channel conduction is facilitated by arranging the multi-layer two-dimensional electron gas channel layer, so that the whole device can realize larger current and higher breakdown voltage, and the working performance of the whole device is further improved; meanwhile, by arranging at least two layers of gate electrode layers, the control of the gate potential is more balanced, the response of the gate control is fast, and the on-off of the 2DEG in the composite channel layer is convenient to control rapidly.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of an internal structure of a multi-channel HEMT device according to an embodiment of the present application;
fig. 2 is a schematic diagram of layout design of a two-layer gate electrode structure of a multi-channel HEMT device according to the embodiment of the present application;
fig. 3 is a schematic diagram of an internal structure of another multi-channel HEMT device according to an embodiment of the present application;
fig. 4 is a schematic layout design diagram of a two-layer gate electrode structure of another multi-channel HEMT device provided in the embodiment of the present application;
fig. 5 is a schematic flowchart of a method for manufacturing a multi-channel HEMT device according to an embodiment of the present application;
fig. 6 is a schematic specific flowchart in step S100 of a method for manufacturing a multi-channel HEMT device according to an embodiment of the present application;
fig. 7a is a schematic process structure diagram corresponding to step S110 of a method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 7b is a schematic process structure diagram corresponding to step S120 of a method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 7c is a schematic view of a process structure corresponding to step S210 of a method for manufacturing a multi-channel HEMT device according to an embodiment of the present application;
fig. 7d is a schematic process structure diagram corresponding to step S220 of a method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 7e is a schematic view of a process structure corresponding to step S250 of a method for manufacturing a multi-channel HEMT device according to an embodiment of the present application;
fig. 7f is a schematic process structure diagram corresponding to step S260 of the method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 7g is a schematic process structure diagram corresponding to step S300 of the method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 7h is a schematic process structure diagram corresponding to step S400 of a method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 7i is a schematic process structure diagram corresponding to step S500 of a method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 7j is a schematic process structure diagram corresponding to step S700 of a method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 8 is a schematic specific flowchart in step S200 of a method for manufacturing a multi-channel HEMT device according to an embodiment of the present application;
fig. 9 is a schematic flow chart of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 10a is a schematic view of a process structure corresponding to step S110 of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 10b is a schematic view of a process structure corresponding to step S120 of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 10c is a schematic process structure diagram corresponding to step S210 of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 10d is a schematic view of a process structure corresponding to step S220 of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 10e is a schematic process structure diagram corresponding to step S250 of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 10f is a schematic process structure diagram corresponding to step S260 of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 10g is a schematic process structure diagram corresponding to step S300 of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 10h is a schematic process structure diagram corresponding to step S400 of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 10i is a schematic process structure diagram corresponding to step S500 of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 10j is a schematic process structure diagram corresponding to step S700 of another method for manufacturing a multi-channel HEMT device according to the embodiment of the present application;
fig. 11 is a schematic diagram of an internal structure of another multi-channel HEMT device according to the embodiment of the present application.
In the figure:
100-a substrate;
300-a buffer layer;
400-a substrate layer;
500 a-a composite channel layer;
500-a first gate electrode film layer; 510-a first gate electrode structure; 510 a-a first sub-electrode;
610-a first undoped channel layer; 620 — a first barrier layer;
710-a second undoped channel layer; 720-a second barrier layer;
900-a second gate electrode film layer; 910 — a second gate electrode structure; 910 a-a second sub-electrode;
1000-a passivation layer; 1010-front passivation layer;
1100-first connecting slot; 1110-a first gate;
1200-a second connection slot; 1210-a source electrode;
1300-a third connecting groove; 1310-drain electrode;
1400-second gate.
Detailed Description
The technical solutions of the present application will be described clearly and completely with reference to the following embodiments, and it should be apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
With reference to fig. 1, an embodiment of the present application provides a multi-channel HEMT device, including: a substrate 100, a buffer layer 300 (e.g., a stacked structure of AlN and GaN), a base material layer 400 (i.e., a GaN layer illustrated in fig. 1), and a composite channel layer 500a, which are stacked on the substrate 100. The composite channel layer 500a serves as a channel between the source electrode 1210 and the drain electrode 1310, and the structure thereof directly affects the on-current and breakdown voltage of the device. In addition, the material of the substrate layer 400 is preferably GaN in the present application, which is more favorable for growing a P-type GaN film layer thereon, and improves the growth quality of the film layer. Wherein the thickness of the substrate layer can be 5 to 500nm; the thickness of the buffer layer can be 5008000 nm.
Specifically, the composite channel layer 500a includes at least two-dimensional electron gas channel layers, each of which includes a non-doped channel layer and a barrier layer (e.g., alGaN), and at least two gate electrode layers that control the on and off of a two-dimensional electron gas (2 DEG) in the channel. The specific number of layers of the two-dimensional electron gas channel layer and the number of layers of the gate electrode layer may be set according to actual requirements of the device, and fig. 1 illustrates a 2-layer two-dimensional electron gas channel layer as an example.
Illustratively, in fig. 1, the composite channel layer 500a includes a first two-dimensional electron gas channel layer including a first undoped channel layer 610 and a first barrier layer 620, and a second two-dimensional electron gas channel layer including a second undoped channel layer 710 and a second barrier layer 720; the HEMT device comprises gate electrode layers which are respectively as follows: a first gate electrode layer and a second gate electrode layer; the first gate electrode layer includes a patterned first gate electrode structure 510; the first undoped channel layer 610 surrounds the first gate electrode structure 510; the second gate electrode layer comprises a patterned second gate electrode structure 910, and the second gate electrode structure 910 is distributed on the surface of the second electron gas channel layer; the first gate electrode structure 510 is electrically connected to the first gate 1110, and the second gate electrode structure 910 is electrically connected to the second gate 1400.
The first gate electrode structure 510 and the second gate electrode structure 910 are specifically configured according to the position and arrangement of the gate, and both can be prepared by combining an electrode film formation process and a patterning process.
Note that the first gate electrode structure 510 and the second gate electrode structure 910 may be overlapped or arranged in a staggered manner, and the width dimension may be set to different specifications. Fig. 1 illustrates a first gate electrode structure 510 and a second gate electrode structure 910, which are arranged in an overlapping manner, and fig. 3 illustrates a structure of a multi-channel HEMT device according to another embodiment, in which the first gate electrode structure 510 and the second gate electrode structure 910 are arranged in a staggered manner. In some embodiments, the vertical projections of the first gate electrode structure 510 and the second gate electrode structure 910 on the substrate layer 400 are overlapped, and in the device structure, the first connection groove for forming the first gate only needs to be opened until one first gate electrode structure 510 appears, so that the process difficulty is low, the risk is low, and the chip film surface is flat. The first gate electrode layer and the second gate electrode layer have a strong ability to control the 2DEG in the interlayer at the same position. In other embodiments, the first gate electrode structures 510 and the second gate electrode structures 910 are disposed in a staggered manner in terms of vertical projection on the substrate layer 400, and in the device structure, the first connection groove for forming the first gate needs to be opened until each first gate electrode structure 510 appears, so that the process difficulty is slightly higher, but the first gate electrode layer and the second gate electrode layer are more uniformly controlled for the 2DEG in the interlayer at the same position.
According to the multi-channel HEMT device provided by the exemplary embodiment, the upper gate electrode layer and the lower gate electrode layer are arranged, so that the gate potential control is more balanced, the gate control response speed is higher, and the on-off of the 2DEG in the composite channel layer 500a can be controlled rapidly; meanwhile, the multi-layer two-dimensional electron gas channel layer is arranged, so that multi-channel conduction is facilitated to be formed, and the whole device can realize larger current. The multi-gate potential controls the leakage current, so that higher breakdown voltage can be realized, and the working performance of the whole device is further improved.
More two-dimensional electron gas channel layers and gate electrode layers, such as 4-layer two-dimensional electron gas channel layers and 3-layer gate electrode layers, may also be included in the HEMT device, and the following description will be made by taking the structure of the HEMT device including 4-layer two-dimensional electron gas channel layers and 4-layer gate electrode layers as an example:
the composite channel layer comprises a first two-dimensional electron gas channel layer, a second two-dimensional electron gas channel layer and a third two-dimensional electron gas channel layer which are sequentially stacked, the first two-dimensional electron gas channel layer is positioned on one side closest to the substrate layer, and the third two-dimensional electron gas channel layer is positioned on one side farthest from the substrate layer; each two-dimensional electron gas channel layer comprises a non-doped channel layer and a barrier layer; the gate electrode layer that this HEMT device included is respectively: a first gate electrode layer and a second gate electrode layer; the first gate electrode layer includes a patterned first gate electrode structure; the non-doped channel layer of the first two-dimensional electron gas channel layer surrounds the first gate electrode structure; the second gate electrode layer comprises a patterned second gate electrode structure, and the undoped channel layer of the third two-dimensional electron gas channel layer surrounds the second gate electrode structure; the second gate electrode structure is distributed on the upper layer of the second two-dimensional electron gas channel layer and below the third two-dimensional electron gas channel layer, and controls the on-off of the second two-dimensional electrons and the third two-dimensional electrons simultaneously; the first gate electrode structure is electrically connected with the first gate, and the second gate electrode structure is electrically connected with the second gate.
In some embodiments, the number of layers of the two-dimensional electron gas channel layer and the gate electrode layer in the HEMT device may be designed by satisfying the following conditions; the conditions to be met are as follows:
N-1≤M≤N；
wherein N is the number of the two-dimensional electron gas channel layers, and N is an integer and is more than or equal to 2. M is the number of gate electrode layers.
Each layer 2DEG is controlled by at least one gate electrode layer. When the 2-layer 2DEG is distributed on the upper side and the lower side of the gate electrode, the 2-layer 2DEG shares one gate electrode to realize the opening and closing of the device, so that the film space is saved, the complex stacking of the gate electrode is avoided, and the process difficulty is reduced.
Taking the number of the two-dimensional electron gas channel layers as 3 and the number of the gate electrode layers as 2 as an example, referring to fig. 11, in this embodiment, the composite channel layer 500a includes a first two-dimensional electron gas channel layer, a second two-dimensional electron gas channel layer, and a third two-dimensional electron gas channel layer, which are stacked, each two-dimensional electron gas channel layer includes a non-doped channel layer and a barrier layer, which are sequentially disposed from bottom to top, the first gate electrode structure 510 is located in the first two-dimensional electron gas channel layer, and the second gate electrode structure 910 is located in the third two-dimensional electron gas channel layer; the HEMT device is also provided with a drain electrode (D in the figure) and a source electrode (S in the figure) which are electrically connected with the first two-dimensional electron gas channel layer.
This HEMT device compares than single channel's Hemt, has formed 3 DEG high speed channels under the unchangeable condition of chip size, consequently has higher two-dimensional electron gas concentration and bigger conduction current, and the opening and closing of two-dimensional electron gas are controlled simultaneously to upper and lower gate electrode, and the passage of greatly reduced electric leakage improves the breakdown voltage of device.
In some embodiments, with continued reference to fig. 1, the first gate electrode structure 510 and the second gate electrode structure 910 in this embodiment are both P-GaN electrodes, which are P-doped GaN layers or P-doped AlGaN layers. Depletion of the 2DEG under the gate electrode is facilitated through the P-type GaN, so that normally-off control of the device is achieved.
The P-type GaN layer is selected from an element-doped P-type gallium nitride layer or a P-type aluminum gallium nitride layer; the doping concentration of the element is 10 17 ~10 19 cm -3 . The preparation method can be MOCVD process growth or ion implantation, and is not limited. Wherein the doping element can be an element for realizing P-type doping of the GaN layer, such as Mg and the like。
In some embodiments, with continued reference to fig. 1, the multi-channel HEMT device provided by embodiments of the present application further comprises: the passivation layer 1000 is located on a side of the composite channel layer 500a away from the substrate 100, and surrounds the periphery of the second gate electrode structure 910, and is mainly used for protecting the second gate electrode structure 910 and the composite channel layer 500a.
Optionally, the passivation layer 1000 in this embodiment mainly includes silicon dioxide, silicon nitride, aluminum oxide, or other material combinations.
Still taking a HEMT device employing two-dimensional electron gas channel layers and two gate electrode layers as an example, a first gate 1110 (G1 illustrated in fig. 1) and a second gate 1400 (G2 illustrated in fig. 1) are disposed on a side of the passivation layer 1000 away from the substrate 100; the first gate electrode 1110 is electrically connected to the first gate electrode structure 510 through a first connection groove 1100 penetrating the passivation layer 1000 and the two-dimensional electron gas channel layer. Wherein, the first connection groove 1100 (see fig. 7 h) can be realized by an etching process, and the bottom of the first connection groove 1100 stays at the upper surface of the first gate electrode structure 510 to realize the electrical connection between the first gate 1110 and the first gate electrode structure 510. The second gate 1400 is stacked on the second gate electrode structure 910, and can be directly electrically connected.
Alternatively, the first gate 1110 and the second gate 1400 may be prepared by the same gate metal deposition process. The metal material in the first connection groove 1100 is the same as the metal material of the first gate 1110, and both are prepared through the same process.
In some embodiments, with continued reference to fig. 1, the hemt device is further provided with a source electrode 1210 (S in fig. 1) and a drain electrode 1310 (D in fig. 1).
As can be seen from the figure, the second gate electrode layer includes a plurality of second gate electrode structures 910 which are parallel to each other and are interconnected, wherein each second gate electrode structure 910 is a second sub-electrode 910a, and each second sub-electrode 910a corresponds to an elongated electrode structure extending in a direction perpendicular to the paper. For the same multi-channel HEMT device, the source electrode 1210 and the drain electrode 1310 are respectively located on both sides of one of the second sub-electrodes 910 a.
Specifically, the source electrode 1210 is in electrical contact with the underlying second two-dimensional electron gas channel layer through a second connection groove 1200 (see fig. 7 h) that penetrates the passivation layer 1000 and extends to the two-dimensional electron gas channel layer of the substrate layer; the drain electrode 1310 is in electrical contact with the underlying second two-dimensional electron gas channel layer through a third connection trench 1300 (see fig. 7 h) that penetrates the passivation layer 1000 and extends to the two-dimensional electron gas channel layer of the substrate layer. The metal material in the second connecting groove 1200 is the same as the metal material of the source electrode 1210, and the two are prepared by the same process; the metal material in the third connecting groove 1300 is the same as the metal material of the drain electrode 1310, and both can be prepared by the same process.
Illustratively, the materials of the first gate and the second gate are independently selected from Ti, al, tiN, ni, pt, au, pd, and alloys thereof, and form a schottky contact with PGaN.
Illustratively, the materials of the drain electrode and the source electrode are independently selected from Ti, al, ni, au, mo and alloys thereof.
It should be noted that, under the control of the first gate 1110 and the second gate 1400, the composite channel layer 500a interposed between the second connection groove 1200 and the third connection groove 1300 serves as a two-dimensional electron gas transmission channel to achieve current conduction.
Optionally, the bottoms of the second connection groove 1200 and the third connection groove 1300 both partially extend into the first two-dimensional electron gas channel layer, that is, when the second connection groove 1200 and the third connection groove 1300 are formed by etching, after the passivation layer 1000 and the two-dimensional electron gas channel layer are etched, a partial region of the non-doped channel layer of the two-dimensional electron gas channel layer needs to be continuously etched, so that the source electrode 1210 and the drain electrode 1310 are connected with the non-doped channel layer below to form ohmic contact.
In some embodiments, with continued reference to fig. 1, for the two-dimensional electron gas channel layers, each of the two-dimensional electron gas channel layers includes a heterojunction formed by a GaN/AlGaN stack, so that each of the two-dimensional electron gas channel layers can realize migration of two-dimensional electron gas, thereby increasing on-current.
The method comprises the following steps: the non-doped channel layer is a non-doped GaN channel layer, and the barrier layer is Al x Ga 1x An N barrier layer; wherein x =0.1 to 0.5.
Optionally, the thickness of the non-doped channel layer is 10nm to 3000nm; the thickness of the barrier layer is 10 nm-5000 nm.
In some embodiments, each two-dimensional electron gas channel layer may further include an insertion layer interposed between the undoped channel layer and the barrier layer, by which electron mobility is further enhanced. Illustratively, the insertion layer is an AlN layer, and optionally, the thickness of the insertion layer is 10nm to 100nm.
In an alternative embodiment, as shown in fig. 2, the first gate electrode layer includes a plurality of first gate electrode structures 510 arranged in parallel and interconnected, each of which is a first sub-electrode 510a. The orthographic projections of the first sub-electrode 510a and the second sub-electrode 910a on the substrate 100 are overlapped, which is beneficial to increasing the gate electric field strength, and further increasing the switching speed of gate control.
Specifically, the plurality of first sub-electrodes 510a are interconnected by a transverse connection metal, a length extending direction of the transverse connection metal is perpendicular to a length extending direction of the first sub-electrodes 510a, and the first gate 1110 is in contact with two ends of the transverse connection metal through the first connection groove 1100, so that the first gate 1110 is electrically connected to the first gate electrode structure 510.
In an alternative embodiment, as shown in fig. 4, the first gate electrode layer includes a plurality of first gate electrode structures disposed in parallel and interconnected, each first gate electrode structure is a first sub-electrode 510a, and orthographic projections of the first sub-electrode 510a and the second sub-electrode 910a on the substrate 100 are arranged at intervals in an interlaced manner.
Specifically, the plurality of first sub-electrodes 510a are interconnected through a first transverse connection metal, the plurality of second sub-electrodes 910a are interconnected through a second transverse connection metal, and the free ends of the first transverse connection metal and the second transverse connection metal are arranged in a staggered manner, so that the first gate 1110 and the second gate 1400 are arranged in a staggered manner.
Optionally, the multi-channel HEMT device illustrated in fig. 1 and 3 in the embodiment of the present application further includes an isolation region, a plurality of devices or a plurality of circuits are fabricated on the same heterojunction material, and in order to avoid crosstalk and communication between the devices, the active regions of each device need to be isolated. The isolation region may be implemented by ion implantation and mesa etching, and if the mesa etching is implemented, the isolation region may be synchronized with the connection grooves corresponding to the first gate 1110, the source electrode 1210, and the drain electrode 1310, respectively.
Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which includes the multi-channel HEMT device in the foregoing embodiments. The electronic device may be a high-power device or an electronic product using the high-power device, such as a power adapter, a vehicle-mounted charging device, a data center, and other application fields.
The electronic equipment that this embodiment provided, including the multichannel HEMT device in the aforementioned embodiment, this multichannel HEMT device is through setting up two-layer gate electrode layer from top to bottom for gate potential control is more balanced, and gate control response is fast, is convenient for control the break-make of 2DEG in the compound channel layer 500a fast, simultaneously through setting up multilayer two-dimentional electron gas channel layer, is favorable to forming the multichannel and conducts electricity, makes whole device can realize more heavy current and higher breakdown voltage, and then promotes whole electronic equipment's working property.
Based on the same inventive concept, as shown in fig. 5, an embodiment of the present application further provides a method for manufacturing a multi-channel HEMT device, which is used for manufacturing the multi-channel HEMT device in the foregoing embodiment, and the specific manufacturing method includes the following steps:
s100, providing a substrate 100, and sequentially preparing a buffer layer 300, a base material layer 400, and a first gate electrode layer on the substrate 100; obtaining a semi-finished device;
s200, sequentially forming a multi-layer two-dimensional electron gas channel layer and a second gate electrode layer on the semi-finished device; the second gate electrode layer includes a patterned second gate electrode structure 910, as shown in fig. 7 f.
According to the preparation method of the multi-channel HEMT device, two layers of gate electrode layers are prepared on the substrate layer 400, so that the gate potential control is more balanced, the gate control response is fast, the on-off of the 2DEG in the composite channel layer 500a can be controlled conveniently and rapidly, and meanwhile, the multi-channel conduction is facilitated by preparing the multi-layer two-dimensional electron gas channel layer, so that the whole device can realize higher current and higher breakdown voltage, and the working performance of the whole device is further improved.
In some embodiments, as shown in fig. 6, in step S100, the process of preparing the first gate electrode layer includes:
s110, preparing a first gate electrode film 500 on the substrate layer 400; wherein the first gate electrode film 500 is a P-GaN layer, as shown in fig. 7 a.
S120, a patterning process is performed on the first gate electrode film 500 according to the reserved position of the first gate 1110, so as to obtain a patterned first gate electrode structure 510, as shown in fig. 7 b.
In some embodiments, as shown in fig. 6 to 7, the forming of the composite channel layer in step S200 includes:
s210, a GaN channel layer, i.e., a first undoped channel layer 610, is epitaxially grown on the first gate electrode structure 510 twice, and the GaN channel layer covers the first gate electrode structure 510, as shown in fig. 7 c. The first gate electrode structure 510 is a P-GaN electrode.
S220, planarizing the GaN channel layer to be flush with the first gate electrode structure 510 (to expose the first gate electrode structure 510), thereby obtaining a first non-doped channel layer 610, as shown in fig. 7 d;
s230, forming a first barrier layer 620 on the first undoped channel layer 610 to obtain a first two-dimensional electron gas channel layer;
s240, epitaxially growing a layer of the non-doped channel layer on the first two-dimensional electron gas channel layer, and forming a layer of the barrier layer on the non-doped channel layer to obtain a second two-dimensional electron gas channel layer.
In the actual process of manufacturing the composite channel layer, whether the steps of S110 to S240 are repeated may be determined according to the number of the two-dimensional electron gas channel layers in the composite channel layer. When the composite channel layer includes a 4-layer two-dimensional electron gas channel layer, it further includes, after S160:
s241, forming a layer of gate electrode film layer on the second two-dimensional electron gas channel layer, and performing a patterning process on the gate electrode film layer by using the reserved position of the gate electrode layer to obtain a patterned gate electrode structure M; and S242, growing a GaN channel layer on the gate electrode structure M in a secondary epitaxial manner, grinding the GaN channel layer to be flush with the gate electrode structure M (so that the gate electrode structure M is shown), obtaining a non-doped channel layer of a third two-dimensional electron gas channel layer, and repeating the steps S230 and S240 on the non-doped channel layer of the third two-dimensional electron gas channel layer, so that the four-layer two-dimensional electron gas channel layer can be obtained.
In some embodiments, as shown in fig. 8, in step S200, the process of preparing the second gate electrode layer includes:
s250, preparing a second gate electrode film layer 900 on the composite channel layer; wherein the second gate electrode film layer 900 is a P-GaN layer as shown in fig. 7 e.
S260, performing a patterning process on the second gate electrode film layer 900 according to the reserved position of the second gate 1400, so as to obtain a patterned second gate electrode structure 910, as shown in fig. 7 f. The second gate electrode structure 910 is a P-GaN electrode.
In some embodiments, as shown in fig. 9, after the second gate electrode layer is prepared in step S200, the method includes:
s300, preparing a pre-passivation layer 1010, wherein the pre-passivation layer 1010 covers the barrier layer and the patterned second gate electrode structure 910, and optionally, the pre-passivation layer 1010 may be SiO 2 、SiN、Al 2 O 3 Or other combinations, etc. It should be noted that the step of preparing the pre-passivation layer 1010 in S300 may be omitted in the actual production process, and the photoresist layer in the etching process through the second electrode layer may also play a similar role in protection.
An etching process is used to open a first connection trench 1100, a second connection trench 1200 and a third connection trench 1300 on the composite channel layer, so that the electrical contact areas of the first gate 1110, the source electrode 1210 and the drain electrode 1310 are opened, as shown in fig. 7 g.
Alternatively, the groove bottoms of the first connection groove 1100 need to contact the upper surface of the first gate electrode structure 510, and the groove bottoms of the second connection groove 1200 and the third connection groove 1300 need to partially extend to the two-dimensional electron gas channel layer near the substrate layer, so as to form an ohmic contact.
S400, an ohmic contact metal layer of the source electrode 1210 and the drain electrode 1310 is prepared, as shown in fig. 7 h.
S500, preparing a second passivation layer 1000, covering the inside of the first connection groove 1100 with the second passivation layer 1000, as shown in fig. 7i, and removing the upper surface of the groove bottom of the first connection groove 1100, which needs to contact the first gate electrode structure 510;
preparing a first gate 1110; the metal of the first gate may be Ti/Al/Ni/Au or other metal combinations.
Alternatively, the ohmic contact metal layer may be a combination of Ti/Al/Ni/Au or other metals, and then RTA annealing for an appropriate time is required.
S600, a portion of the passivation layer 1000 on the second gate electrode structure 910 is removed, and the upper surface of the second gate electrode structure 910 is exposed.
Optionally, the passivation layer 1000 for the metal connection region of the second gate electrode structure 910 is removed by an etching process, exposing the upper surface of the upper P-GaN layer.
S700, a gate metal is deposited on the second gate electrode structure 910, thereby forming a second gate 1400, as shown in fig. 7 j.
Alternatively, the deposited gate metal may be a Ti/Al/Ni/Au or other metal combination. It should be noted that in this step, the upper and lower layers of P-GaN electrodes are electrically connected through layout design.
S800, performing a metal interconnection process on the second gate 1400, the first gate 1110, the source electrode 1210, and the drain electrode 1310 to obtain a device structure, which is the device structure shown in fig. 1.
Optionally, the electrical connection of the whole device is realized through a conventional back-end metal interconnection process, so that the preparation of the device main body structure is completed.
It should be noted that the device body structure in this embodiment refers to a semiconductor device after two-layer gate fabrication and metal interconnection processes are completed, that is, the structure illustrated in fig. 1.
In another embodiment, different device body structure preparations can be realized by adjusting the layout design of the first gate electrode structure 510 and the second gate electrode structure 910, and specific process steps refer to S100 to S700 in the foregoing embodiment, and only the structures of part of processes have differences, and the specific process steps are as follows:
s100, providing a substrate 100, and sequentially preparing a buffer layer 300, a base material layer 400, and a first gate electrode layer on the substrate 100.
S200, sequentially preparing a multi-layer two-dimensional electron gas channel layer and a second gate electrode layer on the first gate electrode layer; the second gate electrode layer includes a patterned second gate electrode structure 910, as shown in fig. 10 f.
In some embodiments, in step S100, the process of preparing the first gate electrode layer includes:
s110, preparing a first gate electrode film 500 on the substrate layer 400; the first gate electrode film 500 is a P-GaN layer, as shown in fig. 10a.
S120, a patterning process is performed on the first gate electrode film 500 according to the reserved position of the first gate 1110, so as to obtain a patterned first gate electrode structure 510, as shown in fig. 10 b.
In some embodiments, in step S200, the process of manufacturing the composite channel layer 500a includes:
s210, a GaN channel layer, i.e. a first undoped channel layer 610, is epitaxially grown on the first gate electrode structure 510 twice, and the GaN channel layer covers the first gate electrode structure 510, as shown in fig. 10 c. The first gate electrode structure 510 is a P-GaN electrode.
S220, the GaN channel layer is ground to be flush with the first gate electrode structure 510, so as to obtain a non-doped channel layer of the first two-dimensional electron gas channel layer, as shown in fig. 10 d.
S230, forming a first barrier layer 620 on the first undoped channel layer 610 to obtain a first two-dimensional electron gas channel layer.
S240, epitaxially growing a layer of the non-doped channel layer on the first two-dimensional electron gas channel layer, and forming a barrier layer on the non-doped channel layer to obtain a second two-dimensional electron gas channel layer.
In some embodiments, in step S200, the process of preparing the second gate electrode layer includes:
s250, preparing a second gate electrode film 900 on the composite channel layer 500 a; wherein the second gate electrode film 900 is a P-type GaN layer, as shown in fig. 10 e.
S260, a patterning process is performed on the second gate electrode film 900 according to the reserved position of the second gate 1400, so as to obtain a patterned second gate electrode structure 910 (corresponding to the second gate 1400 layer), as shown in fig. 10 f. The second gate electrode structure 910 is a P-GaN electrode.
In some embodiments, after the second gate electrode layer is completely prepared in step S200, the method includes:
s300, opening electrical contact areas of the first gate 1110, the source electrode 1210 and the drain electrode 1310 by dry etching and/or wet etching to form a first connection groove 1100, a second connection groove 1200 and a third connection groove 1300, respectively, as shown in fig. 10 g.
Alternatively, the groove bottoms of the first connection groove 1100 need to contact the upper surface of the first gate electrode structure 510, and the groove bottoms of the second connection groove 1200 and the third connection groove 1300 need to partially extend into the two-dimensional electron gas channel layer close to the substrate layer, so as to form an ohmic contact.
S400, ohmic contact metal layers of the source electrode 1210 and the drain electrode 1310 are prepared, as shown in fig. 10 h.
Alternatively, the ohmic contact metal layer may be a combination of Ti/Al/Ni/Au or other metals, and then RTA annealing for an appropriate time is required.
S500, preparing a second passivation layer, covering the inner surface of the first connection groove 1100 with the passivation layer, as shown in fig. 10i, and removing the upper surface of the groove bottom of the first connection groove 1100, which needs to contact the first gate electrode structure 510;
preparing a first gate 1110; the metal of the first gate may be Ti/Al/Ni/Au or other metal combinations.
S600, a portion of the passivation layer 1000 on the second gate electrode structure 910 is removed, and the upper surface of the second gate electrode structure 910 is exposed.
Optionally, the passivation layer 1000 for the metal connection region of the second gate electrode structure 910 is removed by an etching process, exposing the upper surface of the upper P-GaN layer.
S700, a gate metal is deposited on the second gate electrode structure 910, thereby forming a second gate 1400, as shown in fig. 10 j.
Alternatively, the deposited gate metal may be a Ti/Al/Ni/Au or other metal combination. It should be noted that in this step, the upper and lower layers of P-GaN electrodes are electrically connected through layout design.
S800, a metal interconnection process is performed on the second gate 1400, the first gate 1110, the source electrode 1210, and the drain electrode 1310 to obtain a device body structure, as shown in fig. 3.
Optionally, the electrical connection of the whole device is realized through a conventional back-end metal interconnection process, so that the preparation of the device main body structure is completed.
It should be noted that the device body structure in this embodiment refers to a semiconductor device after two-layer gate fabrication and metal interconnection processes are completed, that is, the structure illustrated in fig. 3.
In addition, after the second gate electrode layer is prepared, the passivation layer and the gate electrode, the source electrode and the drain electrode can be prepared by a method comprising the following steps:
forming a second connecting groove and a third connecting groove on the composite channel layer by using dry etching and/or wet etching; the second connecting groove and the third connecting groove extend to the two-dimensional electron gas channel layer close to the substrate layer to be displayed;
forming an ohmic contact metal layer in the second connecting groove and the third connecting groove by using a Lift off film tearing process to form a source electrode and a drain electrode;
forming a first connecting groove on the composite channel layer by using dry etching and/or wet etching; the first connecting groove extends to the appearance of the first gate electrode structure;
depositing to form a passivation film layer;
removing part of the passivation film layer on the top surface of the second gate electrode structure and the bottom surface of the first connecting groove; visualizing a second gate electrode structure and a first gate electrode structure;
depositing gate metal on the second gate electrode structure and the first gate electrode structure to form a second gate and a first gate;
and carrying out metal interconnection technology on the second grid electrode, the first grid electrode, the source electrode and the drain electrode to obtain the device.
In addition, in other alternative embodiments, after step S800 in the above embodiments, the following steps are further included:
and carrying out temporary bonding between the front surface of the device main body structure and the temporary substrate by adopting a low-temperature bonding process.
The substrate 100 is removed from the back side of the device body structure.
Vias are formed by an etching process to introduce the source 1210 and drain 1310 electrodes to the backside of the device body structure.
The metal electrode layers of the source electrode 1210 and the drain electrode 1310 are formed on the back surface of the device body structure and within the via by metal deposition.
The temporary substrate 100 is peeled off using a debonding process.
Subsequent packaging processes such as dicing may then be performed.
And back metal interconnection.
Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.
In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific situation by those of ordinary skill in the art.
In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless otherwise indicated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (21)

1. A multi-channel HEMT device, comprising: the device comprises a substrate, a buffer layer, a base material layer, a composite channel layer and at least two gate electrode layers; the buffer layer, the substrate layer and the composite channel layer are sequentially arranged on the substrate in a laminated manner;
the composite channel layer comprises at least two-dimensional electron gas channel layers;
each two-dimensional electron gas channel layer is electrically connected with at least one gate electrode layer.
2. The multi-channel HEMT device of claim 1, wherein the number of gate electrode layers and the number of two-dimensional electron gas channel layers satisfy the following relationship:
N-1≤M≤N；
wherein N is the number of the two-dimensional electron gas channel layers, is not less than 2 and is an integer; m is the number of gate electrode layers.
3. The multi-channel HEMT device of claim 1, wherein each said two-dimensional electron gas channel layer comprises a non-doped channel layer, a barrier layer in a stacked arrangement; the non-doped channel layer is arranged close to one side of the substrate layer; the barrier layer is arranged on one side far away from the base material layer.
4. The multi-channel HEMT device of claim 3, wherein each said two-dimensional electron gas channel layer further comprises an intervening layer between said undoped channel layer and said barrier layer.
5. The multi-channel HEMT device of claim 4, wherein the undoped channel layer is an undoped GaN channel layer; and/or
The barrier layer is Al x Ga 1x An N barrier layer; wherein x = 0.1-0.5; and/or
The insertion layer is an AlN layer.
6. The multi-channel HEMT device of claim 4, wherein said undoped channel layer has a thickness of 10nm to 3000nm; and/or
The thickness of the barrier layer is 10 nm-5000 nm; and/or
The thickness of the insertion layer is 0.5nm to 5nm.
7. The multi-channel HEMT device of claim 1, wherein said substrate layer comprises a GaN layer; and/or
The buffer layer is an AlGaN buffer layer.
8. The multi-channel HEMT device as claimed in claim 7, wherein the thickness of the substrate layer is 5nm to 500nm; and/or
The thickness of the buffer layer is 500nm to 8000nm.
9. The multi-channel HEMT device of claim 1, wherein said gate electrode layer is a P-type GaN layer;
the P-type GaN layer is selected from an element-doped P-type gallium nitride layer or a P-type aluminum gallium nitride layer; the doping concentration of the element is 10 17 ~10 18 cm -3 。
10. The multi-channel HEMT device of claim 3, further comprising: a passivation layer; the passivation layer is located on one side of the barrier layer away from the substrate.
11. The multi-channel HEMT device of claim 10, wherein said at least two gate electrode layers comprise a first gate electrode layer and a second gate electrode layer;
the first gate electrode layer comprises a plurality of first gate electrode structures arrayed on the substrate layer;
the second gate electrode layer comprises a plurality of second gate electrode structures arrayed on the composite channel layer;
the passivation layer surrounds the periphery of the second gate electrode structure; the undoped channel layer close to one side of the substrate layer surrounds the periphery of the first gate electrode structure.
12. The multi-channel HEMT device of claim 11, wherein a side of said passivation layer remote from said substrate is further provided with a source electrode and a drain electrode;
the plurality of second gate electrode structures are arranged in parallel and in an interconnected mode, and the source electrode and the drain electrode are respectively positioned on two sides of one of the second gate electrode structures;
the source electrode and the drain electrode are respectively in electrical contact with the two-dimensional electron gas channel layer.
13. The multi-channel HEMT device of claim 11, wherein orthographic projections of a plurality of said first gate electrode structures and a plurality of said second gate electrode structures on said substrate are either overlappingly arranged or staggered.
14. An electronic device comprising a multi-channel HEMT device according to any one of claims 1 to 13.
15. A method of manufacturing a multi-channel HEMT device for manufacturing the multi-channel HEMT device of any one of claims 1 to 13, comprising:
providing a semi-finished product device, wherein the semi-finished product device comprises a buffer layer, a base material layer and a first gate electrode layer, which are sequentially formed on a substrate;
forming a composite channel layer and a second gate electrode layer on the semi-finished device in sequence;
wherein the composite channel layer comprises at least two-dimensional electron gas channel layers.
16. The method for manufacturing a semiconductor device according to claim 15, wherein the first gate electrode layer comprises a plurality of first gate electrode structures arrayed on the substrate layer;
the forming of the first gate electrode layer includes:
forming a first gate electrode film layer on the substrate layer;
and carrying out a patterning process on the first gate electrode film layer according to the reserved position of the first gate electrode to obtain the patterned first gate electrode structure.
17. The method of manufacturing according to claim 16, wherein each of the two-dimensional electron gas channel layers comprises a non-doped channel layer, a barrier layer, which are stacked;
the forming of the composite channel layer includes:
epitaxially growing a channel layer on the first gate electrode structure twice, wherein the channel layer covers the first gate electrode structure;
grinding the non-doped channel layer until the height of the non-doped channel layer is consistent with that of the first gate electrode structure, and obtaining a first non-doped channel layer;
forming a barrier layer on the first undoped channel layer to obtain a first two-dimensional electron gas channel layer;
epitaxially growing a layer of the non-doped channel layer on the first two-dimensional electron gas channel layer, and forming a layer of the barrier layer on the non-doped channel layer to obtain a second two-dimensional electron gas channel layer;
and repeating or not repeating the preparation steps of the two-dimensional electron gas channel layer according to the number of the two-dimensional electron gas channel layers included in the composite channel layer to obtain the composite channel layer.
18. The method according to claim 16, wherein the second gate electrode layer is prepared by a process comprising:
preparing a second gate electrode film layer on the composite channel layer;
and carrying out a patterning process on the second gate electrode film layer according to the reserved position of the second gate electrode to obtain a patterned second gate electrode structure.
19. The method for manufacturing a gate electrode according to claim 18, wherein after the second gate electrode layer is manufactured, the method comprises the following steps: forming a passivation layer;
the forming of the passivation layer includes:
forming a first connecting groove, a second connecting groove and a third connecting groove on the composite channel layer by using dry etching and/or wet etching; wherein the first connection groove extends to the appearance of the first gate electrode structure; the second connecting groove and the third connecting groove extend to the two-dimensional electron gas channel layer close to the substrate layer to be displayed;
forming an ohmic contact metal layer in the second connecting groove and the third connecting groove by using a Lift off film tearing process to form a source electrode and a drain electrode;
depositing to form a passivation film layer;
removing the top surface of the second gate electrode structure and part of the passivation film layer on the bottom surface of the first connecting groove; visualizing the second gate electrode structure and the first gate electrode structure;
depositing gate metal on the second gate electrode structure and the first gate electrode structure to form a second gate and a first gate;
and carrying out metal interconnection technology on the second grid electrode, the first grid electrode, the source electrode and the drain electrode to obtain the device.
20. The method for manufacturing a gate electrode according to claim 18, wherein after the second gate electrode layer is manufactured, the method comprises the following steps: forming a passivation layer;
the forming of the passivation layer includes:
forming a second connecting groove and a third connecting groove on the composite channel layer by using dry etching and/or wet etching; the second connecting groove and the third connecting groove extend to the two-dimensional electron gas channel layer close to the substrate layer to be displayed;
forming an ohmic contact metal layer in the second connecting groove and the third connecting groove by using a Lift off film tearing process to form a source electrode and a drain electrode;
forming a first connecting groove on the composite channel layer by using dry etching and/or wet etching; the first connecting groove extends to the appearance of the first gate electrode structure;
depositing to form a passivation film layer;
removing a part of the passivation film layer on the top surface of the second gate electrode structure and the bottom surface of the first connecting groove; visualizing the second gate electrode structure and the first gate electrode structure;
depositing gate metal on the second gate electrode structure and the first gate electrode structure to form a second gate and a first gate;
and carrying out metal interconnection technology on the second grid, the first grid, the source electrode and the drain electrode to obtain the device.
21. A method for preparing a semiconductor device according to claim 19 or 20, wherein the passivation layer is made of SiN or SiO 2 、Al 2 O 3 Any one or more of.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158923A (en) * 2015-04-17 2016-11-23 北京大学 Enhancement mode GaN FinFET based on many two dimension raceway grooves
CN208706658U (en) * 2018-08-06 2019-04-05 苏州汉骅半导体有限公司 Semiconductor devices
CN212676277U (en) * 2020-09-07 2021-03-09 中国科学技术大学 Novel AlGaN-based multi-channel field effect transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158923A (en) * 2015-04-17 2016-11-23 北京大学 Enhancement mode GaN FinFET based on many two dimension raceway grooves
CN208706658U (en) * 2018-08-06 2019-04-05 苏州汉骅半导体有限公司 Semiconductor devices
CN212676277U (en) * 2020-09-07 2021-03-09 中国科学技术大学 Novel AlGaN-based multi-channel field effect transistor

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Denomination of invention: Multichannel HEMT devices and their preparation methods, electronic devices

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