CN115602683A - Display panel and display device - Google Patents

Abstract

The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a plurality of sub-pixels and a plurality of electrostatic discharge protection units; the display panel comprises a first edge, sub-pixels adjacent to the first edge form a first sub-pixel group, the sub-pixels in the first sub-pixel group are arranged along a first direction, and an electrostatic discharge protection unit is arranged between at least part of two adjacent sub-pixels in the first sub-pixel group. In the embodiment of the application, the esd protection unit may be disposed between two adjacent sub-pixels of the first sub-pixel group, and it is not necessary to set a certain frame width on the first edge side of the display panel for disposing the esd protection unit, which is beneficial to reducing the frame width of the display panel on the first edge side. Meanwhile, the frame threshold width reserved on the first edge side of the display panel for damaging the electrostatic discharge protection unit can be avoided, so that the extremely narrow frame of the display panel is favorably realized.

Description

Display panel and display device

[ technical field ] A method for producing a semiconductor device

The present application relates to the field of display technologies, and in particular, to a display panel and a display device.

[ background ] A method for producing a semiconductor device

In recent years, narrow-frame display and frameless display of a display panel have become important development directions of high-end display.

On the way of pursuing an extremely narrow frame, some attempts have been made to omit a shift register circuit for providing signals to scan lines to reduce the width of the frame, which requires the addition of gate leads in the same direction as the extending direction of the data lines, but this solution is only suitable for low-resolution display products, otherwise, the aperture ratio of the display area will be greatly reduced, and in addition, the resolution which this solution can be used for cannot meet the current requirement of consumers for resolution. To further meet current resolution requirements and narrow bezel, flexible Organic Light Emitting Display (OLED) is gaining favor by bending the circuitry of the bezel area to the back of the display surface, thereby making the consumer appear to be frameless.

However, the flexible organic light emitting display is difficult to be applied to all current display scenes due to high price, short service life, poor stability, no resistance to high temperature and humidity, no corrosion, and the like, and thus pursuing an extremely narrow bezel is still a problem to be solved urgently in the display field.

[ application contents ]

In view of the above, embodiments of the present application provide a display panel and a display device to solve the above problems.

In a first aspect, an embodiment of the present application provides a display panel, which includes a plurality of sub-pixels and a plurality of esd protection units; the display panel comprises a first edge, sub-pixels adjacent to the first edge form a first sub-pixel group, the sub-pixels in the first sub-pixel group are arranged along a first direction, and an electrostatic discharge protection unit is arranged between at least part of two adjacent sub-pixels in the first sub-pixel group.

In one implementation manner of the first aspect, the display panel includes a second edge, the second edge is disposed opposite to the first edge along a second direction, and the second direction intersects with the first direction; the display panel comprises a pin, the pin is positioned on one side close to the second edge, and the pin is used for being electrically connected with the circuit board.

In one implementation of the first aspect, the sub-pixel comprises a light emitting device; in the first sub-pixel group, the electrostatic discharge protection unit is positioned between adjacent light emitting devices.

In one implementation manner of the first aspect, the display panel further includes a third edge and a fourth edge oppositely arranged along the first direction, and the first sub-pixel group includes sub-pixels adjacent to the third edge; and no electrostatic discharge protection unit is arranged on one side of the first sub-pixel group close to the third edge.

In one implementation of the first aspect, the first sub-pixel group further includes sub-pixels adjacent to the fourth edge; and no electrostatic discharge protection unit is arranged on one side of the first sub-pixel group close to the fourth edge.

In one implementation of the first aspect, a sub-pixel includes a pixel circuit and a light emitting device; in the same sub-pixel of the first sub-pixel group, the pixel circuit is located on one side of the light emitting device away from the first edge along a second direction, and the second direction intersects with the first direction.

In one implementation manner of the first aspect, in the first sub-pixel group, the number of sub-pixels is Q1, the number of electrostatic discharge protection units is Q2, and Q1 is less than or equal to Q2; and an electrostatic discharge protection unit is arranged between any two adjacent sub-pixels in the first sub-pixel group.

In one implementation of the first aspect, a sub-pixel includes a pixel circuit and a light emitting device; in the same sub-pixel of the first sub-pixel group, along a second direction, part of the pixel circuit is positioned on one side of the light-emitting device close to the first edge, and the second direction is crossed with the first direction; in the first sub-pixel group, a plurality of adjacent sub-pixels form a first pixel unit, and the electrostatic discharge protection unit is positioned between two adjacent first pixel units.

In one implementation manner of the first aspect, in the first sub-pixel group, the number of sub-pixels is Q1, the number of electrostatic discharge protection units is Q2, and Q1 is less than or equal to Q2; and an electrostatic discharge protection unit is arranged between any two adjacent first pixel units.

In one implementation form of the first aspect, the first pixel unit includes three adjacent sub-pixels.

In one implementation form of the first aspect, the display panel includes a first voltage signal line, and the pixel circuit includes a first portion; in the same sub-pixel of the first sub-pixel group, along the second direction, the first portion is located on one side of the light emitting device far away from the first edge, and the first portion is electrically connected with the first voltage signal line.

In one implementation manner of the first aspect, the first voltage signal line includes a first sub-voltage signal line, and the first sub-voltage signal line extends to between two adjacent sub-pixels of the same first pixel unit; one end of the first sub-voltage signal line close to the first edge is positioned between the first parts of two adjacent pixel circuits in the first pixel unit.

In a second aspect, embodiments of the present application provide a display device, including the display panel provided in the first aspect.

In one implementation manner of the second aspect, the display device is formed by splicing a plurality of display panels as provided by the first aspect; the at least two display panels are spliced along a second direction, and the second direction is intersected with the first direction.

In the embodiment of the application, the esd protection unit may be disposed between two adjacent sub-pixels of the first sub-pixel group, that is, the esd protection unit may be located in the display area of the display panel, and it is not necessary to set a certain frame width on the first edge side of the display panel for placing the esd protection unit, which is beneficial to reducing the frame width of the display panel on the first edge side. Meanwhile, because the electrostatic discharge protection unit is not required to be arranged between the first sub-pixel group and the first edge of the display panel, the frame threshold width reserved on the first edge side of the display panel for damaging the electrostatic discharge protection unit can be avoided, the frame width of the display panel on the first edge side can be further reduced, and the extremely narrow frame of the display panel can be realized.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic view of a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic view of another display panel provided in an embodiment of the present application;

fig. 3 is a schematic diagram illustrating a connection between a display panel and a circuit board according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another display panel provided in the embodiment of the present application;

fig. 5 is a schematic view of another display panel provided in an embodiment of the present application;

fig. 6 is a schematic diagram of a local layout of a first sub-pixel group according to an embodiment of the present application;

fig. 7 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 8 is a timing diagram of the pixel circuit of FIG. 7;

fig. 9 is a schematic view of another display panel provided in an embodiment of the present application;

FIG. 10 is a schematic diagram of the first sub-pixel group of FIG. 9;

fig. 11 is a schematic diagram of another pixel circuit provided in the present application;

fig. 12 is a schematic layout diagram of a first pixel unit according to an embodiment of the present disclosure;

fig. 13 is a schematic view of another display panel provided in an embodiment of the present application;

fig. 14 is a schematic view of a display device according to an embodiment of the present disclosure;

fig. 15 is a schematic view of another display device provided in an embodiment of the present application.

[ detailed description ] A

For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

In the description herein, it is to be understood that the terms "substantially", "approximately", "about", "substantially", and the like, as used in the claims and the examples herein, are intended to be generally accepted as not being precise, within the scope of reasonable process operation or tolerance.

It will be understood that, although the terms first, second, etc. may be used herein to describe directions, edges, etc., in embodiments of the present application, these directions, edges, etc. should not be limited by these terms. These terms are only used to distinguish one direction, edge, etc. from another. For example, a first direction may also be referred to as a second direction, and similarly, a second direction may also be referred to as a first direction, without departing from the scope of embodiments of the present application.

In the field of display technology, a pixel array in a display panel generally includes a plurality of columns of data lines and a plurality of rows of gate lines interleaved with the data lines. When a frame of picture is displayed, the grid lines sequentially output enable signals to control the transistors in the pixel array to be turned on, and simultaneously, data signals are provided to the pixel units of the corresponding row in the pixel array through the data lines.

In the display panel, in order to avoid the data line from being broken down by static electricity, it is usually necessary to provide an electrostatic discharge protection unit electrically connected to the far end of the data line. However, in the related art, the esd protection unit is usually located in a frame region of the display panel, and the data line of the display region needs to extend a predetermined length toward the frame region to be electrically connected to the esd protection unit. Moreover, when the large panel is cut, a certain frame threshold width needs to be reserved in order to avoid cutting the electrostatic discharge protection unit, which causes the frame area of the display panel to be large, and is not beneficial to realizing the extremely narrow frame of the display panel.

The applicant provides a solution to the problems of the prior art through intensive research.

Fig. 1 is a schematic view of a display panel according to an embodiment of the present disclosure.

In an embodiment of the present application, as shown in fig. 1, the display panel 01 includes a plurality of sub-pixels 10 and a plurality of esd protection units 20, and the esd protection units 20 are used for protecting important components in the display panel 01 from being damaged by static electricity.

For example, the esd protection unit 20 may be electrically connected to the data line for protecting the data line in the display panel 01 from being broken down by static electricity.

Specifically, the esd protection units 20 may be electrically connected to the data lines in a one-to-one correspondence, and the esd protection units 20 are electrically connected to the far ends of the data lines.

Of course, in some other embodiments, the esd protection unit 20 may also be electrically connected to the gate line for protecting the gate line from electrostatic breakdown.

The display panel 01 includes a first edge A1, and sub-pixels 10 adjacent to the first edge A1 form a first sub-pixel group P1, and the sub-pixels 10 in the first sub-pixel group P1 are arranged along a first direction X.

Alternatively, the first direction X is a row direction in the display panel 01, and the first edge A1 extends along the row direction of the display panel 01, that is, the first subpixel group P1 may be a first row of subpixels adjacent to the first edge A1 in the display panel 01.

It should be noted that, in the embodiment of the present application, the first edge A1 is a cut edge of the display panel 01, that is, the first edge A1 is an outermost edge of the display panel 01, and the first edge A1 may be an upper edge of the display panel 01.

In the first sub-pixel group P1, an electrostatic discharge protection unit 20 is disposed between at least some adjacent two sub-pixels 10.

That is, the electrostatic discharge protection unit 20 may be disposed between two adjacent sub-pixels 10 in the first sub-pixel group P1. The electrostatic discharge protection unit 20 is disposed between two adjacent sub-pixels 10, which means that the projection of the two adjacent sub-pixels 10 in the first direction X overlaps with the projection of the electrostatic discharge protection unit 20 in the first direction X.

In the embodiment of the present application, the esd protection unit 20 may be disposed between two adjacent sub-pixels 10 of the first sub-pixel group P1, that is, the esd protection unit 20 may be located in the display area of the display panel 01, and it is not necessary to set a certain frame width on the first edge A1 side of the display panel 01 for placing the esd protection unit 20, which is beneficial to reducing the frame width of the display panel 01 on the first edge A1 side. Meanwhile, since the electrostatic discharge protection unit 20 does not need to be arranged between the first subpixel group P1 and the first edge A1 of the display panel 01, the frame threshold width reserved on the first edge A1 side of the display panel 01 to destroy the electrostatic discharge protection unit 20 can be avoided, which is beneficial to further reducing the frame width of the display panel 01 on the first edge A1 side, and is beneficial to realizing an extremely narrow frame of the display panel 01.

Fig. 2 is a schematic view of another display panel provided in the embodiment of the present application, and fig. 3 is a schematic view of a connection between the display panel and a circuit board provided in the embodiment of the present application.

As shown in fig. 2, in one embodiment of the present application, the display panel 01 includes a second edge A2, and the second edge A2 is disposed opposite to the first edge A1 along a second direction Y, which intersects the first direction X.

Alternatively, the second direction Y is a column direction of the display panel 01.

It should be noted that, in the embodiment of the present application, the second edge A2 is a cut edge of the display panel 01, that is, the second edge A2 is an outermost edge of the display panel 01, and the second edge A2 may be a lower edge of the display panel 01.

The display panel 01 includes a pin BY, which is located on a side of the display panel 01 near the second edge A2 and is used for electrically connecting with the circuit board 02. The Circuit board 02 is used to provide various signals for driving the display panel 01 to display, and the Circuit board 02 may be a Flexible Printed Circuit (FPC), a Chip On Film (COF), a transfer Printed Circuit board (FPC), or the like.

In the embodiment of the present application, the signal provided by the circuit board 02 enters the display panel 01 through the second edge A2, the first edge A1 may be a far-end edge of the display panel 01 for receiving the signal, and the number of the traces of the display panel 01 on the first edge A1 side is relatively small, so that it is possible for the esd protection unit 20 to be disposed in the first subpixel group P1 close to the first edge A1.

In an implementation manner of the embodiment of the present application, as shown in fig. 3, the circuit board 02 may be located on one side of the backlight surface of the display panel 01, and the pin BY is electrically connected to the circuit board 02 through the side trace CL. Of course, in some other embodiments, the circuit board 02 may also be directly bonded to the pins BY, and then the circuit board 02 is bent to the backlight side of the display panel 01.

Fig. 4 is a schematic view of another display panel according to an embodiment of the present disclosure.

In one embodiment of the present application, as shown in fig. 4, the sub-pixel 10 includes a pixel circuit 11 and light emitting devices 12, and in the first sub-pixel group P1, the electrostatic discharge protection unit 20 is located between the adjacent light emitting devices 12.

With reference to fig. 4, the display panel 01 further includes a plurality of first signal lines DL1, the first signal lines DL1 extend along the second direction Y, and the plurality of first signal lines DL1 are arranged along the first direction X.

The first signal line DL1 is electrically connected to the pixel circuit 11 in the sub-pixel 10, and may be used to transmit a data signal to the pixel circuit 11, that is, the first signal line DL1 may be a data line in the display panel 01.

It is to be understood that the pixel circuits 11 in the same column of sub-pixels 10 may be electrically connected to the same first signal line DL1, and the first signal line DL1 generally extends from the second edge A2 side to between the pixel circuits 11 adjacent to the first edge A1, that is, in the first sub-pixel group P1, the first signal line DL1 is generally included between two adjacent pixel circuits 11.

Therefore, in the embodiment of the present application, the esd protection unit 20 is disposed between the adjacent light emitting devices 12 in the first sub-pixel group P1, so as to prevent the wiring space between the pixel circuits 11 from being tight, which is beneficial to the preparation of the display panel 01.

In an application scenario of the embodiment of the present application, the esd protection units 20 may be electrically connected to the first signal lines DL1 in a one-to-one correspondence, for protecting the first signal lines DL1 from being broken down by static electricity.

Specifically, as shown in fig. 4, the esd protection unit 20 may be electrically connected to one end (far end of the first signal line DL 1) of the first signal line DL1 close to the first edge A1, and protect the first signal line DL1 from electrostatic breakdown without affecting the normal signal transmission of the first signal line DL1.

In an embodiment of the present application, with continued reference to fig. 1, the display panel 01 further includes a third edge A3 and a fourth edge A4 oppositely disposed along the first direction X. The first pixel group P1 includes a sub-pixel 10 adjacent to the third edge A3, and there is no esd protection unit 20 on a side of the first pixel group P1 close to the third edge A3.

It should be noted that, in the embodiment of the present application, the third edge A3 and the fourth edge A4 are two cut edges of the display panel 01 that are oppositely disposed along the first direction X, that is, the third edge A3 and the fourth edge A4 are two outermost edges of the display panel 01, and the third edge A3 and the fourth edge A4 may be a left edge and a right edge of the display panel 01, respectively.

In the embodiment of the present application, the esd protection unit 20 is no longer disposed on one side of the first sub-pixel group P1 close to the third edge A3, and a certain frame width does not need to be disposed on the third edge A3 side of the display panel 01 for disposing the esd protection unit 20, which is beneficial to reducing the frame width of the display panel 01 on the third edge A3 side. Meanwhile, since the electrostatic discharge protection unit 20 does not need to be arranged between the first subpixel group P1 and the third edge A3 of the display panel 01, the frame threshold width reserved on the third edge A3 side of the display panel 01 to destroy the electrostatic discharge protection unit 20 can be avoided, which is beneficial to further reducing the frame width of the display panel 01 on the third edge A3 side, and is beneficial to further realizing the extremely narrow frame of the display panel 01.

In addition, since the esd protection unit 20 may be electrically connected to the first signal line DL1, when the esd protection unit 20 is no longer disposed on a side of the first sub-pixel group P1 close to the third edge A3, the first signal line DL1 may also be no longer disposed on a side of the first sub-pixel group P1 close to the third edge A3, and the first signal line DL1 electrically connected to the sub-pixel adjacent to the third edge A3 may be disposed on a side of the sub-pixel 10 away from the third edge A3, so as to reduce a frame width disposed on the third edge side A3 of the display panel 01 for disposing the first signal line DL1, and facilitate further implementing an extremely narrow frame of the display panel 01.

Referring to fig. 1, in an embodiment of the present disclosure, the first pixel group P1 further includes a sub-pixel 10 adjacent to the fourth edge A4, and there is no esd protection unit 20 on a side of the first pixel group P1 close to the fourth edge A4.

In the embodiment of the present application, the esd protection unit 20 is no longer disposed on a side of the first sub-pixel group P1 close to the fourth edge A4, so that a certain frame width does not need to be disposed on the fourth edge A4 side of the display panel 01 for disposing the esd protection unit 20, which is beneficial to reducing the frame width of the display panel 01 on the fourth edge A4 side. Meanwhile, since the electrostatic discharge protection unit 20 does not need to be arranged between the first subpixel group P1 and the fourth edge A4 of the display panel 01, a frame threshold width reserved on the fourth edge A4 side of the display panel 01 to destroy the electrostatic discharge protection unit 20 can be avoided, which is beneficial to further reducing the frame width of the display panel 01 on the fourth edge A4 side, and is beneficial to further realizing an extremely narrow frame of the display panel 01.

In addition, since the esd protection unit 20 may be electrically connected to the first signal line DL1, when the esd protection unit 20 is no longer disposed on a side of the first sub-pixel group P1 close to the fourth edge A4, the first signal line DL1 may also be no longer disposed on a side of the first sub-pixel group P1 close to the fourth edge A4, and the first signal line DL1 electrically connected to the sub-pixel adjacent to the fourth edge A4 may be disposed on a side of the sub-pixel 10 away from the fourth edge A4, so as to reduce a frame width disposed on the fourth edge side A4 of the display panel 01 for disposing the first signal line DL1, which is beneficial to further realizing an extremely narrow frame of the display panel 01.

Fig. 5 is a schematic diagram of another display panel provided in the embodiment of the present application, and fig. 6 is a schematic diagram of a local layout of a first sub-pixel group provided in the embodiment of the present application.

In one embodiment of the present application, as shown in fig. 4 and 5, the sub-pixel 10 includes a pixel circuit 11 and a light emitting device 12, and the pixel circuit 11 is used for driving the light emitting device 12 to emit light.

In the same subpixel 10 of the first subpixel group P1, the pixel circuit 11 is located on a side of the light emitting device 12 away from the first edge A1 along a second direction Y, which intersects the first direction X.

Alternatively, the first direction X is a row direction in the display panel 01, and the second direction Y is a column direction in the display panel 01.

The light emitting device 12 may be a sub-millimeter light emitting diode (Mini-LED), and the pixel circuit 11 may be a common 7T1C (including seven transistors and a storage capacitor) circuit. Of course, in some other embodiments, the pixel circuit 11 may also include more transistors and storage capacitors relative to the 7T1C circuit, for example, the pixel circuit 11 may be a 13T2C (including thirteen transistors and two storage capacitors) circuit.

It should be noted that in the sub-pixels 10 outside the first sub-pixel group P1, along the second direction Y, the pixel circuits 11 of the same sub-pixel 10 may be located on the side of the included light emitting device 12 close to the first edge A1. Of course, in the sub-pixels 10 outside the first sub-pixel group P1, along the second direction Y, the pixel circuits 11 of the same sub-pixel 10 may also be located on the side of the light emitting device 12 included therein away from the first edge A1. This is not particularly limited in the embodiments of the present application.

As shown in fig. 5 and 6, the display panel 01 further includes a plurality of second signal lines DL2 extending along the second direction Y, and the second signal lines DL2 are electrically connected to the sub-pixels 10.

Specifically, as shown in fig. 6, the second signal line DL2 may be electrically connected to the pixel circuit 11 or the light emitting device 12 through a connection line extending in the second direction X. The second signal line DL2 includes a first voltage signal line PVDD electrically connectable to the pixel circuit 11 and a second voltage signal line PVEE electrically connected to the light emitting device 12.

Further, the light emitting device 12 may include two connection points Z1 and Z2, the connection point Z1 is electrically connected to the pixel circuit 11, the connection point Z2 is electrically connected to the second voltage signal line PVEE, and the connection point Z2 is located at a side of the connection point Z1 away from the first edge A1, so as to ensure that in the first sub-pixel group P1, the second voltage signal line PVEE does not need to extend to a region closer to the first edge A1, so that there is sufficient space between two adjacent light emitting devices 12.

In the embodiment of the present application, the pixel circuit 11 of the sub-pixel 10 in the first sub-pixel group P1 is disposed at a side of the light emitting device 12 electrically connected to the pixel circuit 11, which is far away from the first edge A1, so that the first voltage signal line PVDD electrically connected to the pixel circuit 11 may not need to extend to an area close to the first edge A1, and compared with a configuration mode in which the pixel circuit 11 is disposed at a side of the light emitting device 12 close to the first edge A1, the extension length of the first voltage signal line PVDD is shortened in the embodiment of the present application, and does not need to extend to between two adjacent light emitting devices 12, thereby reserving a space for the esd protection unit 20 disposed between two adjacent light emitting devices 12 of the first sub-pixel group P1.

In addition, since the pixel circuit 11 is located on the side of the light emitting device 12 away from the first edge A1 in the sub-pixel 10 of the first sub-pixel group P1, in the first sub-pixel group P1, there is no need to provide a device (such as a transistor or a storage capacitor) of the pixel circuit 11 on the side of the light emitting device 12 close to the first edge A1, that is, there is no need to provide a device of the pixel circuit 11 between the light emitting device 12 adjacent to the first edge A1 and the first edge A1, so that there is no need to provide a trace of the pixel circuit 11 between two adjacent light emitting devices 12 of the first sub-pixel group P1, and the number of traces between two adjacent light emitting devices 12 in the first sub-pixel group P1 is very small or even no trace, so as to reserve a space between any two adjacent light emitting devices 12 for the electrostatic discharge protection unit 20 to be disposed.

In the embodiment of the present application, the esd protection unit 20 may be disposed between any two adjacent sub-pixels 10 in the first sub-pixel group P1.

Fig. 7 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure, and fig. 8 is a timing diagram of the pixel circuit shown in fig. 7.

For clarity of explanation of the technical solutions of the embodiments of the present application, the following describes an operation process of the pixel circuit shown in fig. 7 with reference to fig. 7 and 8.

As shown in fig. 7, the pixel circuit 11 includes a drive transistor Md for supplying a light emission drive current to the light emitting device 12, a data voltage write transistor M1, a power voltage write transistor M2, a first reset transistor M3, a threshold voltage capture transistor M4, a light emission control transistor M5, and a second reset transistor M6.

The source of the data voltage writing transistor M1 is electrically connected to the first signal line DL1, the drain is electrically connected to the source of the driving transistor Md, and the gate is electrically connected to the first scan line S1; the source of the power supply voltage writing transistor M2 is electrically connected to the first voltage signal line PVDD, the drain is electrically connected to the source of the drive transistor Md, and the gate is electrically connected to the emission control signal line EM; the source of the first reset transistor M3 is electrically connected to the reset signal line SL1, the drain is electrically connected to the gate of the drive transistor Md, and the gate is electrically connected to the second scanning line S2; the source electrode of the threshold voltage grabbing transistor M4 is electrically connected with the drain electrode of the driving transistor Md, the drain electrode is electrically connected with the grid electrode of the driving transistor Md, and the grid electrode is electrically connected with the first scanning line S1; the light emission control transistor M5 has a source electrically connected to the drain of the drive transistor Md, a drain electrically connected to the first pole of the light emitting device 12, and a gate electrically connected to the light emission control signal line EM; the second reset transistor M6 has a source electrically connected to the reset signal line SL1, a drain electrically connected to the first pole of the light emitting device 12, a gate electrically connected to the first scan line S1, and a second pole of the light emitting device 12 electrically connected to the second voltage signal line PVEE.

Note that, the data voltage writing transistor M1, the power voltage writing transistor M2, the first reset transistor M3, the threshold voltage grasping transistor M4, the emission control transistor M5, and the second reset transistor M6 are all P-type transistors, which will be described below as an example.

In one frame of the display panel 01, the operation process of the pixel circuit 11 includes a reset phase t1, a data writing phase t2 and a light emitting phase t3.

In the reset stage t1, the second scan line S2 transmits a turn-on signal, i.e., a low level signal, and the first reset transistor M3 is turned on; the first scanning line S1 and the emission control signal line EM transmit off signals, i.e., high level signals, and the data voltage writing transistor M1, the threshold voltage grasping transistor M4, the power voltage writing transistor M2, the emission control transistor M5, and the second reset transistor M6 are turned off. Meanwhile, the reset signal line SL1 transmits a reset voltage Vref, and the reset voltage Vref is transmitted to the gate of the drive transistor Md through the turned-on first reset transistor M3, thereby completing the reset of the gate of the drive transistor Md.

In the data writing stage t2, the first scan line S1 transmits a turn-on signal, i.e., a low level signal, and the data voltage writing transistor M1, the threshold voltage capturing transistor M4, and the second reset transistor M6 are turned on; the second scanning line S2 and the emission control signal line EM transmit off signals, i.e., high level signals, and the first reset transistor M3, the power supply voltage writing transistor M2, and the emission control transistor M5 are turned off. Meanwhile, the first signal line DL1 transmits a data voltage Vdata, at the start point of the data writing stage t2, the gate potential of the driving transistor Md is the reset voltage Vref, the source potential of the driving transistor Md is the data voltage Vdata, the potential difference between the source and the gate of the driving transistor Md is (Vdata-Vref), and the potential difference between the source and the gate of the driving transistor Md is greater than 0, so that the driving transistor Md is turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Md through the turned-on driving transistor Md and the turned-on threshold voltage capture transistor M4, so that the gate potential of the driving transistor Md gradually increases. When the gate voltage of the driving transistor Md is equal to (Vdata- | Vth |), the driving transistor Md is turned off. Where Vth is the threshold voltage of the drive transistor Md.

At the same time, the reset voltage Vref resets the first pole of the light emitting device 12 through the turned-on second reset transistor M6. Optionally, the light emitting device 12 is a sub-millimeter light emitting diode (Mini-LED), and the reset voltage Vref resets the anode of the sub-millimeter light emitting diode through the turned-on second reset transistor M6.

In the light emitting period t3, the first scan line S1 and the second scan line S2 transmit turn-off signals, i.e., high level signals, and the data voltage writing transistor M1, the first reset transistor M3, the threshold voltage capturing transistor M4, and the second reset transistor M6 are turned off; the emission control signal line EM transmits a turn-on signal, i.e., a low level signal, and the power supply voltage writing transistor M2 and the emission control transistor M5 are turned on. Meanwhile, the first voltage signal line PVDD transmits the power supply voltage, that is, the potential of the source of the driving transistor Md is the power supply voltage. Since the potential of the power supply voltage is greater than the potential of the data voltage Vdata, the driving transistor Md generates a driving current and transmits the driving current to the light emitting device 12 through the light emission controlling transistor M5, controlling the light emitting device 12 to emit light.

In fig. 7, the first reset transistor M3 and the threshold voltage capture transistor M4 may have a single-gate structure or a double-gate structure.

In an embodiment of the present application, in the first sub-pixel group P1, the number of sub-pixels 10 is Q1, the number of the esd protection units 20 is Q2, and Q1 ≦ Q2. An electrostatic discharge protection unit 20 is disposed between any two adjacent sub-pixels 10 in the first sub-pixel group P1.

In the embodiment of the present application, the esd protection unit 20 can be uniformly disposed in the first sub-pixel group P1, which is beneficial to ensuring that the light emitting devices 12 in the first sub-pixel group P1 can be uniformly disposed, so as to ensure the uniformity of the brightness of the display panel 01.

It is understood that the esd protection units 20 may be electrically connected to the data lines connected to the sub-pixels 10 in a one-to-one correspondence to protect the data lines from electrostatic damage; in addition, in order to improve the display quality of the display panel 01, a bias voltage signal line electrically connected to the sub-pixel 10 is also generally provided, and therefore, in the first sub-pixel group P1, an electrostatic discharge protection unit 20 electrically connected to the bias voltage signal line may be further provided to protect the bias voltage signal line from electrostatic damage; furthermore, the esd protection unit 20 for protecting the scan lines (such as the first scan line S1 in the above embodiment) electrically connected to the pixel circuit 11 can also be disposed in the first sub-pixel group P1. Therefore, in the first sub-pixel group P1, the number of the esd protection units 20 is usually not less than the number of the sub-pixels 10 included in the first sub-pixel group P1.

In the embodiment of the present application, since Q1 is less than or equal to Q2, and the number of the esd protection units 20 is greater than the number of gaps between two adjacent sub-pixels 10 in the first sub-pixel group P1, the number of the esd protection units 20 disposed in a partial gap may be greater than the number of the esd protection units 20 disposed in another partial gap.

For example, as shown in fig. 4 and 5, a gap between two adjacent sub-pixels 10 in the first sub-pixel group P1 is M1, and when Q1= Q2, two esd protection units 20 may be disposed in one gap M1 in the first sub-pixel group P1, and one esd protection unit 20 may be disposed in the other gap M1.

Further, with continued reference to fig. 5, in the display panel 01, three sub-pixels 10 adjacent to each other along the first direction X may form a pixel Pix, the three sub-pixels 10 forming the pixel Pix may be a blue sub-pixel, a green sub-pixel, and a red sub-pixel, respectively, the blue sub-pixel, the red sub-pixel, and the green sub-pixel are used as three primary colors, and can emit light to generate a white dot, and the full-color display is realized by controlling the luminance ratio between the sub-pixels. Therefore, the pixel Pix may be a minimum unit of color values allocated in the display panel 01, the gap between the adjacent pixels Pix may be set to be larger than the gap between the sub-pixels 10 inside the pixel Pix, and when the number of the esd protection cells 20 in the first sub-pixel group P1 is larger than the gap M1, the number of the esd protection cells 20 set between the adjacent two pixels Pix may be larger than the number of the esd protection cells 20 set between the adjacent sub-pixels 10 inside the pixel Pix.

Fig. 9 is a schematic diagram of another display panel provided in the embodiment of the present application, fig. 10 is a schematic diagram of a first sub-pixel group in fig. 9, fig. 11 is a schematic diagram of another pixel circuit provided in the embodiment of the present application, and fig. 12 is a layout schematic diagram of a first pixel unit provided in the embodiment of the present application.

In one embodiment of the present application, as shown in fig. 9 and 10, the sub-pixel 10 includes a pixel circuit 11 and a light emitting device 12, and the pixel circuit 11 is used for driving the light emitting device 12 to emit light.

In the same sub-pixel 10 of the first sub-pixel group P1, along the second direction Y, a portion of the pixel circuit 11 is located on a side of the light emitting device 12 close to the first edge A1, and another portion of the pixel circuit 11 may be located on a side of the light emitting device 12 far from the first edge A1. The second direction Y intersects the first direction X, which may be a row direction in the display panel 01, and the second direction Y may be a column direction in the display panel 01.

Specifically, as shown in fig. 10, in the first sub-pixel group P1, the pixel circuit 11 may include a first portion 11A and a second portion 11B electrically connected to each other, the first portion 11A being located on a side of the light emitting device 12 away from the first edge A1, the second portion 11B being located on a side of the light emitting device 12 close to the first edge A1.

The light emitting device 12 may be a sub-millimeter light emitting diode (Mini-LED), and the pixel circuit 11 may be a common 7T1C (including seven transistors and one storage capacitor) circuit. Of course, in some other embodiments, the pixel circuit 11 may further include more transistors and storage capacitors relative to the 7T1C circuit, for example, the pixel circuit 11 may also be a 13T2C (including thirteen transistors and two storage capacitors) circuit.

In the first sub-pixel group P1, a plurality of adjacent sub-pixels 10 form a first pixel unit 100, and the esd protection unit 20 is located between two adjacent first pixel units 100. The esd protection units 20 located between two adjacent first pixel units 100 are respectively connected to the adjacent data lines.

Alternatively, the first pixel unit 100 includes three adjacent sub-pixels 10, and the emission colors of the three adjacent sub-pixels 10 are different from each other.

For example, the three sub-pixels 10 in the first pixel unit 100 may be a blue sub-pixel, a red sub-pixel, and a green sub-pixel, respectively. The blue sub-pixel, the red sub-pixel and the green sub-pixel can emit light to generate a white point as three primary colors, and full-color display is realized by controlling the luminance ratio among the sub-pixels.

It can be understood that the pixel circuit 11 has more traces, and especially when the pixel circuit 11 includes more transistors, the structure of the pixel circuit 11 is relatively complex and the number of signal lines connected thereto is large. In the first sub-pixel group P1, when a portion of the pixel circuit 11 is located on a side of the light emitting device 12 close to the first edge A1, a routing between the portion and a portion of the pixel circuit 11 located on a side of the light emitting device 12 far from the first edge A1 is generally required to pass through a gap between two adjacent light emitting devices 12.

For example, as shown in fig. 11, the pixel circuit 11 includes transistors T1 to T13 and capacitors C1, C2. The connection of the transistors T1-T13 and the capacitors C1, C2 is shown in fig. 11 and will not be described again. The transistors T1 to T7 and the capacitor C1 may form a first portion 11A of the pixel circuit 11, the first portion 11A is electrically connected to the first voltage signal line PVDD, the first fixed potential signal line Data, the reset signal line SL1, and the light emitting device 12, and the first portion 11A is used for driving the light emitting device 12 to emit light.

The transistors T8 to T13 and the capacitor C2 may constitute a second portion 11B of the pixel circuit 11, the second portion 11B being electrically connected to the first node N1 in the first portion 11A, and further, the second portion 11B being electrically connected to the first signal line DL1, the second fixed-potential signal line VH2, the reset signal line SL1, and the pulse signal line Sweep which may transmit a triangular wave signal. The second portion 11B may be used to adjust the light emitting time of the light emitting device 12.

As shown in fig. 12, in the same first pixel unit 100, the trace between the first portion 11A and the second portion 11B of the pixel circuit 11 passes through the gap between two adjacent light emitting devices 12. Also, the connection line of the second portion 11B and the first signal line SL1, the reset signal line SL1, etc. may pass through the gap between the adjacent two light emitting devices 12.

In the embodiment of the present application, the esd protection unit 20 is disposed between two adjacent first pixel units 100, so that the esd protection unit 20 can be prevented from occupying the gap between two adjacent light emitting devices 12 in the same first pixel unit 100, and the gap space between two adjacent light emitting devices 12 in the same first pixel unit 100 is ensured to be large, so as to meet the routing requirement of the pixel circuit 11. At this time, the first signal line DL1 (data line) is routed from above the sub-pixel 10 to the corresponding esd protection unit 20 and electrically connected thereto.

Moreover, the routing of the pixel circuit 11 is concentrated inside the first pixel unit 100, so that the gap between two adjacent first pixel units 100 is relatively large, thereby providing a space for the esd protection unit 20 to be disposed between two adjacent first pixel units 100.

Fig. 13 is a schematic view of another display panel provided in an embodiment of the present application.

In one implementation manner of the embodiment of the present application, as shown in fig. 13, the display panel 01 includes a plurality of second signal lines DL2 extending along the second direction Y, and the second signal lines DL2 are electrically connected to the sub-pixels 10.

As shown in connection with fig. 12, the second signal line DL2 may be electrically connected to the pixel circuit 11 or the light emitting device 12 through a connection line extending in the second direction X. The second signal line DL2 includes a first voltage signal line PVDD electrically connectable to the pixel circuit 11 and a second voltage signal line PVEE electrically connected to the light emitting device 12.

The pixel circuit 11 includes a first portion 11A, the first portion 11A being located on a side of the light emitting device 12 away from the first edge A1 in the second direction Y in the same subpixel 10 of the first subpixel group P1, the first portion 11A being electrically connected to the first voltage signal line PVDD.

It should be noted that in the sub-pixels 10 outside the first sub-pixel group P1, the pixel circuits 11 of the same sub-pixel 10 may be located on the same side of the light emitting device 12 included therein along the second direction Y. For example, in fig. 13, in the sub-pixels 10 outside the first sub-pixel group P1, along the second direction Y, the pixel circuits 11 of the same sub-pixel 10 are all located on the side of the light emitting device 12 included therein near the first edge A1.

Of course, in the sub-pixels 10 outside the first sub-pixel group P1, along the second direction Y, the pixel circuits 11 of the same sub-pixel 10 may be located on the side of the included light emitting device 12 far from the first edge A1, or the pixel circuits 11 of the same sub-pixel 10 may be located on the two sides of the included light emitting device 12. This is not particularly limited in the embodiments of the present application.

In this implementation, in the first sub-pixel group P1, since the first voltage signal line PVDD is electrically connected to the first portion 11A of the pixel circuit 11 that is farther from the first edge A1, the first voltage signal line PVDD does not need to extend to a region closer to the first edge A1, and the extension length of the first voltage signal line PVDD can be shortened, so that a space is reserved for the esd protection unit 20 to be disposed between two adjacent first pixel units 100.

Further, the light emitting device 12 may include two connection points Z1 and Z2, the connection point Z1 is electrically connected to the pixel circuit 11, the connection point Z2 is electrically connected to the second voltage signal line PVEE, and the connection point Z2 is located at a side of the connection point Z1 away from the first edge A1, so as to ensure that in the first sub-pixel group P1, the second voltage signal line PVEE does not need to extend to a region closer to the first edge A1, so that there is sufficient space between two adjacent first pixel units 100.

In an embodiment of the present application, with reference to fig. 12, the first voltage signal line PVDD includes a first sub-voltage signal line PVDD1, and the first sub-voltage signal line PVDD1 extends between two adjacent sub-pixels 10 of the first pixel unit 100. The first sub-voltage signal line PVDD1 may be a portion of the first voltage signal line PVDD located inside the first pixel cell 100.

One end of the first sub-voltage signal line PVDD1 close to the first edge A1 is located between the first portions 11A of two adjacent pixel circuits 11 in the first pixel unit 100.

In this embodiment, one end of the first sub-voltage signal line PVDD1 close to the first edge A1 is located between the first portions 11A of the two adjacent pixel circuits 11 in the first pixel unit 100, so that the first sub-voltage signal line PVDD1 can be prevented from occupying a gap between the two adjacent light emitting devices 12 in the same first pixel unit 100, and thus it is further ensured that a gap space between the two adjacent light emitting devices 12 in the same first pixel unit 100 is large, so as to further meet the routing requirement of the pixel circuits 11.

In an embodiment of the present application, with continued reference to fig. 13, in the first sub-pixel group P1, the number of sub-pixels 10 is Q1, the number of the esd protection units 20 is Q2, and Q1 ≦ Q2. An electrostatic discharge protection unit 20 is disposed between any two adjacent first pixel units 100 in the first sub-pixel group P1.

In the embodiment of the present application, the esd protection unit 20 can be uniformly disposed in the first sub-pixel group P1, which is favorable for ensuring that the first pixel unit 100 in the first sub-pixel group P1 can be uniformly disposed, thereby ensuring the uniformity of the brightness of the display panel 01.

It is understood that the esd protection units 20 may be electrically connected to the data lines connected to the sub-pixels 10 in a one-to-one correspondence to protect the data lines from electrostatic damage; in addition, in order to improve the display quality of the display panel 01, a bias voltage signal line electrically connected to the sub-pixel 10 is also generally provided, and therefore, in the first sub-pixel group P1, an electrostatic discharge protection unit 20 electrically connected to the bias voltage signal line is also provided to protect the bias voltage signal line from electrostatic damage; furthermore, the esd protection unit 20 for protecting the scan lines (such as the first scan line S1 in the above embodiment) electrically connected to the pixel circuit 11 can also be disposed in the first sub-pixel group P1. Therefore, in the first sub-pixel group P1, the number of the esd protection units 20 is usually not less than the number of the sub-pixels 10 included in the first sub-pixel group P1.

In the embodiment of the present application, since Q1 is less than or equal to Q2, and the number of the esd protection units 20 is greater than the number of gaps between two adjacent first pixel units 100 in the first subpixel group P1, the number of the esd protection units 20 in a partial gap may be greater than the number of the esd protection units 20 in another partial gap.

For example, as shown in fig. 13, the gap between two adjacent first pixel units 100 is M2, and when Q1= Q2 and the first pixel unit 100 includes three sub-pixels 10, the number of the electrostatic discharge protection units 20 is three more than three times the number of the gaps M2. At this time, four esd protection units 20 may be disposed in the three gaps M2, and three esd protection units 20 may be disposed in the other gaps M. To ensure that the first pixel units 100 can be distributed more uniformly in the display panel 01.

Fig. 14 is a schematic view of a display device according to an embodiment of the present disclosure.

As shown in fig. 14, an embodiment of the present application provides a display device 02, and the display device 02 includes the display panel 01 provided in the above embodiment. The display device 02 provided in the embodiment of the present application may be an electronic device such as a mobile phone, a computer, a television, a smart wearable device (e.g., a smart watch), and a vehicle-mounted display device, and the embodiment of the present application is not particularly limited.

In the display device 02, the esd protection unit 20 may be disposed between two adjacent sub-pixels 10 of the first sub-pixel group P1, that is, the esd protection unit 20 may be located in the display area of the display panel 01, and it is not necessary to set a certain frame width on the first edge A1 side of the display panel 01 for placing the esd protection unit 20, which is beneficial to reduce the frame width of the display panel 01 on the first edge A1 side. Meanwhile, since the electrostatic discharge protection unit 20 does not need to be arranged between the first subpixel group P1 and the first edge A1 of the display panel 01, a frame threshold width reserved on the first edge A1 side of the display panel 01 to destroy the electrostatic discharge protection unit 20 can be avoided, which is beneficial to further reducing the frame width of the display panel 01 on the first edge A1 side, and is beneficial to realizing an extremely narrow frame of the display panel 01.

Fig. 15 is a schematic view of another display device provided in an embodiment of the present application.

In an embodiment of the present application, as shown in fig. 15, the display device 02 may be formed by splicing a plurality of display panels 01 provided in the above embodiments. At least two display panels 01 are spliced along a second direction Y, and the second direction Y is intersected with the first direction X. The second edge A2 of the previous display panel 01 may meet the first edge A1 of the next display panel 01. Illustratively, the tiled display device 02 may be a light emitting diode tiled screen, a movie screen, a remote-viewing electronic product, and the like, and the embodiment of the present application is not limited in particular.

In the embodiment of the present application, it can be known from the structure of the display panels 01 that the frames of the display panels 01 on the first edge A1 side are smaller, and then for two adjacent display panels 01 in the second direction Y, the sum of the widths occupied by the frame of the previous display panel 01 on the second edge A2 side and the frame of the next display panel 01 on the first edge A1 side can be reduced, which is beneficial to realizing that the pixel units in the whole spliced display device 02 tend to be arranged at equal intervals, weakening the visual seam, and realizing seamless splicing between the display panels 01.

The above description is only a preferred embodiment of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (14)

1. The display panel is characterized by comprising a plurality of sub-pixels and a plurality of electrostatic discharge protection units;

the display panel comprises a first edge, the sub-pixels adjacent to the first edge form a first sub-pixel group, the sub-pixels in the first sub-pixel group are arranged along a first direction, and the electrostatic discharge protection unit is arranged between at least part of two adjacent sub-pixels in the first sub-pixel group.

2. The display panel according to claim 1, wherein the display panel includes a second edge disposed opposite to the first edge in a second direction, the second direction intersecting the first direction;

the display panel comprises a pin, the pin is positioned on one side close to the second edge, and the pin is used for being electrically connected with the circuit board.

3. The display panel according to claim 1, wherein the sub-pixel comprises a light emitting device; in the first sub-pixel group, the electrostatic discharge protection unit is positioned between the adjacent light emitting devices.

4. The display panel according to claim 1, wherein the display panel further comprises a third edge and a fourth edge oppositely arranged along the first direction, and the first sub-pixel group comprises the sub-pixels adjacent to the third edge; and the electrostatic discharge protection unit is not arranged on one side of the first sub-pixel group close to the third edge.

5. The display panel according to claim 4, wherein the first sub-pixel group further comprises the sub-pixel adjacent to the fourth edge; and the electrostatic discharge protection unit is not arranged on one side of the first sub-pixel group close to the fourth edge.

6. The display panel according to claim 1, wherein the sub-pixel includes a pixel circuit and a light-emitting device; in the same sub-pixel of the first sub-pixel group, the pixel circuit is located on one side of the light-emitting device far away from the first edge along a second direction, and the second direction intersects with the first direction.

7. The display panel according to claim 6, wherein in the first sub-pixel group, the number of sub-pixels is Q1, the number of ESD protection units is Q2, and Q1 ≦ Q2;

the electrostatic discharge protection unit is arranged between any two adjacent sub-pixels in the first sub-pixel group.

8. The display panel according to claim 1, wherein the sub-pixel includes a pixel circuit and a light-emitting device; in the same sub-pixel of the first sub-pixel group, along a second direction, the part of the pixel circuit is positioned on one side of the light-emitting device close to the first edge, and the second direction intersects with the first direction;

in the first sub-pixel group, a plurality of adjacent sub-pixels form a first pixel unit, and the electrostatic discharge protection unit is positioned between two adjacent first pixel units.

9. The display panel according to claim 8, wherein in the first sub-pixel group, the number of sub-pixels is Q1, the number of the ESD protection units is Q2, and Q1 ≦ Q2;

the electrostatic discharge protection unit is arranged between any two adjacent first pixel units.

10. The display panel according to claim 8, wherein the first pixel unit comprises three adjacent sub-pixels.

11. The display panel according to claim 8, wherein the display panel comprises a first voltage signal line, and wherein the pixel circuit comprises a first portion;

in the same sub-pixel of the first sub-pixel group, along the second direction, the first portion is located on a side of the light emitting device away from the first edge, and the first portion is electrically connected to the first voltage signal line.

12. The display panel according to claim 11, wherein the first voltage signal line comprises a first sub-voltage signal line extending between two adjacent sub-pixels of the same first pixel unit;

wherein an end of the first sub-voltage signal line near the first edge is located between the first portions of two adjacent pixel circuits in the first pixel unit.

13. A display device characterized by comprising the display panel according to any one of claims 1 to 12.

14. The display device according to claim 13, wherein a plurality of display panels according to any one of claims 1 to 12 are spliced; the display panel comprises at least two display panels, wherein the at least two display panels are spliced along a second direction, and the second direction is intersected with the first direction.

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